Hi,
This enables PCIe network card and the PCIe slot for the RK3588 EVB1.
There is one more PCIe lane being used for a WLAN card, but I did not
yet get that working.
-- Sebastian
Sebastian Reichel (2):
arm64: dts: rockchip: rk3588-evb1: add PCIe2 network controller
arm64: dts: rockchip: rk3588-evb1: add PCIe3 bus
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
--
2.40.1
The RK3588 EVB1 has a second network card, which is connected
via PCIe2. This adds support for that.
Signed-off-by: Sebastian Reichel <[email protected]>
---
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
index 229a9111f5eb..23bef9faa690 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -29,6 +29,26 @@ backlight: backlight {
pwms = <&pwm2 0 25000 0>;
};
+ pcie20_avdd0v85: pcie20-avdd0v85-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd0v85";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&avdd_0v85_s0>;
+ };
+
+ pcie20_avdd1v8: pcie20-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -87,6 +107,10 @@ &combphy0_ps {
status = "okay";
};
+&combphy2_psu {
+ status = "okay";
+};
+
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -163,7 +187,20 @@ rgmii_phy: ethernet-phy@1 {
};
};
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>;
+ status = "okay";
+};
+
&pinctrl {
+ rtl8111 {
+ rtl8111_isolate: rtl8111-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -177,6 +214,12 @@ hym8563_int: hym8563-int {
};
};
+ pcie2 {
+ pcie2_1_rst: pcie2-1-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.40.1
Enable PCIe3 support, which is exposed via a PCIe3 connector.
Signed-off-by: Sebastian Reichel <[email protected]>
---
.../boot/dts/rockchip/rk3588-evb1-v10.dts | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
index 23bef9faa690..c3fe58e39e99 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -49,6 +49,26 @@ pcie20_avdd1v8: pcie20-avdd1v8-regulator {
vin-supply = <&avcc_1v8_s0>;
};
+ pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v75";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -58,6 +78,19 @@ vcc12v_dcin: vcc12v-dcin-regulator {
regulator-max-microvolt = <12000000>;
};
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_pcie30_en>;
+ };
+
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@@ -194,6 +227,18 @@ &pcie2x1l1 {
status = "okay";
};
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_reset>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
&pinctrl {
rtl8111 {
rtl8111_isolate: rtl8111-isolate {
@@ -220,6 +265,16 @@ pcie2_1_rst: pcie2-1-rst {
};
};
+ pcie3 {
+ pcie3_reset: pcie3-reset {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc3v3_pcie30_en: vcc3v3-pcie30-en {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.40.1
On Mon, 18 Sep 2023 16:13:25 +0200, Sebastian Reichel wrote:
> This enables PCIe network card and the PCIe slot for the RK3588 EVB1.
> There is one more PCIe lane being used for a WLAN card, but I did not
> yet get that working.
>
> -- Sebastian
>
> Sebastian Reichel (2):
> arm64: dts: rockchip: rk3588-evb1: add PCIe2 network controller
> arm64: dts: rockchip: rk3588-evb1: add PCIe3 bus
>
> [...]
Applied, thanks!
[1/2] arm64: dts: rockchip: rk3588-evb1: add PCIe2 network controller
commit: 86a2024d95e259c4309ced53242c0db6d993320b
[2/2] arm64: dts: rockchip: rk3588-evb1: add PCIe3 bus
commit: 46bb398ea1d81302e3735087ceb4b5763d5afc29
Best regards,
--
Heiko Stuebner <[email protected]>