Hi all,
This series fixes support for loading kernel to XKPHYS space.
It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
QEMU patch on the way.
Gregory and Vladimir, do let me know if I missed anything.
Thanks
- Jiaxun
[1]: https://lore.kernel.org/lkml/[email protected]/
Jiaxun Yang (5):
MIPS: Export higher/highest relocation functions in uasm
MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
MIPS: Fix set_uncached_handler for ebase in XKPHYS
MIPS: Handle mips_cps_core_entry within lower 4G
MIPS: Allow kernel base to be set from Kconfig for all platforms
arch/mips/Kconfig | 18 +++++++++++++----
arch/mips/include/asm/mips-cm.h | 1 +
arch/mips/include/asm/uasm.h | 2 ++
arch/mips/kernel/genex.S | 19 +++++++++++++----
arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++------
arch/mips/kernel/traps.c | 36 +++++++++++++++++++++++----------
arch/mips/mm/uasm.c | 6 ++++--
7 files changed, 82 insertions(+), 27 deletions(-)
--
2.34.1
ebase may be in XKPHYS if memblock unable to allocate memory
within KSEG0 physical range.
To map ebase into uncached space we just convert it back to
physical address and then use platform's TO_UNCAC helper
to create mapping.
Co-developed-by: Vladimir Kondratiev <[email protected]>
Signed-off-by: Vladimir Kondratiev <[email protected]>
Co-developed-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/traps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 60c513c51684..230728d76d11 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] =
void set_uncached_handler(unsigned long offset, void *addr,
unsigned long size)
{
- unsigned long uncached_ebase = CKSEG1ADDR(ebase);
+ unsigned long uncached_ebase = TO_UNCAC(__pa(ebase));
if (!addr)
panic(panic_null_cerr);
--
2.34.1
Export uasm_rel_{higher,highest} functions.
Those functions can be helpful in dealing with 64bit immediates.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/uasm.h | 2 ++
arch/mips/mm/uasm.c | 6 ++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 296bcf31abb5..12db6d2fca07 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr,
#ifdef CONFIG_64BIT
int uasm_in_compat_space_p(long addr);
#endif
+int uasm_rel_highest(long val);
+int uasm_rel_higher(long val);
int uasm_rel_hi(long val);
int uasm_rel_lo(long val);
void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 125140979d62..6846bf2084c5 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr)
}
UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
-static int uasm_rel_highest(long val)
+int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -433,8 +433,9 @@ static int uasm_rel_highest(long val)
return 0;
#endif
}
+UASM_EXPORT_SYMBOL(uasm_rel_highest);
-static int uasm_rel_higher(long val)
+int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -442,6 +443,7 @@ static int uasm_rel_higher(long val)
return 0;
#endif
}
+UASM_EXPORT_SYMBOL(uasm_rel_higher);
int uasm_rel_hi(long val)
{
--
2.34.1
There are some platforms in wild that generic loading address won't
work with them due to memory layout.
Allow PHYSICAL_START to be override from Kconfig, introduce
PHYSICAL_START_BOOL symbol as powerpc did.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bc8421859006..bfedc8b48a81 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2884,12 +2884,22 @@ config ARCH_SUPPORTS_KEXEC
config ARCH_SUPPORTS_CRASH_DUMP
def_bool y
+config PHYSICAL_START_BOOL
+ bool "Set physical address where the kernel is loaded"
+ default y if CRASH_DUMP
+ help
+ This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel
+ is loaded.
+
+ Say N here unless you know what you are doing.
+
config PHYSICAL_START
- hex "Physical address where the kernel is loaded"
- default "0xffffffff84000000"
- depends on CRASH_DUMP
+ hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
+ default "0xffffffff84000000" if CRASH_DUMP
+ default "0xffffffff80100000"
help
- This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
+ This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel
+ is loaded.
If you plan to use kernel for capturing the crash dump change
this value to start of the reserved region (the "X" value as
specified in the "crashkernel=YM@XM" command line boot parameter
--
2.34.1
Set CM_GCR_Cx_RESET_BASE_MODE and use XKPHYS base address for
core_entry for 64bit CM when mips_cps_core_entry is beyond
KSEG1.
Also disable SMP and warn user if mips_cps_core_entry is
unsuitable as reset vector.
Signed-off-by: Jiaxun Yang <[email protected]>
---
Note: IMO it does not solve the problem of MobileEye,
which have mips_cps_core_entry beyond lower 4G,
it just enables me to test kernel in XKPHYS on boston.
---
arch/mips/include/asm/mips-cm.h | 1 +
arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++++------
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 23c67c0871b1..15d8d69de455 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
+#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
/* GCR_Cx_ID - Identify the current core */
GCR_CX_ACCESSOR_RO(32, 0x028, id)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index dd55d59b88db..623dfd05585b 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -26,6 +26,7 @@
#include <asm/uasm.h>
static DECLARE_BITMAP(core_power, NR_CPUS);
+static uint32_t core_entry_reg;
struct core_boot_config *mips_cps_core_bootcfg;
@@ -37,7 +38,6 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
static void __init cps_smp_setup(void)
{
unsigned int nclusters, ncores, nvpes, core_vpes;
- unsigned long core_entry;
int cl, c, v;
/* Detect & record VPE topology */
@@ -94,10 +94,20 @@ static void __init cps_smp_setup(void)
/* Make core 0 coherent with everything */
write_gcr_cl_coherence(0xff);
- if (mips_cm_revision() >= CM_REV_CM3) {
- core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
- write_gcr_bev_base(core_entry);
- }
+ /*
+ * Set up the core entry address
+ * If accessible in KSEG1 just use KSEG1
+ */
+ if (__pa_symbol(mips_cps_core_entry) < SZ_512M)
+ core_entry_reg = CKSEG1ADDR(__pa_symbol(mips_cps_core_entry));
+
+ /* If CM is 64bit and with-in low 4G just use XKPHYS */
+ if (mips_cm_is64 && __pa_symbol(mips_cps_core_entry) < SZ_4G)
+ core_entry_reg = __pa_symbol(mips_cps_core_entry) |
+ CM_GCR_Cx_RESET_BASE_MODE;
+
+ if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
+ write_gcr_bev_base(core_entry_reg);
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
@@ -114,6 +124,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
mips_mt_set_cpuoptions();
+ if (!core_entry_reg) {
+ pr_err("core_entry address unsuitable, disabling smp-cps\n");
+ goto err_out;
+ }
+
/* Detect whether the CCA is unsuited to multi-core SMP */
cca = read_c0_config() & CONF_CM_CMASK;
switch (cca) {
@@ -213,7 +228,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
/* Set its reset vector */
- write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
+ write_gcr_co_reset_base(core_entry_reg);
/* Ensure its coherency is disabled */
write_gcr_co_coherence(0);
--
2.34.1
Hi Jiaxun,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.6-rc7 next-20231024]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jiaxun-Yang/MIPS-Export-higher-highest-relocation-functions-in-uasm/20231024-034657
base: linus/master
patch link: https://lore.kernel.org/r/20231023191400.170052-4-jiaxun.yang%40flygoat.com
patch subject: [PATCH 3/5] MIPS: Fix set_uncached_handler for ebase in XKPHYS
config: mips-loongson1c_defconfig (https://download.01.org/0day-ci/archive/20231025/[email protected]/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231025/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
1402 | asmlinkage void do_cpu(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1402:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1402 | asmlinkage void do_cpu(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1507:17: warning: no previous prototype for function 'do_msa_fpe' [-Wmissing-prototypes]
1507 | asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
| ^
arch/mips/kernel/traps.c:1507:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1507 | asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
| ^
| static
arch/mips/kernel/traps.c:1527:17: warning: no previous prototype for function 'do_msa' [-Wmissing-prototypes]
1527 | asmlinkage void do_msa(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1527:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1527 | asmlinkage void do_msa(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1548:17: warning: no previous prototype for function 'do_mdmx' [-Wmissing-prototypes]
1548 | asmlinkage void do_mdmx(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1548:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1548 | asmlinkage void do_mdmx(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1560:17: warning: no previous prototype for function 'do_watch' [-Wmissing-prototypes]
1560 | asmlinkage void do_watch(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1560:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1560 | asmlinkage void do_watch(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1590:17: warning: variable 'prev_state' set but not used [-Wunused-but-set-variable]
1590 | enum ctx_state prev_state;
| ^
arch/mips/kernel/traps.c:1587:17: warning: no previous prototype for function 'do_mcheck' [-Wmissing-prototypes]
1587 | asmlinkage void do_mcheck(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1587:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1587 | asmlinkage void do_mcheck(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1612:17: warning: no previous prototype for function 'do_mt' [-Wmissing-prototypes]
1612 | asmlinkage void do_mt(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1612:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1612 | asmlinkage void do_mt(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1648:17: warning: no previous prototype for function 'do_dsp' [-Wmissing-prototypes]
1648 | asmlinkage void do_dsp(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1648:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1648 | asmlinkage void do_dsp(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1656:17: warning: no previous prototype for function 'do_reserved' [-Wmissing-prototypes]
1656 | asmlinkage void do_reserved(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1656:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1656 | asmlinkage void do_reserved(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1832:17: warning: no previous prototype for function 'cache_parity_error' [-Wmissing-prototypes]
1832 | asmlinkage void cache_parity_error(void)
| ^
arch/mips/kernel/traps.c:1832:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1832 | asmlinkage void cache_parity_error(void)
| ^
| static
arch/mips/kernel/traps.c:1880:17: warning: no previous prototype for function 'do_ftlb' [-Wmissing-prototypes]
1880 | asmlinkage void do_ftlb(void)
| ^
arch/mips/kernel/traps.c:1880:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1880 | asmlinkage void do_ftlb(void)
| ^
| static
arch/mips/kernel/traps.c:1909:17: warning: no previous prototype for function 'do_gsexc' [-Wmissing-prototypes]
1909 | asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
| ^
arch/mips/kernel/traps.c:1909:12: note: declare 'static' if the function is not intended to be used outside of this translation unit
1909 | asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
| ^
| static
arch/mips/kernel/traps.c:1944:6: warning: no previous prototype for function 'ejtag_exception_handler' [-Wmissing-prototypes]
1944 | void ejtag_exception_handler(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1944:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
1944 | void ejtag_exception_handler(struct pt_regs *regs)
| ^
| static
arch/mips/kernel/traps.c:1989:17: warning: no previous prototype for function 'nmi_exception_handler' [-Wmissing-prototypes]
1989 | void __noreturn nmi_exception_handler(struct pt_regs *regs)
| ^
arch/mips/kernel/traps.c:1989:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
1989 | void __noreturn nmi_exception_handler(struct pt_regs *regs)
| ^
| static
>> arch/mips/kernel/traps.c:2349:33: error: call to undeclared function 'TO_UNCAC'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
2349 | unsigned long uncached_ebase = TO_UNCAC(__pa(ebase));
| ^
22 warnings and 1 error generated.
vim +/TO_UNCAC +2349 arch/mips/kernel/traps.c
2337
2338 static const char panic_null_cerr[] =
2339 "Trying to set NULL cache error exception handler\n";
2340
2341 /*
2342 * Install uncached CPU exception handler.
2343 * This is suitable only for the cache error exception which is the only
2344 * exception handler that is being run uncached.
2345 */
2346 void set_uncached_handler(unsigned long offset, void *addr,
2347 unsigned long size)
2348 {
> 2349 unsigned long uncached_ebase = TO_UNCAC(__pa(ebase));
2350
2351 if (!addr)
2352 panic(panic_null_cerr);
2353
2354 memcpy((void *)(uncached_ebase + offset), addr, size);
2355 }
2356
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On 10/23/23 12:13, Jiaxun Yang wrote:
> Hi all,
>
> This series fixes support for loading kernel to XKPHYS space.
> It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
>
> Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
> QEMU patch on the way.
>
> Gregory and Vladimir, do let me know if I missed anything.
>
> Thanks
> - Jiaxun
>
> [1]: https://lore.kernel.org/lkml/[email protected]/
FWIW, tested on a Cobalt Qube 2 (RM5231):
Tested-by: Florian Fainelli <[email protected]>
--
Florian
Hello Jiaxun,
> Hi all,
>
> This series fixes support for loading kernel to XKPHYS space.
> It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
>
> Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
> QEMU patch on the way.
>
> Gregory and Vladimir, do let me know if I missed anything.
Thanks for this series, I reviewed it and tested it on my platform, so
you can add for all the patches:
Reviewed-by: Gregory CLEMENT <[email protected]>
Tested-by: Gregory CLEMENT <[email protected]>
However I add to fix the patch " MIPS: Handle mips_cps_core_entry within
lower 4G", I think you missed a case. I will comment on it.
Gregory
>
> Thanks
> - Jiaxun
>
> [1]: https://lore.kernel.org/lkml/[email protected]/
>
> Jiaxun Yang (5):
> MIPS: Export higher/highest relocation functions in uasm
> MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
> MIPS: Fix set_uncached_handler for ebase in XKPHYS
> MIPS: Handle mips_cps_core_entry within lower 4G
> MIPS: Allow kernel base to be set from Kconfig for all platforms
>
> arch/mips/Kconfig | 18 +++++++++++++----
> arch/mips/include/asm/mips-cm.h | 1 +
> arch/mips/include/asm/uasm.h | 2 ++
> arch/mips/kernel/genex.S | 19 +++++++++++++----
> arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++------
> arch/mips/kernel/traps.c | 36 +++++++++++++++++++++++----------
> arch/mips/mm/uasm.c | 6 ++++--
> 7 files changed, 82 insertions(+), 27 deletions(-)
>
> --
> 2.34.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Jiaxun Yang <[email protected]> writes:
> Set CM_GCR_Cx_RESET_BASE_MODE and use XKPHYS base address for
> core_entry for 64bit CM when mips_cps_core_entry is beyond
> KSEG1.
>
> Also disable SMP and warn user if mips_cps_core_entry is
> unsuitable as reset vector.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> Note: IMO it does not solve the problem of MobileEye,
> which have mips_cps_core_entry beyond lower 4G,
> it just enables me to test kernel in XKPHYS on boston.
> ---
> arch/mips/include/asm/mips-cm.h | 1 +
> arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++++------
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
> index 23c67c0871b1..15d8d69de455 100644
> --- a/arch/mips/include/asm/mips-cm.h
> +++ b/arch/mips/include/asm/mips-cm.h
> @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other)
> /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
> GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
> #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
> +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
>
> /* GCR_Cx_ID - Identify the current core */
> GCR_CX_ACCESSOR_RO(32, 0x028, id)
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index dd55d59b88db..623dfd05585b 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -26,6 +26,7 @@
> #include <asm/uasm.h>
>
> static DECLARE_BITMAP(core_power, NR_CPUS);
> +static uint32_t core_entry_reg;
>
> struct core_boot_config *mips_cps_core_bootcfg;
>
> @@ -37,7 +38,6 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
> static void __init cps_smp_setup(void)
> {
> unsigned int nclusters, ncores, nvpes, core_vpes;
> - unsigned long core_entry;
> int cl, c, v;
>
> /* Detect & record VPE topology */
> @@ -94,10 +94,20 @@ static void __init cps_smp_setup(void)
> /* Make core 0 coherent with everything */
> write_gcr_cl_coherence(0xff);
>
> - if (mips_cm_revision() >= CM_REV_CM3) {
> - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
> - write_gcr_bev_base(core_entry);
> - }
> + /*
> + * Set up the core entry address
> + * If accessible in KSEG1 just use KSEG1
> + */
> + if (__pa_symbol(mips_cps_core_entry) < SZ_512M)
> + core_entry_reg = CKSEG1ADDR(__pa_symbol(mips_cps_core_entry));
> +
> + /* If CM is 64bit and with-in low 4G just use XKPHYS */
> + if (mips_cm_is64 && __pa_symbol(mips_cps_core_entry) < SZ_4G)
> + core_entry_reg = __pa_symbol(mips_cps_core_entry) |
> + CM_GCR_Cx_RESET_BASE_MODE;
> +
> + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
> + write_gcr_bev_base(core_entry_reg);
>
> #ifdef CONFIG_MIPS_MT_FPAFF
> /* If we have an FPU, enroll ourselves in the FPU-full mask */
> @@ -114,6 +124,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
>
> mips_mt_set_cpuoptions();
>
> + if (!core_entry_reg) {
> + pr_err("core_entry address unsuitable, disabling smp-cps\n");
> + goto err_out;
> + }
> +
> /* Detect whether the CCA is unsuited to multi-core SMP */
> cca = read_c0_config() & CONF_CM_CMASK;
> switch (cca) {
> @@ -213,7 +228,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
> mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
>
> /* Set its reset vector */
> - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
> + write_gcr_co_reset_base(core_entry_reg);
>
> /* Ensure its coherency is disabled */
> write_gcr_co_coherence(0);
For my point of view the following chunk is missing, and in my tests it
was needed to have this part to fully boot.
Maybe you don't have VP core in tour hardware.
@@ -349,8 +355,8 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
if (cpu_has_vp) {
mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
- core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
- write_gcr_co_reset_base(core_entry);
+ write_gcr_co_reset_base(core_entry_reg);
+
mips_cm_unlock_other();
}
> --
> 2.34.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Gregory CLEMENT <[email protected]> writes:
> Hello Jiaxun,
>
>
>> Hi all,
>>
>> This series fixes support for loading kernel to XKPHYS space.
>> It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
>>
>> Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
>> QEMU patch on the way.
>>
>> Gregory and Vladimir, do let me know if I missed anything.
>
> Thanks for this series, I reviewed it and tested it on my platform, so
> you can add for all the patches:
>
> Reviewed-by: Gregory CLEMENT <[email protected]>
> Tested-by: Gregory CLEMENT <[email protected]>
>
> However I add to fix the patch " MIPS: Handle mips_cps_core_entry within
> lower 4G", I think you missed a case. I will comment on it.
>
> Gregory
I forgot to say that if your series is not merged in 6.7, then I would
like to bring it in my series as I have to change some part of the code
to add support for the memory aliasing workaround.
Thanks,
Gregory
>
>
>>
>> Thanks
>> - Jiaxun
>>
>> [1]: https://lore.kernel.org/lkml/[email protected]/
>>
>> Jiaxun Yang (5):
>> MIPS: Export higher/highest relocation functions in uasm
>> MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
>> MIPS: Fix set_uncached_handler for ebase in XKPHYS
>> MIPS: Handle mips_cps_core_entry within lower 4G
>> MIPS: Allow kernel base to be set from Kconfig for all platforms
>>
>> arch/mips/Kconfig | 18 +++++++++++++----
>> arch/mips/include/asm/mips-cm.h | 1 +
>> arch/mips/include/asm/uasm.h | 2 ++
>> arch/mips/kernel/genex.S | 19 +++++++++++++----
>> arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++------
>> arch/mips/kernel/traps.c | 36 +++++++++++++++++++++++----------
>> arch/mips/mm/uasm.c | 6 ++++--
>> 7 files changed, 82 insertions(+), 27 deletions(-)
>>
>> --
>> 2.34.1
>>
>
> --
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> http://bootlin.com
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
在2023年10月27日十月 下午5:35，Gregory CLEMENT写道：
> Hello Jiaxun,
>
>
>> Hi all,
>>
>> This series fixes support for loading kernel to XKPHYS space.
>> It is derived from "MIPS: use virtual addresses from xkphys for MIPS64" [1].
>>
>> Boot tested on boston and QEMU with loading address set to 0xa800000090000000.
>> QEMU patch on the way.
>>
>> Gregory and Vladimir, do let me know if I missed anything.
>
> Thanks for this series, I reviewed it and tested it on my platform, so
> you can add for all the patches:
>
> Reviewed-by: Gregory CLEMENT <[email protected]>
> Tested-by: Gregory CLEMENT <[email protected]>
>
> However I add to fix the patch " MIPS: Handle mips_cps_core_entry within
> lower 4G", I think you missed a case. I will comment on it.
I found a better solution for CPS handling, will send v2 later together with
fixes to bring TO_CAC to 32bit.
Thanks.
- Jiaxun
>
> Gregory
>
>
>>
>> Thanks
>> - Jiaxun
>>
>> [1]: https://lore.kernel.org/lkml/[email protected]/
>>
>> Jiaxun Yang (5):
>> MIPS: Export higher/highest relocation functions in uasm
>> MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
>> MIPS: Fix set_uncached_handler for ebase in XKPHYS
>> MIPS: Handle mips_cps_core_entry within lower 4G
>> MIPS: Allow kernel base to be set from Kconfig for all platforms
>>
>> arch/mips/Kconfig | 18 +++++++++++++----
>> arch/mips/include/asm/mips-cm.h | 1 +
>> arch/mips/include/asm/uasm.h | 2 ++
>> arch/mips/kernel/genex.S | 19 +++++++++++++----
>> arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++------
>> arch/mips/kernel/traps.c | 36 +++++++++++++++++++++++----------
>> arch/mips/mm/uasm.c | 6 ++++--
>> 7 files changed, 82 insertions(+), 27 deletions(-)
>>
>> --
>> 2.34.1
>>
>
> --
> Gregory Clement, Bootlin
> Embedded Linux and Kernel engineering
> http://bootlin.com
--
- Jiaxun