Qualcomm targets define the following interrupts for usb wakeup:
{dp/dm}_hs_phy_irq, hs_phy_irq, pwr_event, ss_phy_irq.
But QUSB2 Phy based targets have another interrupt which gets triggered
in response to J/K states on dp/dm pads. Its functionality is replaced
by dp/dm interrupts on Femto/m31/eusb2 phy based targets for wakeup
purposes. Exceptions are some targets like SDM845/SDM670/SM6350 where
dp/dm irq's are used although they are qusb2 phy targets.
Currently in QUSB2 Phy based DT's, te qusb2_phy interrupt is named and
used as "hs_phy_irq" when in fact it is a different interrupt (used by
HW validation folks for debug purposes and not used on any downstream
target qusb/non-qusb).
On some non-QUSB2 targets (like sm8450/sm8550), the pwr_event IRQ was
named as hs_phy_irq and actual pwr_event_irq was skipped.
This series tries to address the discrepancies in the interrupt numbering
adding the missing interrupts and correcting the existing ones.
This series has been compared with downstream counter part and hw specifics
to ensure the numbering is right. Since there is not functionality change
the code has been only compile tested.
Changes in v2:
Removed additional compatibles added for different targets in v1.
Specified permuations of interrupts possible for QC targets and regrouped
interrupts for most of the DT's.
Rebased on top of wakeup interrupts fixes by Johan Hovold:
https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
Link to v1: (providing patchwork link since threading was broken in v1)
https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
Krishna Kurapati (6):
dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings
usb: dwc3: qcom: Rename hs_phy_irq to qusb2_phy_irq
arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets
arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350
arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332
.../devicetree/bindings/usb/qcom,dwc3.yaml | 122 +++++-------------
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 14 +-
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 14 +-
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 8 +-
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 ++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++
arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 ++-
arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +-
arch/arm64/boot/dts/qcom/qcs404.dtsi | 16 +++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 14 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 ++-
arch/arm64/boot/dts/qcom/sdm670.dtsi | 14 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 28 ++--
arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +-
arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 ++
arch/arm64/boot/dts/qcom/sm6350.dtsi | 13 +-
arch/arm64/boot/dts/qcom/sm6375.dtsi | 12 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +-
drivers/usb/dwc3/dwc3-qcom.c | 22 ++--
26 files changed, 293 insertions(+), 203 deletions(-)
--
2.42.0
The high speed related interrupts present on QC targets are as follows:
dp/dm irq's
These IRQ's directly reflect changes on the DP/DM pads of the SoC. These
are used as wakeup interrupts only on SoCs with non-QUSB2 targets with
exception of SDM670/SDM845/SM6350.
qusb2_phy irq
SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a
single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL
register. The required DPSE/DMSE configuration is done in
QUSB2PHY_INTR_CTRL register of phy address space.
hs_phy_irq
This is completely different from the above two and is present on all
targets with exception of a few IPQ ones. The interrupt is not enabled by
default and its functionality is mutually exclusive of qusb2_phy on QUSB
targets and DP/DM on femto phy targets.
The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq"
when they should have been "qusb2_phy_irq". On Femto phy targets, the
"hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event",
neither of which would never be triggered directly are non-functional
currently. The implementation tries to clean up this issue by addressing
the discrepencies involved and fixing the hs_phy_irq's in respective DT's.
Classify interrupts based on whether qusb2_phy interrupt is used or
{dp/dm}_hs_phy_irq is used and whether hs_phy_irq is present or not.
Signed-off-by: Krishna Kurapati <[email protected]>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 147 +++++++-----------
1 file changed, 58 insertions(+), 89 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 3ec62027f663..94deef765ec3 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -98,12 +98,30 @@ properties:
- const: apps-usb
interrupts:
- minItems: 1
- maxItems: 4
+ description: |
+ Different types of interrupts are used based on HS phy used on target::
+ - qusb2_phy:: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
+ expose only a single IRQ whose behavior can be modified
+ by the QUSB2PHY_INTR_CTRL register. The required DPSE/
+ DMSE configuration is done in QUSB2PHY_INTR_CTRL register
+ of phy address space.
+ - {dp/dm}_hs_phy_irq:: These IRQ's directly reflect changes on the DP/
+ DM pads of the SoC. These are used for wakeup
+ only on SoCs with non-QUSBb2 targets with
+ exception of SDM670/SDM845/SM6350.
+ - ss_phy_irq:: When in super speed mode of operation, interrupts are
+ received when a wakeup event is received on ss_phy_irq.
+ - hs_phY_irq:: Apart from DP/DM/QUSB2 Phy interrupts, there is
+ hs_phy_irq which is not triggered by default and its
+ functionality is mutually exclusive to that of
+ {dp/dm}_hs_phy_irq and qusb2_phy_irq.
+ - pwr_event:: Used for wakeup based on other power events.
+ minItems: 2
+ maxItems: 5
interrupt-names:
- minItems: 1
- maxItems: 4
+ minItems: 2
+ maxItems: 5
qcom,select-utmi-as-pipe-clk:
description:
@@ -359,116 +377,54 @@ allOf:
compatible:
contains:
enum:
- - qcom,ipq4019-dwc3
+ - qcom,ipq5018-dwc3
- qcom,ipq6018-dwc3
- - qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
- - qcom,msm8994-dwc3
- - qcom,qcs404-dwc3
- - qcom,sc7180-dwc3
- - qcom,sdm670-dwc3
- - qcom,sdm845-dwc3
- - qcom,sdx55-dwc3
- - qcom,sdx65-dwc3
- - qcom,sdx75-dwc3
- - qcom,sm4250-dwc3
- - qcom,sm6350-dwc3
- - qcom,sm8150-dwc3
- - qcom,sm8250-dwc3
- - qcom,sm8350-dwc3
- - qcom,sm8450-dwc3
- - qcom,sm8550-dwc3
- - qcom,sm8650-dwc3
+ - qcom,msm8953-dwc3
+ - qcom,msm8998-dwc3
+ - qcom,qcm2290-dwc3
then:
properties:
- interrupts:
- items:
- - description: The interrupt that is asserted
- when a wakeup event is received on USB2 bus.
- - description: The interrupt that is asserted
- when a wakeup event is received on USB3 bus.
- - description: Wakeup event on DM line.
- - description: Wakeup event on DP line.
interrupt-names:
items:
- - const: hs_phy_irq
- - const: ss_phy_irq
- - const: dm_hs_phy_irq
- - const: dp_hs_phy_irq
+ - const: pwr_event
+ - const: qusb2_phy
+ - const: ss_phy_irq (optional)
- if:
properties:
compatible:
contains:
enum:
- - qcom,msm8953-dwc3
- qcom,msm8996-dwc3
- - qcom,msm8998-dwc3
+ - qcom,qcs404-dwc3
+ - qcom,sdm660-dwc3
- qcom,sm6115-dwc3
- qcom,sm6125-dwc3
then:
properties:
- interrupts:
- maxItems: 2
interrupt-names:
items:
+ - const: pwr_event
- const: hs_phy_irq
- - const: ss_phy_irq
+ - const: qusb2_phy
+ - const: ss_phy_irq (optional)
- if:
properties:
compatible:
contains:
enum:
- - qcom,ipq5018-dwc3
- qcom,ipq5332-dwc3
- - qcom,sdm660-dwc3
- then:
- properties:
- interrupts:
- minItems: 1
- maxItems: 2
- interrupt-names:
- minItems: 1
- items:
- - const: hs_phy_irq
- - const: ss_phy_irq
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc7280-dwc3
- then:
- properties:
- interrupts:
- minItems: 3
- maxItems: 4
- interrupt-names:
- minItems: 3
- items:
- - const: hs_phy_irq
- - const: dp_hs_phy_irq
- - const: dm_hs_phy_irq
- - const: ss_phy_irq
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- qcom,sc8280xp-dwc3
then:
properties:
- interrupts:
- maxItems: 4
interrupt-names:
items:
- const: pwr_event
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- - const: ss_phy_irq
+ - const: ss_phy_irq (optional)
- if:
properties:
@@ -476,18 +432,30 @@ allOf:
contains:
enum:
- qcom,sa8775p-dwc3
+ - qcom,sc7180-dwc3
+ - qcom,sc7280-dwc3
+ - qcom,sdm670-dwc3
+ - qcom,sdm845-dwc3
+ - qcom,sdx55-dwc3
+ - qcom,sdx65-dwc3
+ - qcom,sdx75-dwc3
+ - qcom,sm6350-dwc3
+ - qcom,sm6375-dwc3
+ - qcom,sm8150-dwc3
+ - qcom,sm8250-dwc3
+ - qcom,sm8350-dwc3
+ - qcom,sm8450-dwc3
+ - qcom,sm8550-dwc3
+ - qcom,sm8650-dwc3
then:
properties:
- interrupts:
- minItems: 3
- maxItems: 4
interrupt-names:
- minItems: 3
items:
- const: pwr_event
+ - const: hs_phy_irq
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- - const: ss_phy_irq
+ - const: ss_phy_irq (optional)
additionalProperties: false
@@ -522,12 +490,13 @@ examples:
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event", "hs_phy_irq",
+ "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
--
2.42.0
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2
phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or
pwr_event. In one case, the hs_phy_irq was incorrectly defined with the
latter's IRQ number. Since the DT must describe the hw whether or not
the driver uses these interrupts, fix and add the missing entries in order
to describe the HW completely and accurately.
Also modify order of interrupts in accordance to bindings update.
Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 14 ++++++++-----
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 14 +++++++------
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 14 ++++++++-----
arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 +++++++----
arch/arm64/boot/dts/qcom/sm6375.dtsi | 12 ++++++-----
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 +++++++++++++++++---------
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 +++++++++++++++-----------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 +++++++++++++++-----------
arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++-----
arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++-----
11 files changed, 111 insertions(+), 69 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
index e30dbf12990a..3c85f7d0f163 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
@@ -585,12 +585,16 @@ usb: usb@a6f8800 {
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 158 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 157 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_GDSC>;
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index e559adaaeee7..1014853007cf 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -498,14 +498,16 @@ usb: usb@a6f8800 {
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 19 IRQ_TYPE_EDGE_BOTH>,
<&pdc 18 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 4b42a329460c..a75613d26c06 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1610,10 +1610,12 @@ usb_0: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@@ -1697,10 +1699,12 @@ usb_1: usb@a8f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 7 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@@ -1760,9 +1764,11 @@ usb_2: usb@a4f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 8dc50d4afe29..9ae62df49274 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2964,12 +2964,16 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5ca77acd2a46..c8847220aac0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3425,10 +3425,12 @@ usb_2: usb@8cf8800 {
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@@ -3680,11 +3682,13 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq",
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index b479f3d9a3a8..27ea0668a681 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -1361,13 +1361,15 @@ usb_1: usb@4ef8800 {
assigned-clock-rates = <19200000>, <133333333>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 93 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 94 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 3e7048d8ac55..f05397443111 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3565,12 +3565,16 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -3618,12 +3622,16 @@ usb_2: usb@a8f8800 {
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 490 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index be970472f6c4..3cd07813d402 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4131,14 +4131,16 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -4199,14 +4201,16 @@ usb_2: usb@a8f8800 {
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index b46236235b7f..7fc2997456a5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2321,14 +2321,16 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -2394,14 +2396,16 @@ usb_2: usb@a8f8800 {
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 1783fa78bdbc..163186f009c4 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4298,13 +4298,15 @@ usb_1: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 9b5b098bb7e8..0c55c46dd2bb 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2922,13 +2922,15 @@ usb_1: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
--
2.42.0
For qcs404 and ipq5332, certain interrupts are missing in DT.
Add them to ensure they are in accordance to bindings.
Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 8 ++++++--
arch/arm64/boot/dts/qcom/qcs404.dtsi | 16 ++++++++++++++++
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index d3fef2f80a81..82cd807af475 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -307,8 +307,12 @@ usb: usb@8af8800 {
compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SNOC_USB_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 2721f32dfb71..469ea4d8cd3b 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -684,6 +684,14 @@ usb3: usb@7678800 {
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "qusb2_phy";
+
status = "disabled";
usb3_dwc3: usb@7580000 {
@@ -713,6 +721,14 @@ usb2: usb@79b8800 {
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB_HS_SYSTEM_CLK>;
assigned-clock-rates = <19200000>, <133333333>;
+
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "qusb2_phy";
+
status = "disabled";
usb@78c0000 {
--
2.42.0
For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm
interrupts are used for wakeup instead of qusb2_phy irq. These targets
were part of a generation that were the last ones to implement QUSB2 PHY
and the design incorporated dedicated DP/DM interrupts which eventually
carried forward to the newer femto based targets.
Add the missing pwr_event irq for these targets. Also modify order of
interrupts in accordance to bindings update.
Signed-off-by: Krishna Kurapati <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 14 +++++++++-----
arch/arm64/boot/dts/qcom/sdm845.dtsi | 28 ++++++++++++++++++----------
arch/arm64/boot/dts/qcom/sm6350.dtsi | 13 ++++++++-----
3 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index c873560ae9d5..d189bcfeeb05 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1295,12 +1295,16 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0d2be706505a..e672707ee4de 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4053,12 +4053,16 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -4104,12 +4108,16 @@ usb_2: usb@a8f8800 {
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 490 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 8fd6f4d03490..be1ee176b520 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1840,12 +1840,15 @@ usb_1: usb@a6f8800 {
"mock_utmi";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
-
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
--
2.42.0
On Mon, Dec 04, 2023 at 03:39:44PM +0530, Krishna Kurapati wrote:
> Qualcomm targets define the following interrupts for usb wakeup:
> {dp/dm}_hs_phy_irq, hs_phy_irq, pwr_event, ss_phy_irq.
>
> But QUSB2 Phy based targets have another interrupt which gets triggered
> in response to J/K states on dp/dm pads. Its functionality is replaced
> by dp/dm interrupts on Femto/m31/eusb2 phy based targets for wakeup
> purposes. Exceptions are some targets like SDM845/SDM670/SM6350 where
> dp/dm irq's are used although they are qusb2 phy targets.
>
> Currently in QUSB2 Phy based DT's, te qusb2_phy interrupt is named and
> used as "hs_phy_irq" when in fact it is a different interrupt (used by
> HW validation folks for debug purposes and not used on any downstream
> target qusb/non-qusb).
>
> On some non-QUSB2 targets (like sm8450/sm8550), the pwr_event IRQ was
> named as hs_phy_irq and actual pwr_event_irq was skipped.
>
> This series tries to address the discrepancies in the interrupt numbering
> adding the missing interrupts and correcting the existing ones.
>
> This series has been compared with downstream counter part and hw specifics
> to ensure the numbering is right. Since there is not functionality change
> the code has been only compile tested.
This is a good summary.
> Changes in v2:
> Removed additional compatibles added for different targets in v1.
> Specified permuations of interrupts possible for QC targets and regrouped
> interrupts for most of the DT's.
>
> Rebased on top of wakeup interrupts fixes by Johan Hovold:
> https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
>
> Link to v1: (providing patchwork link since threading was broken in v1)
> https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
>
> Krishna Kurapati (6):
> dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings
> usb: dwc3: qcom: Rename hs_phy_irq to qusb2_phy_irq
> arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
> arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets
> arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350
> arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332
You're still mixing USB binding/driver and DT updates, which is what we
want for most subsystems, but not for USB.
For the next version, please split it in two series as these will go in
through two different maintainer trees.
You can link to the driver/binding series from the devicetree series and
mention to Bjorn that it should not be merged before the bindings are
in.
And please use lore for any links instead of patchwork.
Johan
On Mon, Dec 04, 2023 at 03:39:45PM +0530, Krishna Kurapati wrote:
> The high speed related interrupts present on QC targets are as follows:
>
> dp/dm irq's
> These IRQ's directly reflect changes on the DP/DM pads of the SoC. These
> are used as wakeup interrupts only on SoCs with non-QUSB2 targets with
> exception of SDM670/SDM845/SM6350.
>
> qusb2_phy irq
> SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a
> single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL
> register. The required DPSE/DMSE configuration is done in
> QUSB2PHY_INTR_CTRL register of phy address space.
>
> hs_phy_irq
> This is completely different from the above two and is present on all
> targets with exception of a few IPQ ones. The interrupt is not enabled by
> default and its functionality is mutually exclusive of qusb2_phy on QUSB
> targets and DP/DM on femto phy targets.
>
> The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq"
> when they should have been "qusb2_phy_irq". On Femto phy targets, the
> "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event",
> neither of which would never be triggered directly are non-functional
> currently. The implementation tries to clean up this issue by addressing
> the discrepencies involved and fixing the hs_phy_irq's in respective DT's.
>
> Classify interrupts based on whether qusb2_phy interrupt is used or
> {dp/dm}_hs_phy_irq is used and whether hs_phy_irq is present or not.
s/interrupts/SoCs in four groups/
And say something about the SS PHY interrupt being treated as optional
as there are SoCs with multiple controllers where only some supports SS.
As Krzysztof mentioned you should also add something to motivate why
this de-facto ABI breakage by reordering interrupts is justified and
safe in this case.
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 147 +++++++-----------
> 1 file changed, 58 insertions(+), 89 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index 3ec62027f663..94deef765ec3 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -98,12 +98,30 @@ properties:
> - const: apps-usb
>
> interrupts:
> - minItems: 1
> - maxItems: 4
> + description: |
> + Different types of interrupts are used based on HS phy used on target::
Try to use uppercase 'PHY' consistently in text throughout the series.
> + - qusb2_phy:: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
> + expose only a single IRQ whose behavior can be modified
> + by the QUSB2PHY_INTR_CTRL register. The required DPSE/
> + DMSE configuration is done in QUSB2PHY_INTR_CTRL register
> + of phy address space.
> + - {dp/dm}_hs_phy_irq:: These IRQ's directly reflect changes on the DP/
> + DM pads of the SoC. These are used for wakeup
> + only on SoCs with non-QUSBb2 targets with
QUSB2 typo
> + exception of SDM670/SDM845/SM6350.
> + - ss_phy_irq:: When in super speed mode of operation, interrupts are
Capitalise 'Super Speed'
> + received when a wakeup event is received on ss_phy_irq.
The description as it stands sounds circular. And this one is only used
for remote wakeup right?
> + - hs_phY_irq:: Apart from DP/DM/QUSB2 Phy interrupts, there is
s/phY/phy/
Perhaps rephrase to sound less like a commit message and to make it a
bit more concise.
But this is already an improvement over the current descriptions which
are too terse and not even correct.
> + hs_phy_irq which is not triggered by default and its
> + functionality is mutually exclusive to that of
> + {dp/dm}_hs_phy_irq and qusb2_phy_irq.
> + - pwr_event:: Used for wakeup based on other power events.
I'm not sure about the free text description of these (format etc), but
at least this avoid repeating the descriptions for each permutation.
Perhaps the DT maintainers can chime in here.
I think you should reorder them to match the permutations below though.
> + minItems: 2
> + maxItems: 5
>
> interrupt-names:
> - minItems: 1
> - maxItems: 4
> + minItems: 2
> + maxItems: 5
>
> qcom,select-utmi-as-pipe-clk:
> description:
> @@ -359,116 +377,54 @@ allOf:
> compatible:
> contains:
> enum:
> - - qcom,ipq4019-dwc3
> + - qcom,ipq5018-dwc3
> - qcom,ipq6018-dwc3
> - - qcom,ipq8064-dwc3
> - qcom,ipq8074-dwc3
> - - qcom,msm8994-dwc3
> - - qcom,qcs404-dwc3
> - - qcom,sc7180-dwc3
> - - qcom,sdm670-dwc3
> - - qcom,sdm845-dwc3
> - - qcom,sdx55-dwc3
> - - qcom,sdx65-dwc3
> - - qcom,sdx75-dwc3
> - - qcom,sm4250-dwc3
> - - qcom,sm6350-dwc3
> - - qcom,sm8150-dwc3
> - - qcom,sm8250-dwc3
> - - qcom,sm8350-dwc3
> - - qcom,sm8450-dwc3
> - - qcom,sm8550-dwc3
> - - qcom,sm8650-dwc3
> + - qcom,msm8953-dwc3
> + - qcom,msm8998-dwc3
> + - qcom,qcm2290-dwc3
> then:
> properties:
> - interrupts:
> - items:
> - - description: The interrupt that is asserted
> - when a wakeup event is received on USB2 bus.
> - - description: The interrupt that is asserted
> - when a wakeup event is received on USB3 bus.
> - - description: Wakeup event on DM line.
> - - description: Wakeup event on DP line.
> interrupt-names:
> items:
> - - const: hs_phy_irq
> - - const: ss_phy_irq
> - - const: dm_hs_phy_irq
> - - const: dp_hs_phy_irq
> + - const: pwr_event
> + - const: qusb2_phy
> + - const: ss_phy_irq (optional)
You should not include the string "(optional)" here. It was only a
notation I used when we discussed this earlier.
The fact that these are optional should be expressed using min/maxItems
as I mentioned earlier. For the above SoCs that would be
minItems: 2
maxItems: 3
> @@ -522,12 +490,13 @@ examples:
> <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> assigned-clock-rates = <19200000>, <150000000>;
>
> - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
> <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
> - <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
> - interrupt-names = "hs_phy_irq", "ss_phy_irq",
> - "dm_hs_phy_irq", "dp_hs_phy_irq";
> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event", "hs_phy_irq",
> + "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
Perhaps you should align the continuation line here too.
>
> power-domains = <&gcc USB30_PRIM_GDSC>;
Also have you set up the tools so that you can verify your bindings
before posing them? I assume the above wouldn't pass (e.g. due to the
"(optional)" strings).
There's some more details here:
https://docs.kernel.org/devicetree/bindings/writing-schema.html
under "Running checks".
Johan
On Mon, Dec 04, 2023 at 03:39:50PM +0530, Krishna Kurapati wrote:
> For qcs404 and ipq5332, certain interrupts are missing in DT.
> Add them to ensure they are in accordance to bindings.
Here too you can say something about the remote wakeup functionality
that this potentially enables (at least on ipq5332 with the current
Linux implementation).
Johan
Hi Johan. Thanks for the review.
>
> And say something about the SS PHY interrupt being treated as optional
> as there are SoCs with multiple controllers where only some supports SS.
>
> As Krzysztof mentioned you should also add something to motivate why
> this de-facto ABI breakage by reordering interrupts is justified and
> safe in this case.
>
Sure. Let me come up with a good reason why this breakage is needed.
>
> Try to use uppercase 'PHY' consistently in text throughout the series.
>
ACK.
>> + - qusb2_phy:: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
>> + expose only a single IRQ whose behavior can be modified
>> + by the QUSB2PHY_INTR_CTRL register. The required DPSE/
>> + DMSE configuration is done in QUSB2PHY_INTR_CTRL register
>> + of phy address space.
>> + - {dp/dm}_hs_phy_irq:: These IRQ's directly reflect changes on the DP/
>> + DM pads of the SoC. These are used for wakeup
>> + only on SoCs with non-QUSBb2 targets with
>
> QUSB2 typo
>
>> + exception of SDM670/SDM845/SM6350.
>> + - ss_phy_irq:: When in super speed mode of operation, interrupts are
>
> Capitalise 'Super Speed'
>
>> + received when a wakeup event is received on ss_phy_irq.
>
> The description as it stands sounds circular. And this one is only used
> for remote wakeup right?
>
Yes. It is used for remote wakeup. Mentioning it as wakeup event should
be changed ?
>> + - hs_phY_irq:: Apart from DP/DM/QUSB2 Phy interrupts, there is
>
> s/phY/phy/
>
> Perhaps rephrase to sound less like a commit message and to make it a
> bit more concise.
>
> But this is already an improvement over the current descriptions which
> are too terse and not even correct.
>
>> + hs_phy_irq which is not triggered by default and its
>> + functionality is mutually exclusive to that of
>> + {dp/dm}_hs_phy_irq and qusb2_phy_irq.
>> + - pwr_event:: Used for wakeup based on other power events.
>
> I'm not sure about the free text description of these (format etc), but
> at least this avoid repeating the descriptions for each permutation.
>
> Perhaps the DT maintainers can chime in here.
>
> I think you should reorder them to match the permutations below though.
>
Sure. Will reorder them as per permutations.
>> + minItems: 2
>> + maxItems: 5
>>
>> interrupt-names:
>> - minItems: 1
>> - maxItems: 4
>> + minItems: 2
>> + maxItems: 5
>>
>> qcom,select-utmi-as-pipe-clk:
>> description:
>> @@ -359,116 +377,54 @@ allOf:
>> compatible:
>> contains:
>> enum:
>> - - qcom,ipq4019-dwc3
>> + - qcom,ipq5018-dwc3
>> - qcom,ipq6018-dwc3
>> - - qcom,ipq8064-dwc3
>> - qcom,ipq8074-dwc3
>> - - qcom,msm8994-dwc3
>> - - qcom,qcs404-dwc3
>> - - qcom,sc7180-dwc3
>> - - qcom,sdm670-dwc3
>> - - qcom,sdm845-dwc3
>> - - qcom,sdx55-dwc3
>> - - qcom,sdx65-dwc3
>> - - qcom,sdx75-dwc3
>> - - qcom,sm4250-dwc3
>> - - qcom,sm6350-dwc3
>> - - qcom,sm8150-dwc3
>> - - qcom,sm8250-dwc3
>> - - qcom,sm8350-dwc3
>> - - qcom,sm8450-dwc3
>> - - qcom,sm8550-dwc3
>> - - qcom,sm8650-dwc3
>> + - qcom,msm8953-dwc3
>> + - qcom,msm8998-dwc3
>> + - qcom,qcm2290-dwc3
>> then:
>> properties:
>> - interrupts:
>> - items:
>> - - description: The interrupt that is asserted
>> - when a wakeup event is received on USB2 bus.
>> - - description: The interrupt that is asserted
>> - when a wakeup event is received on USB3 bus.
>> - - description: Wakeup event on DM line.
>> - - description: Wakeup event on DP line.
>> interrupt-names:
>> items:
>> - - const: hs_phy_irq
>> - - const: ss_phy_irq
>> - - const: dm_hs_phy_irq
>> - - const: dp_hs_phy_irq
>> + - const: pwr_event
>> + - const: qusb2_phy
>> + - const: ss_phy_irq (optional)
>
> You should not include the string "(optional)" here. It was only a
> notation I used when we discussed this earlier.
>
> The fact that these are optional should be expressed using min/maxItems
> as I mentioned earlier. For the above SoCs that would be
>
> minItems: 2
> maxItems: 3
> >> @@ -522,12 +490,13 @@ examples:
>> <&gcc GCC_USB30_PRIM_MASTER_CLK>;
>> assigned-clock-rates = <19200000>, <150000000>;
>>
>> - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> - <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
>> <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
>> - <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
>> - interrupt-names = "hs_phy_irq", "ss_phy_irq",
>> - "dm_hs_phy_irq", "dp_hs_phy_irq";
>> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "pwr_event", "hs_phy_irq",
>> + "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
>
> Perhaps you should align the continuation line here too.
>
>>
>> power-domains = <&gcc USB30_PRIM_GDSC>;
>
> Also have you set up the tools so that you can verify your bindings
> before posing them? I assume the above wouldn't pass (e.g. due to the
> "(optional)" strings).
>
> There's some more details here:
>
> https://docs.kernel.org/devicetree/bindings/writing-schema.html
>
> under "Running checks".
I did do a dt-binding check and got the following line as well:
DTC_CHK Documentation/devicetree/bindings/usb/qcom,dwc3.example.dtb
/local/mnt/workspace/sriramd/upstream/torvalds/linux/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dtb:
usb@a6f8800: interrupt-names:4: 'ss_phy_irq (optional)' was expected
From schema:
I ignored this because it isn't a warning and the example dtb too was
generated. Will remove the optional thing in v3.
Regards,
Krishna,
On Thu, Dec 07, 2023 at 09:14:55PM +0530, Krishna Kurapati PSSNV wrote:
> >> + - qusb2_phy:: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
> >> + expose only a single IRQ whose behavior can be modified
> >> + by the QUSB2PHY_INTR_CTRL register. The required DPSE/
> >> + DMSE configuration is done in QUSB2PHY_INTR_CTRL register
> >> + of phy address space.
> >> + - {dp/dm}_hs_phy_irq:: These IRQ's directly reflect changes on the DP/
> >> + DM pads of the SoC. These are used for wakeup
> >> + only on SoCs with non-QUSBb2 targets with
> >
> > QUSB2 typo
> >
> >> + exception of SDM670/SDM845/SM6350.
> >> + - ss_phy_irq:: When in super speed mode of operation, interrupts are
> >
> > Capitalise 'Super Speed'
> >
> >> + received when a wakeup event is received on ss_phy_irq.
> >
> > The description as it stands sounds circular. And this one is only used
> > for remote wakeup right?
> >
> Yes. It is used for remote wakeup. Mentioning it as wakeup event should
> be changed ?
It would be good to clarify that this one is the IIUC not used for
connect/disconnect events but just for remote wakeup, that is, unlike
the qusb2_phy and dp/dm_hs_phy interrupts.
The old descriptions just vaguely said "wakeup event" and
connect/disconnect events aren't necessarily wakeup events.
> > Also have you set up the tools so that you can verify your bindings
> > before posing them? I assume the above wouldn't pass (e.g. due to the
> > "(optional)" strings).
> >
> > There's some more details here:
> >
> > https://docs.kernel.org/devicetree/bindings/writing-schema.html
> >
> > under "Running checks".
>
> I did do a dt-binding check and got the following line as well:
>
> DTC_CHK Documentation/devicetree/bindings/usb/qcom,dwc3.example.dtb
> /local/mnt/workspace/sriramd/upstream/torvalds/linux/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dtb:
> usb@a6f8800: interrupt-names:4: 'ss_phy_irq (optional)' was expected
> From schema:
Good that you got that set up.
Johan
On Mon, Dec 04, 2023 at 03:39:45PM +0530, Krishna Kurapati wrote:
> The high speed related interrupts present on QC targets are as follows:
>
> dp/dm irq's
> These IRQ's directly reflect changes on the DP/DM pads of the SoC. These
> are used as wakeup interrupts only on SoCs with non-QUSB2 targets with
> exception of SDM670/SDM845/SM6350.
>
> qusb2_phy irq
> SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a
> single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL
> register. The required DPSE/DMSE configuration is done in
> QUSB2PHY_INTR_CTRL register of phy address space.
>
> hs_phy_irq
> This is completely different from the above two and is present on all
> targets with exception of a few IPQ ones. The interrupt is not enabled by
> default and its functionality is mutually exclusive of qusb2_phy on QUSB
> targets and DP/DM on femto phy targets.
>
> The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq"
> when they should have been "qusb2_phy_irq". On Femto phy targets, the
> "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event",
> neither of which would never be triggered directly are non-functional
> currently. The implementation tries to clean up this issue by addressing
> the discrepencies involved and fixing the hs_phy_irq's in respective DT's.
>
> Classify interrupts based on whether qusb2_phy interrupt is used or
> {dp/dm}_hs_phy_irq is used and whether hs_phy_irq is present or not.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 147 +++++++-----------
> 1 file changed, 58 insertions(+), 89 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index 3ec62027f663..94deef765ec3 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -98,12 +98,30 @@ properties:
> - const: apps-usb
>
> interrupts:
> - minItems: 1
> - maxItems: 4
> + description: |
> + Different types of interrupts are used based on HS phy used on target::
Why the double colon? This isn't rSt.
Rob
On 04/12/2023 11:09, Krishna Kurapati wrote:
> then:
> properties:
> - interrupts:
> - items:
> - - description: The interrupt that is asserted
> - when a wakeup event is received on USB2 bus.
> - - description: The interrupt that is asserted
> - when a wakeup event is received on USB3 bus.
> - - description: Wakeup event on DM line.
> - - description: Wakeup event on DP line.
> interrupt-names:
> items:
> - - const: hs_phy_irq
> - - const: ss_phy_irq
> - - const: dm_hs_phy_irq
> - - const: dp_hs_phy_irq
> + - const: pwr_event
> + - const: qusb2_phy
> + - const: ss_phy_irq (optional)
You did not test your bindings.
Best regards,
Krzysztof