From: Conor Dooley <[email protected]>
While reviewing a CAN clock driver internally for MPFS [1], I realised
that the modeling of the MSSPLL such that one one of its outputs could
be used was not correct. The CAN controllers on MPFS take 2 input
clocks - one that is the bus clock, acquired from the main MSSPLL and
a second clock for the AHB interface to the result of the SoC.
Currently the binding for the CAN controllers and the represetnation
of the MSSPLL only allows for one of these clocks.
Modify the binding and devicetree to expect two clocks and rework the
main clock controller driver for MPFS such that it is capable of
providing multiple outputs from the MSSPLL.
Cheers,
Conor.
1 - Hopefully that'll show up on the lists soon, once we are happy with
it ourselves.
CC: Conor Dooley <[email protected]>
CC: Daire McNamara <[email protected]>
CC: Wolfgang Grandegger <[email protected]>
CC: Marc Kleine-Budde <[email protected]>
CC: "David S. Miller" <[email protected]>
CC: Eric Dumazet <[email protected]>
CC: Jakub Kicinski <[email protected]>
CC: Paolo Abeni <[email protected]>
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: Paul Walmsley <[email protected]>
CC: Palmer Dabbelt <[email protected]>
CC: Albert Ou <[email protected]>
CC: Michael Turquette <[email protected]>
CC: Stephen Boyd <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
Conor Dooley (7):
dt-bindings: clock: mpfs: add more MSSPLL output definitions
dt-bindings: can: mpfs: add missing required clock
clk: microchip: mpfs: split MSSPLL in two
clk: microchip: mpfs: setup for using other mss pll outputs
clk: microchip: mpfs: add missing MSSPLL outputs
clk: microchip: mpfs: convert MSSPLL outputs to clk_divider
riscv: dts: microchip: add missing CAN bus clocks
.../bindings/net/can/microchip,mpfs-can.yaml | 7 +-
arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 +-
drivers/clk/microchip/clk-mpfs.c | 154 ++++++++++--------
.../dt-bindings/clock/microchip,mpfs-clock.h | 5 +
4 files changed, 99 insertions(+), 71 deletions(-)
--
2.39.2
On Fri, Dec 08, 2023 at 05:07:39PM +0000, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> While reviewing a CAN clock driver internally for MPFS [1], I realised
> that the modeling of the MSSPLL such that one one of its outputs could
> be used was not correct. The CAN controllers on MPFS take 2 input
> clocks - one that is the bus clock, acquired from the main MSSPLL and
> a second clock for the AHB interface to the result of the SoC.
> Currently the binding for the CAN controllers and the represetnation
> of the MSSPLL only allows for one of these clocks.
> Modify the binding and devicetree to expect two clocks and rework the
> main clock controller driver for MPFS such that it is capable of
> providing multiple outputs from the MSSPLL.
>
> Cheers,
> Conor.
Whoops, that was meant to get a dry run arg... Please ignore!