Changes in v2:
1. Previous submission included stale patch. Resend without it. No
actual changes, but marking it v2 for convenience.
Best regards,
Krzysztof
Krzysztof Kozlowski (4):
arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes
arm64: dts: qcom: sm8450: drop unneeded assigned-clocks from codec
macros
arm64: dts: qcom: sm8550: move Soundwire pinctrl to its nodes
arm64: dts: qcom: sm8550: drop unneeded assigned-clocks from codec
macros
arch/arm64/boot/dts/qcom/sm8450.dtsi | 36 ++++++++++------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 34 ++++++++++----------------
2 files changed, 24 insertions(+), 46 deletions(-)
--
2.34.1
Pin configuration for Soundwire bus should be set in Soundwire
controller nodes, not in the associated macro codec node. This
placement change should not have big impact in general, because macro
codec is a clock provider for Soundwire controller, thus its devices is
probed first. However it will have impact for disabled Soundwire buses,
e.g. WSA2, because after this change the pins will be left in default
state.
We also follow similar approach in newer SoCs, like Qualcomm SM8650.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Not tested on HW.
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 12e55a0c7417..3b6ea9653d2a 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2160,8 +2160,6 @@ wsa2macro: codec@31e0000 {
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa2_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2173,6 +2171,9 @@ swr4: soundwire-controller@31f0000 {
clock-names = "iface";
label = "WSA2";
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@@ -2208,8 +2209,6 @@ rxmacro: codec@3200000 {
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&rx_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2223,6 +2222,9 @@ swr1: soundwire-controller@3210000 {
qcom,din-ports = <0>;
qcom,dout-ports = <5>;
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
@@ -2254,8 +2256,6 @@ txmacro: codec@3220000 {
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&tx_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2275,8 +2275,6 @@ wsamacro: codec@3240000 {
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2288,6 +2286,9 @@ swr0: soundwire-controller@3250000 {
clock-names = "iface";
label = "WSA";
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@@ -2318,6 +2319,9 @@ swr2: soundwire-controller@33b0000 {
clock-names = "iface";
label = "TX";
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
--
2.34.1
The MCLK clocks of codec macros have fixed 19.2 MHz frequency and
assigning clock rates is redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Not tested on HW.
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 3b6ea9653d2a..52390220d909 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2154,9 +2154,6 @@ wsa2macro: codec@31e0000 {
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
@@ -2203,10 +2200,6 @@ rxmacro: codec@3200000 {
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
@@ -2250,9 +2243,6 @@ txmacro: codec@3220000 {
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
@@ -2269,10 +2259,6 @@ wsamacro: codec@3240000 {
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
@@ -2348,8 +2334,6 @@ vamacro: codec@33f0000 {
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec", "npl";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "fsgen";
--
2.34.1
Pin configuration for Soundwire bus should be set in Soundwire
controller nodes, not in the associated macro codec node. This
placement change should not have big impact in general, because macro
codec is a clock provider for Soundwire controller, thus its devices is
probed first. However it will have impact for disabled Soundwire buses,
e.g. WSA2, because after this change the pins will be left in default
state.
We also follow similar approach in newer SoCs, like Qualcomm SM8650.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 1f06fd33d1ce..d8f79b5895f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2050,8 +2050,6 @@ lpass_wsa2macro: codec@6aa0000 {
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa2_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2063,6 +2061,9 @@ swr3: soundwire-controller@6ab0000 {
clock-names = "iface";
label = "WSA2";
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
@@ -2096,8 +2097,6 @@ lpass_rxmacro: codec@6ac0000 {
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&rx_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2109,6 +2108,9 @@ swr1: soundwire-controller@6ad0000 {
clock-names = "iface";
label = "RX";
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <1>;
qcom,dout-ports = <11>;
@@ -2142,8 +2144,6 @@ lpass_txmacro: codec@6ae0000 {
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&tx_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2161,8 +2161,6 @@ lpass_wsamacro: codec@6b00000 {
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2174,6 +2172,9 @@ swr0: soundwire-controller@6b10000 {
clock-names = "iface";
label = "WSA";
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
@@ -2203,6 +2204,9 @@ swr2: soundwire-controller@6d30000 {
clock-names = "iface";
label = "TX";
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
--
2.34.1
The MCLK clocks of codec macros have fixed 19.2 MHz frequency and
assigning clock rates is redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d8f79b5895f5..68b05ab5f65f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2045,8 +2045,6 @@ lpass_wsa2macro: codec@6aa0000 {
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
@@ -2092,9 +2090,6 @@ lpass_rxmacro: codec@6ac0000 {
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
@@ -2138,9 +2133,6 @@ lpass_txmacro: codec@6ae0000 {
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-
- assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
@@ -2156,9 +2148,6 @@ lpass_wsamacro: codec@6b00000 {
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
@@ -2233,9 +2222,6 @@ lpass_vamacro: codec@6d44000 {
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
-
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
--
2.34.1
Le 13/12/2023 à 17:28, Krzysztof Kozlowski a écrit :
> Pin configuration for Soundwire bus should be set in Soundwire
> controller nodes, not in the associated macro codec node. This
> placement change should not have big impact in general, because macro
> codec is a clock provider for Soundwire controller, thus its devices is
> probed first. However it will have impact for disabled Soundwire buses,
> e.g. WSA2, because after this change the pins will be left in default
> state.
>
> We also follow similar approach in newer SoCs, like Qualcomm SM8650.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Not tested on HW.
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++--------
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 12e55a0c7417..3b6ea9653d2a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2160,8 +2160,6 @@ wsa2macro: codec@31e0000 {
>
> #clock-cells = <0>;
> clock-output-names = "wsa2-mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&wsa2_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2173,6 +2171,9 @@ swr4: soundwire-controller@31f0000 {
> clock-names = "iface";
> label = "WSA2";
>
> + pinctrl-0 = <&wsa2_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <2>;
> qcom,dout-ports = <6>;
>
> @@ -2208,8 +2209,6 @@ rxmacro: codec@3200000 {
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&rx_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2223,6 +2222,9 @@ swr1: soundwire-controller@3210000 {
> qcom,din-ports = <0>;
> qcom,dout-ports = <5>;
>
> + pinctrl-0 = <&rx_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
> qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
> qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
> @@ -2254,8 +2256,6 @@ txmacro: codec@3220000 {
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&tx_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2275,8 +2275,6 @@ wsamacro: codec@3240000 {
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&wsa_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2288,6 +2286,9 @@ swr0: soundwire-controller@3250000 {
> clock-names = "iface";
> label = "WSA";
>
> + pinctrl-0 = <&wsa_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <2>;
> qcom,dout-ports = <6>;
>
> @@ -2318,6 +2319,9 @@ swr2: soundwire-controller@33b0000 {
> clock-names = "iface";
> label = "TX";
>
> + pinctrl-0 = <&tx_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <4>;
> qcom,dout-ports = <0>;
> qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
Reviewed-by: Neil Armstrong <[email protected]>
Le 13/12/2023 à 17:28, Krzysztof Kozlowski a écrit :
> The MCLK clocks of codec macros have fixed 19.2 MHz frequency and
> assigning clock rates is redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Not tested on HW.
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 3b6ea9653d2a..52390220d909 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2154,9 +2154,6 @@ wsa2macro: codec@31e0000 {
> <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> <&vamacro>;
> clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> - <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>, <19200000>;
>
> #clock-cells = <0>;
> clock-output-names = "wsa2-mclk";
> @@ -2203,10 +2200,6 @@ rxmacro: codec@3200000 {
> <&vamacro>;
> clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> - <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>, <19200000>;
> -
> #clock-cells = <0>;
> clock-output-names = "mclk";
> #sound-dai-cells = <1>;
> @@ -2250,9 +2243,6 @@ txmacro: codec@3220000 {
> <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> <&vamacro>;
> clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> - <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>, <19200000>;
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> @@ -2269,10 +2259,6 @@ wsamacro: codec@3240000 {
> <&vamacro>;
> clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> - <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>, <19200000>;
> -
> #clock-cells = <0>;
> clock-output-names = "mclk";
> #sound-dai-cells = <1>;
> @@ -2348,8 +2334,6 @@ vamacro: codec@33f0000 {
> <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> clock-names = "mclk", "macro", "dcodec", "npl";
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>;
>
> #clock-cells = <0>;
> clock-output-names = "fsgen";
Reviewed-by: Neil Armstrong <[email protected]>
Le 13/12/2023 à 17:28, Krzysztof Kozlowski a écrit :
> Pin configuration for Soundwire bus should be set in Soundwire
> controller nodes, not in the associated macro codec node. This
> placement change should not have big impact in general, because macro
> codec is a clock provider for Soundwire controller, thus its devices is
> probed first. However it will have impact for disabled Soundwire buses,
> e.g. WSA2, because after this change the pins will be left in default
> state.
>
> We also follow similar approach in newer SoCs, like Qualcomm SM8650.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++--------
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 1f06fd33d1ce..d8f79b5895f5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2050,8 +2050,6 @@ lpass_wsa2macro: codec@6aa0000 {
>
> #clock-cells = <0>;
> clock-output-names = "wsa2-mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&wsa2_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2063,6 +2061,9 @@ swr3: soundwire-controller@6ab0000 {
> clock-names = "iface";
> label = "WSA2";
>
> + pinctrl-0 = <&wsa2_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <4>;
> qcom,dout-ports = <9>;
>
> @@ -2096,8 +2097,6 @@ lpass_rxmacro: codec@6ac0000 {
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&rx_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2109,6 +2108,9 @@ swr1: soundwire-controller@6ad0000 {
> clock-names = "iface";
> label = "RX";
>
> + pinctrl-0 = <&rx_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <1>;
> qcom,dout-ports = <11>;
>
> @@ -2142,8 +2144,6 @@ lpass_txmacro: codec@6ae0000 {
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&tx_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2161,8 +2161,6 @@ lpass_wsamacro: codec@6b00000 {
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> - pinctrl-names = "default";
> - pinctrl-0 = <&wsa_swr_active>;
> #sound-dai-cells = <1>;
> };
>
> @@ -2174,6 +2172,9 @@ swr0: soundwire-controller@6b10000 {
> clock-names = "iface";
> label = "WSA";
>
> + pinctrl-0 = <&wsa_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <4>;
> qcom,dout-ports = <9>;
>
> @@ -2203,6 +2204,9 @@ swr2: soundwire-controller@6d30000 {
> clock-names = "iface";
> label = "TX";
>
> + pinctrl-0 = <&tx_swr_active>;
> + pinctrl-names = "default";
> +
> qcom,din-ports = <4>;
> qcom,dout-ports = <0>;
> qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
Reviewed-by: Neil Armstrong <[email protected]>
Le 13/12/2023 à 17:28, Krzysztof Kozlowski a écrit :
> The MCLK clocks of codec macros have fixed 19.2 MHz frequency and
> assigning clock rates is redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 --------------
> 1 file changed, 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index d8f79b5895f5..68b05ab5f65f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2045,8 +2045,6 @@ lpass_wsa2macro: codec@6aa0000 {
> <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> <&lpass_vamacro>;
> clock-names = "mclk", "macro", "dcodec", "fsgen";
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>;
>
> #clock-cells = <0>;
> clock-output-names = "wsa2-mclk";
> @@ -2092,9 +2090,6 @@ lpass_rxmacro: codec@6ac0000 {
> <&lpass_vamacro>;
> clock-names = "mclk", "macro", "dcodec", "fsgen";
>
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>;
> -
> #clock-cells = <0>;
> clock-output-names = "mclk";
> #sound-dai-cells = <1>;
> @@ -2138,9 +2133,6 @@ lpass_txmacro: codec@6ae0000 {
> <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> <&lpass_vamacro>;
> clock-names = "mclk", "macro", "dcodec", "fsgen";
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> -
> - assigned-clock-rates = <19200000>;
>
> #clock-cells = <0>;
> clock-output-names = "mclk";
> @@ -2156,9 +2148,6 @@ lpass_wsamacro: codec@6b00000 {
> <&lpass_vamacro>;
> clock-names = "mclk", "macro", "dcodec", "fsgen";
>
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>;
> -
> #clock-cells = <0>;
> clock-output-names = "mclk";
> #sound-dai-cells = <1>;
> @@ -2233,9 +2222,6 @@ lpass_vamacro: codec@6d44000 {
> <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> clock-names = "mclk", "macro", "dcodec";
>
> - assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> - assigned-clock-rates = <19200000>;
> -
> #clock-cells = <0>;
> clock-output-names = "fsgen";
> #sound-dai-cells = <1>;
Reviewed-by: Neil Armstrong <[email protected]>
On Wed, 13 Dec 2023 17:28:52 +0100, Krzysztof Kozlowski wrote:
> Changes in v2:
> 1. Previous submission included stale patch. Resend without it. No
> actual changes, but marking it v2 for convenience.
>
> Best regards,
> Krzysztof
>
> [...]
Applied, thanks!
[1/4] arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes
commit: 565f4d00cde3e2e7c84fc81eb72f220eb048fcf1
[2/4] arm64: dts: qcom: sm8450: drop unneeded assigned-clocks from codec macros
commit: 39859a1206e9ec47a00e7e712c5aecb4d352e001
[3/4] arm64: dts: qcom: sm8550: move Soundwire pinctrl to its nodes
commit: a25d2dbb68aab84a4431d382d6a21539ed6760e5
[4/4] arm64: dts: qcom: sm8550: drop unneeded assigned-clocks from codec macros
commit: 738387a1f8fa72c0f6db3fb659c60a1ff3c5a736
Best regards,
--
Bjorn Andersson <[email protected]>