Convert the layerscape-pci PCIe binding document to yaml format.
Additionally, changes for the layerscape-pci endpoint part:
- Add interrupt name 'pme' restriction for fsl,ls1028a-pcie-ep,
fsl,ls1046a-pcie-ep, and fsl,ls1088a-pcie-ep.
- Add register name restrictions: 'reg' and 'addr_space'. 'addr_space' is
required by snps,dw-pcie-ep.
- Add an example.
Changes for the layerscape-pci root complex part:
- Add required property: 'reg-names', "#address-cells", "#size-cells",
'device_type', 'bus-range', 'ranges', "#interrupt-cells",
'interrupt-map-mask' and 'interrupt-map'.
- Interrupt-names requirement split to each compatible string.
- Add register name restrictions: 'reg' and 'config'. 'config' is required
by snps,dw-pcie.
Signed-off-by: Frank Li <[email protected]>
---
Notes:
There are log discuss at v1. If I missed something, let me know.
Change from v2 to v3
- update commit message, show change compare txt file
- add failback compatible fsl,ls-pcie-ep.
- add commit message about 'addr_space' and 'config'.
Change from v1 to v2
- remove '|-'
- dma-coherent: true
- add interrupts and interrupt-names at before Allof
- remove ref to snps,pcie*.yaml, some reg-names are not aligned with in
drivers
- Add an example for pcie-ep
.../bindings/pci/fsl,layerscape-pcie-ep.yaml | 110 +++++++++++
.../bindings/pci/fsl,layerscape-pcie.yaml | 182 ++++++++++++++++++
.../bindings/pci/layerscape-pci.txt | 79 --------
3 files changed, 292 insertions(+), 79 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt
diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
new file mode 100644
index 0000000000000..b384a0b2fe22e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Layerscape PCIe Endpoint(EP) controller
+
+maintainers:
+ - Frank Li <[email protected]>
+
+description:
+ This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
+
+ This controller derives its clocks from the Reset Configuration Word (RCW)
+ which is used to describe the PLL settings at the time of chip-reset.
+
+ Also as per the available Reference Manuals, there is no specific 'version'
+ register available in the Freescale PCIe controller register set,
+ which can allow determining the underlying DesignWare PCIe controller version
+ information.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,ls2088a-pcie-ep
+ - fsl,ls1088a-pcie-ep
+ - fsl,ls1046a-pcie-ep
+ - fsl,ls1028a-pcie-ep
+ - fsl,lx2160ar2-pcie-ep
+ - const: fsl,ls-pcie-ep
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: regs
+ - const: addr_space
+
+ fsl,pcie-scfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to the SCFG device node. The second entry is the
+ physical PCIe controller index starting from '0'. This is used to get
+ SCFG PEXN registers.
+
+ big-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: If the PEX_LUT and PF register block is in big-endian, specify
+ this property.
+
+ dma-coherent: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ oneOf:
+ - anyOf:
+ - const: pme
+ - const: aer
+ - const: intr
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,ls1028a-pcie-ep
+ - fsl,ls1046a-pcie-ep
+ - fsl,ls1088a-pcie-ep
+ then:
+ properties:
+ interrupt-names:
+ items:
+ - const: pme
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie_ep1: pcie-ep@3400000 {
+ compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
new file mode 100644
index 0000000000000..988929729580a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Layerscape PCIe Root Complex(RC) controller
+
+maintainers:
+ - Frank Li <[email protected]>
+
+description:
+ This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
+
+ This controller derives its clocks from the Reset Configuration Word (RCW)
+ which is used to describe the PLL settings at the time of chip-reset.
+
+ Also as per the available Reference Manuals, there is no specific 'version'
+ register available in the Freescale PCIe controller register set,
+ which can allow determining the underlying DesignWare PCIe controller version
+ information.
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1021a-pcie
+ - fsl,ls2080a-pcie
+ - fsl,ls2085a-pcie
+ - fsl,ls2088a-pcie
+ - fsl,ls1088a-pcie
+ - fsl,ls1046a-pcie
+ - fsl,ls1043a-pcie
+ - fsl,ls1012a-pcie
+ - fsl,ls1028a-pcie
+ - fsl,lx2160a-pcie
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: regs
+ - const: config
+
+ fsl,pcie-scfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to the SCFG device node. The second entry is the
+ physical PCIe controller index starting from '0'. This is used to get
+ SCFG PEXN registers.
+
+ big-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: If the PEX_LUT and PF register block is in big-endian, specify
+ this property.
+
+ dma-coherent: true
+
+ msi-parent: true
+
+ iommu-map: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#address-cells"
+ - "#size-cells"
+ - device_type
+ - bus-range
+ - ranges
+ - interrupts
+ - interrupt-names
+ - "#interrupt-cells"
+ - interrupt-map-mask
+ - interrupt-map
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,lx2160a-pcie
+ then:
+ properties:
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ items:
+ - const: pme
+ - const: aer
+ - const: intr
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,ls1028a-pcie
+ - fsl,ls1046a-pcie
+ - fsl,ls1043a-pcie
+ - fsl,ls1012a-pcie
+ then:
+ properties:
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ items:
+ - const: pme
+ - const: aer
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,ls2080a-pcie
+ - fsl,ls2085a-pcie
+ - fsl,ls2088a-pcie
+ - fsl,ls1021a-pcie
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: intr
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,ls1088a-pcie
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: aer
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@3400000 {
+ compatible = "fsl,ls1088a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
deleted file mode 100644
index ee8a4791a78b4..0000000000000
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ /dev/null
@@ -1,79 +0,0 @@
-Freescale Layerscape PCIe controller
-
-This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in snps,dw-pcie.yaml.
-
-This controller derives its clocks from the Reset Configuration Word (RCW)
-which is used to describe the PLL settings at the time of chip-reset.
-
-Also as per the available Reference Manuals, there is no specific 'version'
-register available in the Freescale PCIe controller register set,
-which can allow determining the underlying DesignWare PCIe controller version
-information.
-
-Required properties:
-- compatible: should contain the platform identifier such as:
- RC mode:
- "fsl,ls1021a-pcie"
- "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
- "fsl,ls2088a-pcie"
- "fsl,ls1088a-pcie"
- "fsl,ls1046a-pcie"
- "fsl,ls1043a-pcie"
- "fsl,ls1012a-pcie"
- "fsl,ls1028a-pcie"
- EP mode:
- "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
- "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
- "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
- "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
- "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
-- reg: base addresses and lengths of the PCIe controller register blocks.
-- interrupts: A list of interrupt outputs of the controller. Must contain an
- entry for each entry in the interrupt-names property.
-- interrupt-names: It could include the following entries:
- "aer": Used for interrupt line which reports AER events when
- non MSI/MSI-X/INTx mode is used
- "pme": Used for interrupt line which reports PME events when
- non MSI/MSI-X/INTx mode is used
- "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
- which has a single interrupt line for miscellaneous controller
- events(could include AER and PME events).
-- fsl,pcie-scfg: Must include two entries.
- The first entry must be a link to the SCFG device node
- The second entry is the physical PCIe controller index starting from '0'.
- This is used to get SCFG PEXN registers
-- dma-coherent: Indicates that the hardware IP block can ensure the coherency
- of the data transferred from/to the IP block. This can avoid the software
- cache flush/invalid actions, and improve the performance significantly.
-
-Optional properties:
-- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
- this property.
-
-Example:
-
- pcie@3400000 {
- compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
- <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
- interrupt-names = "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- dma-coherent;
- num-viewport = <256>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- msi-parent = <&its>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
- };
--
2.34.1
On Wed, Feb 14, 2024 at 02:41:44PM -0500, Frank Li wrote:
> Convert the layerscape-pci PCIe binding document to yaml format.
>
> Additionally, changes for the layerscape-pci endpoint part:
> - Add interrupt name 'pme' restriction for fsl,ls1028a-pcie-ep,
> fsl,ls1046a-pcie-ep, and fsl,ls1088a-pcie-ep.
> - Add register name restrictions: 'reg' and 'addr_space'. 'addr_space' is
> required by snps,dw-pcie-ep.
> - Add an example.
>
> Changes for the layerscape-pci root complex part:
> - Add required property: 'reg-names', "#address-cells", "#size-cells",
> 'device_type', 'bus-range', 'ranges', "#interrupt-cells",
> 'interrupt-map-mask' and 'interrupt-map'.
> - Interrupt-names requirement split to each compatible string.
> - Add register name restrictions: 'reg' and 'config'. 'config' is required
> by snps,dw-pcie.
@conor
Any comments about this one?
Frank
>
> Signed-off-by: Frank Li <[email protected]>
> ---
>
> Notes:
> There are log discuss at v1. If I missed something, let me know.
>
> Change from v2 to v3
> - update commit message, show change compare txt file
> - add failback compatible fsl,ls-pcie-ep.
> - add commit message about 'addr_space' and 'config'.
>
> Change from v1 to v2
> - remove '|-'
> - dma-coherent: true
> - add interrupts and interrupt-names at before Allof
> - remove ref to snps,pcie*.yaml, some reg-names are not aligned with in
> drivers
> - Add an example for pcie-ep
>
> .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 110 +++++++++++
> .../bindings/pci/fsl,layerscape-pcie.yaml | 182 ++++++++++++++++++
> .../bindings/pci/layerscape-pci.txt | 79 --------
> 3 files changed, 292 insertions(+), 79 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> new file mode 100644
> index 0000000000000..b384a0b2fe22e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> @@ -0,0 +1,110 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Layerscape PCIe Endpoint(EP) controller
> +
> +maintainers:
> + - Frank Li <[email protected]>
> +
> +description:
> + This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
> +
> + This controller derives its clocks from the Reset Configuration Word (RCW)
> + which is used to describe the PLL settings at the time of chip-reset.
> +
> + Also as per the available Reference Manuals, there is no specific 'version'
> + register available in the Freescale PCIe controller register set,
> + which can allow determining the underlying DesignWare PCIe controller version
> + information.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,ls2088a-pcie-ep
> + - fsl,ls1088a-pcie-ep
> + - fsl,ls1046a-pcie-ep
> + - fsl,ls1028a-pcie-ep
> + - fsl,lx2160ar2-pcie-ep
> + - const: fsl,ls-pcie-ep
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: regs
> + - const: addr_space
> +
> + fsl,pcie-scfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A phandle to the SCFG device node. The second entry is the
> + physical PCIe controller index starting from '0'. This is used to get
> + SCFG PEXN registers.
> +
> + big-endian:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: If the PEX_LUT and PF register block is in big-endian, specify
> + this property.
> +
> + dma-coherent: true
> +
> + interrupts:
> + minItems: 1
> + maxItems: 2
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 2
> + oneOf:
> + - anyOf:
> + - const: pme
> + - const: aer
> + - const: intr
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls1028a-pcie-ep
> + - fsl,ls1046a-pcie-ep
> + - fsl,ls1088a-pcie-ep
> + then:
> + properties:
> + interrupt-names:
> + items:
> + - const: pme
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcie_ep1: pcie-ep@3400000 {
> + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x80 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> new file mode 100644
> index 0000000000000..988929729580a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> @@ -0,0 +1,182 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Layerscape PCIe Root Complex(RC) controller
> +
> +maintainers:
> + - Frank Li <[email protected]>
> +
> +description:
> + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
> +
> + This controller derives its clocks from the Reset Configuration Word (RCW)
> + which is used to describe the PLL settings at the time of chip-reset.
> +
> + Also as per the available Reference Manuals, there is no specific 'version'
> + register available in the Freescale PCIe controller register set,
> + which can allow determining the underlying DesignWare PCIe controller version
> + information.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,ls1021a-pcie
> + - fsl,ls2080a-pcie
> + - fsl,ls2085a-pcie
> + - fsl,ls2088a-pcie
> + - fsl,ls1088a-pcie
> + - fsl,ls1046a-pcie
> + - fsl,ls1043a-pcie
> + - fsl,ls1012a-pcie
> + - fsl,ls1028a-pcie
> + - fsl,lx2160a-pcie
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: regs
> + - const: config
> +
> + fsl,pcie-scfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A phandle to the SCFG device node. The second entry is the
> + physical PCIe controller index starting from '0'. This is used to get
> + SCFG PEXN registers.
> +
> + big-endian:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: If the PEX_LUT and PF register block is in big-endian, specify
> + this property.
> +
> + dma-coherent: true
> +
> + msi-parent: true
> +
> + iommu-map: true
> +
> + interrupts:
> + minItems: 1
> + maxItems: 3
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 3
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - "#address-cells"
> + - "#size-cells"
> + - device_type
> + - bus-range
> + - ranges
> + - interrupts
> + - interrupt-names
> + - "#interrupt-cells"
> + - interrupt-map-mask
> + - interrupt-map
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,lx2160a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 2
> + interrupt-names:
> + items:
> + - const: pme
> + - const: aer
> + - const: intr
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls1028a-pcie
> + - fsl,ls1046a-pcie
> + - fsl,ls1043a-pcie
> + - fsl,ls1012a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 2
> + interrupt-names:
> + items:
> + - const: pme
> + - const: aer
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls2080a-pcie
> + - fsl,ls2085a-pcie
> + - fsl,ls2088a-pcie
> + - fsl,ls1021a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: intr
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls1088a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: aer
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcie@3400000 {
> + compatible = "fsl,ls1088a-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> + interrupt-names = "aer";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + device_type = "pci";
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&its>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
> + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> deleted file mode 100644
> index ee8a4791a78b4..0000000000000
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -Freescale Layerscape PCIe controller
> -
> -This PCIe host controller is based on the Synopsys DesignWare PCIe IP
> -and thus inherits all the common properties defined in snps,dw-pcie.yaml.
> -
> -This controller derives its clocks from the Reset Configuration Word (RCW)
> -which is used to describe the PLL settings at the time of chip-reset.
> -
> -Also as per the available Reference Manuals, there is no specific 'version'
> -register available in the Freescale PCIe controller register set,
> -which can allow determining the underlying DesignWare PCIe controller version
> -information.
> -
> -Required properties:
> -- compatible: should contain the platform identifier such as:
> - RC mode:
> - "fsl,ls1021a-pcie"
> - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
> - "fsl,ls2088a-pcie"
> - "fsl,ls1088a-pcie"
> - "fsl,ls1046a-pcie"
> - "fsl,ls1043a-pcie"
> - "fsl,ls1012a-pcie"
> - "fsl,ls1028a-pcie"
> - EP mode:
> - "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
> - "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
> - "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
> - "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
> - "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
> -- reg: base addresses and lengths of the PCIe controller register blocks.
> -- interrupts: A list of interrupt outputs of the controller. Must contain an
> - entry for each entry in the interrupt-names property.
> -- interrupt-names: It could include the following entries:
> - "aer": Used for interrupt line which reports AER events when
> - non MSI/MSI-X/INTx mode is used
> - "pme": Used for interrupt line which reports PME events when
> - non MSI/MSI-X/INTx mode is used
> - "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
> - which has a single interrupt line for miscellaneous controller
> - events(could include AER and PME events).
> -- fsl,pcie-scfg: Must include two entries.
> - The first entry must be a link to the SCFG device node
> - The second entry is the physical PCIe controller index starting from '0'.
> - This is used to get SCFG PEXN registers
> -- dma-coherent: Indicates that the hardware IP block can ensure the coherency
> - of the data transferred from/to the IP block. This can avoid the software
> - cache flush/invalid actions, and improve the performance significantly.
> -
> -Optional properties:
> -- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
> - this property.
> -
> -Example:
> -
> - pcie@3400000 {
> - compatible = "fsl,ls1088a-pcie";
> - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> - <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "regs", "config";
> - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> - interrupt-names = "aer";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - dma-coherent;
> - num-viewport = <256>;
> - bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
> - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> - msi-parent = <&its>;
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 7>;
> - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
> - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
> - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
> - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> - };
> --
> 2.34.1
>
On Wed, Feb 14, 2024 at 02:41:44PM -0500, Frank Li wrote:
> Convert the layerscape-pci PCIe binding document to yaml format.
>
> Additionally, changes for the layerscape-pci endpoint part:
> - Add interrupt name 'pme' restriction for fsl,ls1028a-pcie-ep,
> fsl,ls1046a-pcie-ep, and fsl,ls1088a-pcie-ep.
> - Add register name restrictions: 'reg' and 'addr_space'. 'addr_space' is
> required by snps,dw-pcie-ep.
> - Add an example.
>
> Changes for the layerscape-pci root complex part:
> - Add required property: 'reg-names', "#address-cells", "#size-cells",
> 'device_type', 'bus-range', 'ranges', "#interrupt-cells",
> 'interrupt-map-mask' and 'interrupt-map'.
> - Interrupt-names requirement split to each compatible string.
> - Add register name restrictions: 'reg' and 'config'. 'config' is required
> by snps,dw-pcie.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
>
> Notes:
> There are log discuss at v1. If I missed something, let me know.
>
> Change from v2 to v3
> - update commit message, show change compare txt file
> - add failback compatible fsl,ls-pcie-ep.
> - add commit message about 'addr_space' and 'config'.
>
> Change from v1 to v2
> - remove '|-'
> - dma-coherent: true
> - add interrupts and interrupt-names at before Allof
> - remove ref to snps,pcie*.yaml, some reg-names are not aligned with in
> drivers
> - Add an example for pcie-ep
>
> .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 110 +++++++++++
> .../bindings/pci/fsl,layerscape-pcie.yaml | 182 ++++++++++++++++++
> .../bindings/pci/layerscape-pci.txt | 79 --------
> 3 files changed, 292 insertions(+), 79 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> new file mode 100644
> index 0000000000000..b384a0b2fe22e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> @@ -0,0 +1,110 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Layerscape PCIe Endpoint(EP) controller
> +
> +maintainers:
> + - Frank Li <[email protected]>
> +
> +description:
> + This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
Where's the reference to the DWC schema?
> +
> + This controller derives its clocks from the Reset Configuration Word (RCW)
> + which is used to describe the PLL settings at the time of chip-reset.
> +
> + Also as per the available Reference Manuals, there is no specific 'version'
> + register available in the Freescale PCIe controller register set,
> + which can allow determining the underlying DesignWare PCIe controller version
> + information.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,ls2088a-pcie-ep
> + - fsl,ls1088a-pcie-ep
> + - fsl,ls1046a-pcie-ep
> + - fsl,ls1028a-pcie-ep
> + - fsl,lx2160ar2-pcie-ep
> + - const: fsl,ls-pcie-ep
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: regs
> + - const: addr_space
> +
> + fsl,pcie-scfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A phandle to the SCFG device node. The second entry is the
> + physical PCIe controller index starting from '0'. This is used to get
> + SCFG PEXN registers.
> +
> + big-endian:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: If the PEX_LUT and PF register block is in big-endian, specify
> + this property.
> +
> + dma-coherent: true
> +
> + interrupts:
> + minItems: 1
> + maxItems: 2
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 2
> + oneOf:
> + - anyOf:
> + - const: pme
> + - const: aer
> + - const: intr
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls1028a-pcie-ep
> + - fsl,ls1046a-pcie-ep
> + - fsl,ls1088a-pcie-ep
> + then:
> + properties:
> + interrupt-names:
> + items:
> + - const: pme
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcie_ep1: pcie-ep@3400000 {
> + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x80 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
Not documented and deprecated.
> + status = "disabled";
Examples should be enabled.
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> new file mode 100644
> index 0000000000000..988929729580a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> @@ -0,0 +1,182 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Layerscape PCIe Root Complex(RC) controller
> +
> +maintainers:
> + - Frank Li <[email protected]>
> +
> +description:
> + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
> +
> + This controller derives its clocks from the Reset Configuration Word (RCW)
> + which is used to describe the PLL settings at the time of chip-reset.
> +
> + Also as per the available Reference Manuals, there is no specific 'version'
> + register available in the Freescale PCIe controller register set,
> + which can allow determining the underlying DesignWare PCIe controller version
> + information.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,ls1021a-pcie
> + - fsl,ls2080a-pcie
> + - fsl,ls2085a-pcie
> + - fsl,ls2088a-pcie
> + - fsl,ls1088a-pcie
> + - fsl,ls1046a-pcie
> + - fsl,ls1043a-pcie
> + - fsl,ls1012a-pcie
> + - fsl,ls1028a-pcie
> + - fsl,lx2160a-pcie
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: regs
> + - const: config
> +
> + fsl,pcie-scfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A phandle to the SCFG device node. The second entry is the
> + physical PCIe controller index starting from '0'. This is used to get
> + SCFG PEXN registers.
> +
> + big-endian:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: If the PEX_LUT and PF register block is in big-endian, specify
> + this property.
> +
> + dma-coherent: true
> +
> + msi-parent: true
> +
> + iommu-map: true
> +
> + interrupts:
> + minItems: 1
> + maxItems: 3
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 3
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - "#address-cells"
> + - "#size-cells"
> + - device_type
> + - bus-range
This should never be required unless you have some restriction in the
h/w. DWC generally doesn't.
> + - ranges
> + - interrupts
> + - interrupt-names
> + - "#interrupt-cells"
> + - interrupt-map-mask
> + - interrupt-map
The common PCI and DWC schemas already make most of these required, so
you don't need to here.
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,lx2160a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 2
> + interrupt-names:
> + items:
> + - const: pme
> + - const: aer
> + - const: intr
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls1028a-pcie
> + - fsl,ls1046a-pcie
> + - fsl,ls1043a-pcie
> + - fsl,ls1012a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 2
> + interrupt-names:
> + items:
> + - const: pme
> + - const: aer
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls2080a-pcie
> + - fsl,ls2085a-pcie
> + - fsl,ls2088a-pcie
> + - fsl,ls1021a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: intr
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - fsl,ls1088a-pcie
> + then:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: aer
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcie@3400000 {
> + compatible = "fsl,ls1088a-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> + interrupt-names = "aer";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + device_type = "pci";
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&its>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
> + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> + };
> + };
> +...
On Mon, Feb 19, 2024 at 04:36:10PM -0500, Frank Li wrote:
> On Wed, Feb 14, 2024 at 02:41:44PM -0500, Frank Li wrote:
> > Convert the layerscape-pci PCIe binding document to yaml format.
> >
> > Additionally, changes for the layerscape-pci endpoint part:
> > - Add interrupt name 'pme' restriction for fsl,ls1028a-pcie-ep,
> > fsl,ls1046a-pcie-ep, and fsl,ls1088a-pcie-ep.
> > - Add register name restrictions: 'reg' and 'addr_space'. 'addr_space' is
> > required by snps,dw-pcie-ep.
> > - Add an example.
> >
> > Changes for the layerscape-pci root complex part:
> > - Add required property: 'reg-names', "#address-cells", "#size-cells",
> > 'device_type', 'bus-range', 'ranges', "#interrupt-cells",
> > 'interrupt-map-mask' and 'interrupt-map'.
> > - Interrupt-names requirement split to each compatible string.
> > - Add register name restrictions: 'reg' and 'config'. 'config' is required
> > by snps,dw-pcie.
>
> @conor
> Any comments about this one?
Sorry I missed this - I've been sick the last week and probably
overzealously deleted stuff from my mailbox. I see Rob replied to this
as I was in the process of reading through the patch, so I only left two
minor comments here.
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie_ep1: pcie-ep@3400000 {
Nit: unused label.
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,lx2160a-pcie
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
> > + interrupt-names:
> > + items:
> > + - const: pme
> > + - const: aer
> > + - const: intr
You set maxItems to 2 but there are 3 names. That doesn't seem right!
Chers,
Conor.
On Thu, Feb 22, 2024 at 12:30:48PM -0600, Rob Herring wrote:
> On Wed, Feb 14, 2024 at 02:41:44PM -0500, Frank Li wrote:
> > Convert the layerscape-pci PCIe binding document to yaml format.
> >
> > Additionally, changes for the layerscape-pci endpoint part:
> > - Add interrupt name 'pme' restriction for fsl,ls1028a-pcie-ep,
> > fsl,ls1046a-pcie-ep, and fsl,ls1088a-pcie-ep.
> > - Add register name restrictions: 'reg' and 'addr_space'. 'addr_space' is
> > required by snps,dw-pcie-ep.
> > - Add an example.
> >
> > Changes for the layerscape-pci root complex part:
> > - Add required property: 'reg-names', "#address-cells", "#size-cells",
> > 'device_type', 'bus-range', 'ranges', "#interrupt-cells",
> > 'interrupt-map-mask' and 'interrupt-map'.
> > - Interrupt-names requirement split to each compatible string.
> > - Add register name restrictions: 'reg' and 'config'. 'config' is required
> > by snps,dw-pcie.
> >
> > Signed-off-by: Frank Li <[email protected]>
> > ---
> >
> > Notes:
> > There are log discuss at v1. If I missed something, let me know.
> >
> > Change from v2 to v3
> > - update commit message, show change compare txt file
> > - add failback compatible fsl,ls-pcie-ep.
> > - add commit message about 'addr_space' and 'config'.
> >
> > Change from v1 to v2
> > - remove '|-'
> > - dma-coherent: true
> > - add interrupts and interrupt-names at before Allof
> > - remove ref to snps,pcie*.yaml, some reg-names are not aligned with in
> > drivers
> > - Add an example for pcie-ep
> >
> > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 110 +++++++++++
> > .../bindings/pci/fsl,layerscape-pcie.yaml | 182 ++++++++++++++++++
> > .../bindings/pci/layerscape-pci.txt | 79 --------
> > 3 files changed, 292 insertions(+), 79 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> > create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> > new file mode 100644
> > index 0000000000000..b384a0b2fe22e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
> > @@ -0,0 +1,110 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Freescale Layerscape PCIe Endpoint(EP) controller
> > +
> > +maintainers:
> > + - Frank Li <[email protected]>
> > +
> > +description:
> > + This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
>
> Where's the reference to the DWC schema?
reg-names have not alignned with dwc schema yet because this driver
upstream early. ('reg' vs 'dbi') If Add dwc schema, which will cause many
warning when do dtb check.
I plan update driver and this binding in future to add dwc schema.
Is it okay? or I add ref dwc schama, and omit dtb_check warning now?
Frank
>
> > +
> > + This controller derives its clocks from the Reset Configuration Word (RCW)
> > + which is used to describe the PLL settings at the time of chip-reset.
> > +
> > + Also as per the available Reference Manuals, there is no specific 'version'
> > + register available in the Freescale PCIe controller register set,
> > + which can allow determining the underlying DesignWare PCIe controller version
> > + information.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - fsl,ls2088a-pcie-ep
> > + - fsl,ls1088a-pcie-ep
> > + - fsl,ls1046a-pcie-ep
> > + - fsl,ls1028a-pcie-ep
> > + - fsl,lx2160ar2-pcie-ep
> > + - const: fsl,ls-pcie-ep
> > +
> > + reg:
> > + maxItems: 2
> > +
> > + reg-names:
> > + items:
> > + - const: regs
> > + - const: addr_space
> > +
> > + fsl,pcie-scfg:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A phandle to the SCFG device node. The second entry is the
> > + physical PCIe controller index starting from '0'. This is used to get
> > + SCFG PEXN registers.
> > +
> > + big-endian:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description: If the PEX_LUT and PF register block is in big-endian, specify
> > + this property.
> > +
> > + dma-coherent: true
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 2
> > + oneOf:
> > + - anyOf:
> > + - const: pme
> > + - const: aer
> > + - const: intr
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,ls1028a-pcie-ep
> > + - fsl,ls1046a-pcie-ep
> > + - fsl,ls1088a-pcie-ep
> > + then:
> > + properties:
> > + interrupt-names:
> > + items:
> > + - const: pme
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie_ep1: pcie-ep@3400000 {
> > + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep";
> > + reg = <0x00 0x03400000 0x0 0x00100000
> > + 0x80 0x00000000 0x8 0x00000000>;
> > + reg-names = "regs", "addr_space";
> > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> > + interrupt-names = "pme";
>
> > + num-ib-windows = <6>;
> > + num-ob-windows = <8>;
>
> Not documented and deprecated.
>
> > + status = "disabled";
>
> Examples should be enabled.
>
> > + };
> > + };
> > +...
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> > new file mode 100644
> > index 0000000000000..988929729580a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> > @@ -0,0 +1,182 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Freescale Layerscape PCIe Root Complex(RC) controller
> > +
> > +maintainers:
> > + - Frank Li <[email protected]>
> > +
> > +description:
> > + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
> > +
> > + This controller derives its clocks from the Reset Configuration Word (RCW)
> > + which is used to describe the PLL settings at the time of chip-reset.
> > +
> > + Also as per the available Reference Manuals, there is no specific 'version'
> > + register available in the Freescale PCIe controller register set,
> > + which can allow determining the underlying DesignWare PCIe controller version
> > + information.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,ls1021a-pcie
> > + - fsl,ls2080a-pcie
> > + - fsl,ls2085a-pcie
> > + - fsl,ls2088a-pcie
> > + - fsl,ls1088a-pcie
> > + - fsl,ls1046a-pcie
> > + - fsl,ls1043a-pcie
> > + - fsl,ls1012a-pcie
> > + - fsl,ls1028a-pcie
> > + - fsl,lx2160a-pcie
> > +
> > + reg:
> > + maxItems: 2
> > +
> > + reg-names:
> > + items:
> > + - const: regs
> > + - const: config
> > +
> > + fsl,pcie-scfg:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A phandle to the SCFG device node. The second entry is the
> > + physical PCIe controller index starting from '0'. This is used to get
> > + SCFG PEXN registers.
> > +
> > + big-endian:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description: If the PEX_LUT and PF register block is in big-endian, specify
> > + this property.
> > +
> > + dma-coherent: true
> > +
> > + msi-parent: true
> > +
> > + iommu-map: true
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 3
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 3
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - "#address-cells"
> > + - "#size-cells"
> > + - device_type
> > + - bus-range
>
> This should never be required unless you have some restriction in the
> h/w. DWC generally doesn't.
>
> > + - ranges
> > + - interrupts
> > + - interrupt-names
> > + - "#interrupt-cells"
> > + - interrupt-map-mask
> > + - interrupt-map
>
> The common PCI and DWC schemas already make most of these required, so
> you don't need to here.
>
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,lx2160a-pcie
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
> > + interrupt-names:
> > + items:
> > + - const: pme
> > + - const: aer
> > + - const: intr
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,ls1028a-pcie
> > + - fsl,ls1046a-pcie
> > + - fsl,ls1043a-pcie
> > + - fsl,ls1012a-pcie
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
> > + interrupt-names:
> > + items:
> > + - const: pme
> > + - const: aer
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,ls2080a-pcie
> > + - fsl,ls2085a-pcie
> > + - fsl,ls2088a-pcie
> > + - fsl,ls1021a-pcie
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 1
> > + interrupt-names:
> > + items:
> > + - const: intr
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,ls1088a-pcie
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 1
> > + interrupt-names:
> > + items:
> > + - const: aer
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie@3400000 {
> > + compatible = "fsl,ls1088a-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> > + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
> > + interrupt-names = "aer";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + dma-coherent;
> > + device_type = "pci";
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&its>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
> > + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
> > + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> > + };
> > + };
> > +...