Added a description, required properties and appropriate compatibles
for all the SoCs that are supported by microchip.
Signed-off-by: Durai Manickam KR <[email protected]>
---
.../devicetree/bindings/dma/atmel-dma.txt | 42 -------------
.../bindings/dma/microchip,at91-dma.yaml | 71 ++++++++++++++++++++++
2 files changed, 71 insertions(+), 42 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
deleted file mode 100644
index f69bcf5a6343..000000000000
--- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* Atmel Direct Memory Access Controller (DMA)
-
-Required properties:
-- compatible: Should be "atmel,<chip>-dma".
-- reg: Should contain DMA registers location and length.
-- interrupts: Should contain DMA interrupt.
-- #dma-cells: Must be <2>, used to represent the number of integer cells in
-the dmas property of client devices.
-
-Example:
-
-dma0: dma@ffffec00 {
- compatible = "atmel,at91sam9g45-dma";
- reg = <0xffffec00 0x200>;
- interrupts = <21>;
- #dma-cells = <2>;
-};
-
-DMA clients connected to the Atmel DMA controller must use the format
-described in the dma.txt file, using a three-cell specifier for each channel:
-a phandle plus two integer cells.
-The three cells in order are:
-
-1. A phandle pointing to the DMA controller.
-2. The memory interface (16 most significant bits), the peripheral interface
-(16 less significant bits).
-3. Parameters for the at91 DMA configuration register which are device
-dependent:
- - bit 7-0: peripheral identifier for the hardware handshaking interface. The
- identifier can be different for tx and rx.
- - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
-
-Example:
-
-i2c0@i2c@f8010000 {
- compatible = "atmel,at91sam9x5-i2c";
- reg = <0xf8010000 0x100>;
- interrupts = <9 4 6>;
- dmas = <&dma0 1 7>,
- <&dma0 1 8>;
- dma-names = "tx", "rx";
-};
diff --git a/Documentation/devicetree/bindings/dma/microchip,at91-dma.yaml b/Documentation/devicetree/bindings/dma/microchip,at91-dma.yaml
new file mode 100644
index 000000000000..a0a582902e4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/microchip,at91-dma.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/microchip,at91-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Direct Memory Access Controller (DMA)
+
+maintainers:
+ - Ludovic Desroches <[email protected]>
+ - Tudor Ambarus <[email protected]>
+
+description: |
+ The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
+ peripheral to a destination peripheral over one or more AMBA buses. One channel
+ is required for each source/destination pair. In the most basic configuration,
+ the DMAC has one master interface and one channel. The master interface reads
+ the data from a source and writes it to a destination. Two AMBA transfers are
+ required for each DMAC data transfer. This is also known as a dual-access transfer.
+ The DMAC is programmed via the APB interface.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - atmel,at91sam9g45-dma
+ - atmel,at91sam9rl-dma
+ reg:
+ description: Should contain DMA registers location and length.
+ maxItems: 1
+
+ interrupts:
+ description: Should contain the DMA interrupts associated to the DMA channels.
+ maxItems: 1
+
+ "#dma-cells":
+ description:
+ Must be <2>, used to represent the number of integer cells in the dmas
+ property of client devices.
+ const: 2
+
+ clocks:
+ description: Should contain a clock specifier for each entry in clock-names.
+ maxItems: 1
+
+ clock-names:
+ description: Should contain the clock of the DMA controller.
+ const: dma_clk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#dma-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ dma0: dma-controller@ffffec00 {
+ compatible = "atmel,at91sam9g45-dma";
+ reg = <0xffffec00 0x200>;
+ interrupts = <21>;
+ #dma-cells = <2>;
+ clocks = <&pmc 2 20>;
+ clock-names = "dma_clk";
+ };
+
+...
---
base-commit: 7e90b5c295ec1e47c8ad865429f046970c549a66
change-id: 20240214-dmac-5f48fd7f3b9d
Best regards,
--
Durai Manickam KR <[email protected]>
On Thu, Feb 15, 2024 at 04:15:44PM +0530, Durai Manickam KR wrote:
> Added a description, required properties and appropriate compatibles
> for all the SoCs that are supported by microchip.
>
> Signed-off-by: Durai Manickam KR <[email protected]>
> ---
> .../devicetree/bindings/dma/atmel-dma.txt | 42 -------------
> .../bindings/dma/microchip,at91-dma.yaml | 71 ++++++++++++++++++++++
> 2 files changed, 71 insertions(+), 42 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
> deleted file mode 100644
> index f69bcf5a6343..000000000000
> --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -* Atmel Direct Memory Access Controller (DMA)
> -
> -Required properties:
> -- compatible: Should be "atmel,<chip>-dma".
> -- reg: Should contain DMA registers location and length.
> -- interrupts: Should contain DMA interrupt.
> -- #dma-cells: Must be <2>, used to represent the number of integer cells in
> -the dmas property of client devices.
> -
> -Example:
> -
> -dma0: dma@ffffec00 {
> - compatible = "atmel,at91sam9g45-dma";
> - reg = <0xffffec00 0x200>;
> - interrupts = <21>;
> - #dma-cells = <2>;
> -};
> -
> -DMA clients connected to the Atmel DMA controller must use the format
> -described in the dma.txt file, using a three-cell specifier for each channel:
> -a phandle plus two integer cells.
> -The three cells in order are:
> -
> -1. A phandle pointing to the DMA controller.
> -2. The memory interface (16 most significant bits), the peripheral interface
> -(16 less significant bits).
> -3. Parameters for the at91 DMA configuration register which are device
> -dependent:
> - - bit 7-0: peripheral identifier for the hardware handshaking interface. The
> - identifier can be different for tx and rx.
> - - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
> -
> -Example:
> -
> -i2c0@i2c@f8010000 {
> - compatible = "atmel,at91sam9x5-i2c";
> - reg = <0xf8010000 0x100>;
> - interrupts = <9 4 6>;
> - dmas = <&dma0 1 7>,
> - <&dma0 1 8>;
> - dma-names = "tx", "rx";
> -};
> diff --git a/Documentation/devicetree/bindings/dma/microchip,at91-dma.yaml b/Documentation/devicetree/bindings/dma/microchip,at91-dma.yaml
> new file mode 100644
> index 000000000000..a0a582902e4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/microchip,at91-dma.yaml
Filename matching the compatible please.
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/microchip,at91-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Atmel Direct Memory Access Controller (DMA)
> +
> +maintainers:
> + - Ludovic Desroches <[email protected]>
> + - Tudor Ambarus <[email protected]>
> +
> +description: |
The | is not needed.
> + The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
> + peripheral to a destination peripheral over one or more AMBA buses. One channel
> + is required for each source/destination pair. In the most basic configuration,
> + the DMAC has one master interface and one channel. The master interface reads
> + the data from a source and writes it to a destination. Two AMBA transfers are
> + required for each DMAC data transfer. This is also known as a dual-access transfer.
> + The DMAC is programmed via the APB interface.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - atmel,at91sam9g45-dma
> + - atmel,at91sam9rl-dma
> + reg:
> + description: Should contain DMA registers location and length.
Drop the description from these common properties.
> + maxItems: 1
> +
> + interrupts:
> + description: Should contain the DMA interrupts associated to the DMA channels.
> + maxItems: 1
> +
> + "#dma-cells":
> + description:
> + Must be <2>, used to represent the number of integer cells in the dmas
> + property of client devices.
You've lost the description of how these cells work, which is somewhat
unique and needs to be preserved.
This is the only property that needs a description.
> + const: 2
> +
> + clocks:
> + description: Should contain a clock specifier for each entry in clock-names.
> + maxItems: 1
> +
> + clock-names:
> + description: Should contain the clock of the DMA controller.
> + const: dma_clk
This is a new addition? You should call out in the commit message wat
you've added that was not in th text binding.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#dma-cells"
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + dma0: dma-controller@ffffec00 {
Drop the label, its not used.
Thanks,
Conor.
> + compatible = "atmel,at91sam9g45-dma";
> + reg = <0xffffec00 0x200>;
> + interrupts = <21>;
> + #dma-cells = <2>;
> + clocks = <&pmc 2 20>;
> + clock-names = "dma_clk";
> + };
> +
> +...
>
> ---
> base-commit: 7e90b5c295ec1e47c8ad865429f046970c549a66
> change-id: 20240214-dmac-5f48fd7f3b9d
>
> Best regards,
> --
> Durai Manickam KR <[email protected]>
>