Hi,
Thanks Angelo for the feedback, this version should fix all issues you
reported as well as the kernel test robot issues.
Thanks for any feedback!
Best,
Markus
Based on v6.4-rc1
Changes in v6:
- Change flags field to be u8 instead of u32
- Use macro concatenation to simplify BUS_PROT macros:
BUS_PROT_WR(_hwip, ...) etc.
- Use the final bit values for scpsys_bus_prot_flags from the beginning
of the series.
- Changed scpsys_domain_data->caps to be u16 to accommodate the new flag
MTK_SCPD_STRICT_BUS_PROTECTION.
Changes in v5:
- Create defines for all registers and bits in mt8365 power domain patch
- Redesign scpsys_bus_prot_data to use flags to store reg_update,
clr_ack as well as the difference between SMI and INFRACFG. The code
uses the appropriate regmap depending on the flags.
- The WAY_EN patch now uses two flags, one for inverted operations
'BUS_PROT_INVERTED' and one to use infracfg-nao for the status flags
'BUS_PROT_STA_COMPONENT_INFRA_NAO'.
Changes in v4:
- Redesigned WAY_EN patch and split it up in smaller patches.
- Added two documentation patches.
- Added mediatek,infracfg-nao field to the binding.
Changes in v3:
- Mainly redesigned WAY_EN patch to be easier to understand
- Rebased onto v6.0-rc1
- Several other stuff that is described in the individual patches
Changes in v2:
- Updated error handling path for scpsys_power_on()
- Minor updates described in each patch
Previous versions:
v1 - https://lore.kernel.org/linux-mediatek/[email protected]/
v2 - https://lore.kernel.org/linux-mediatek/[email protected]/
v3 - https://lore.kernel.org/linux-mediatek/[email protected]/
v4 - https://lore.kernel.org/linux-arm-kernel/[email protected]/
Alexandre Bailon (2):
soc: mediatek: Add support for WAY_EN operations
soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap
Fabien Parent (2):
dt-bindings: power: Add MT8365 power domains
soc: mediatek: pm-domains: Add support for MT8365
Markus Schneider-Pargmann (4):
soc: mediatek: pm-domains: Move bools to a flags field
soc: mediatek: pm-domains: Split bus_prot_mask
soc: mediatek: pm-domains: Create bus protection operation functions
soc: mediatek: pm-domains: Unify configuration for infracfg and smi
.../power/mediatek,power-controller.yaml | 6 +
drivers/soc/mediatek/mt6795-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8167-pm-domains.h | 20 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8183-pm-domains.h | 125 ++++++----
drivers/soc/mediatek/mt8186-pm-domains.h | 236 ++++++++++--------
drivers/soc/mediatek/mt8188-pm-domains.h | 223 +++++++++++------
drivers/soc/mediatek/mt8192-pm-domains.h | 112 ++++++---
drivers/soc/mediatek/mt8195-pm-domains.h | 199 +++++++++------
drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 157 ++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 51 ++--
.../dt-bindings/power/mediatek,mt8365-power.h | 19 ++
include/linux/soc/mediatek/infracfg.h | 41 +++
14 files changed, 972 insertions(+), 446 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
--
2.40.1
From: Fabien Parent <[email protected]>
Add the needed board data to support MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
---
drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 5 +
include/linux/soc/mediatek/infracfg.h | 41 +++++
3 files changed, 243 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediatek/mt8365-pm-domains.h
new file mode 100644
index 000000000000..3d83d49eaa7c
--- /dev/null
+++ b/drivers/soc/mediatek/mt8365-pm-domains.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mediatek,mt8365-power.h>
+
+/*
+ * MT8365 power domain support
+ */
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
+ BUS_PROT_WR(INFRA, _mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
+ BUS_PROT_WR(INFRA, _mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
+
+#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
+ BUS_PROT_WR(SMI, BIT(port), \
+ MT8365_SMI_COMMON_CLAMP_EN_SET, \
+ MT8365_SMI_COMMON_CLAMP_EN_CLR, \
+ MT8365_SMI_COMMON_CLAMP_EN)
+
+#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
+ _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
+ BUS_PROT_COMPONENT_INFRA | \
+ BUS_PROT_STA_COMPONENT_INFRA_NAO | \
+ BUS_PROT_INVERTED | \
+ BUS_PROT_REG_UPDATE)
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
+ [MT8365_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x30c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
+ MT8365_BUS_PROT_WAY_EN(
+ MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
+ MT8365_INFRA_TOPAXI_SI0_CTL,
+ MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI0_STA),
+ MT8365_BUS_PROT_WAY_EN(
+ MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
+ MT8365_INFRA_TOPAXI_SI2_CTL,
+ MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI2_STA),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
+ },
+ .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
+ },
+ [MT8365_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
+ },
+ },
+ [MT8365_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(12, 8),
+ .sram_pdn_ack_bits = GENMASK(17, 13),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8365_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8365_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
+ },
+ },
+ [MT8365_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0370,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
+ },
+ },
+ [MT8365_POWER_DOMAIN_APU] = {
+ .name = "apu",
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x0378,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(14, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 15),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
+ },
+ },
+ [MT8365_POWER_DOMAIN_DSP] = {
+ .name = "dsp",
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x037C,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+};
+
+static const struct scpsys_soc_data mt8365_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt8365,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
+};
+
+#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 632285bf0d44..261367476488 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -24,6 +24,7 @@
#include "mt8188-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
+#include "mt8365-pm-domains.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8195-power-controller",
.data = &mt8195_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt8365-power-controller",
+ .data = &mt8365_scpsys_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 07f67b3d8e97..f853397697b5 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -2,6 +2,47 @@
#ifndef __SOC_MEDIATEK_INFRACFG_H
#define __SOC_MEDIATEK_INFRACFG_H
+#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
+#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30)
+# define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31)
+
+#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
+# define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24)
+#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
+# define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14)
+#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
+# define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6)
+#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
+# define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5)
+
+#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
+#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
+#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
+
#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
--
2.40.1
From: Alexandre Bailon <[email protected]>
This updates the power domain to support WAY_EN operations. WAY_EN
operations on mt8365 are using a different component to check for the
acknowledgment, namely the infracfg-nao component. Also to enable a way
it the bit needs to be cleared while disabling a way needs a bit to be
set. To support these two operations two flags are added,
BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
another regmap is created if the INFRA_NAO capability is set.
This operation is required by the mt8365 for the MM power domain.
Signed-off-by: Alexandre Bailon <[email protected]>
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
---
drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 3 +++
2 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 3cdf62c0b6bd..608b5eab8146 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -44,6 +44,7 @@ struct scpsys_domain {
struct clk_bulk_data *clks;
int num_subsys_clks;
struct clk_bulk_data *subsys_clks;
+ struct regmap *infracfg_nao;
struct regmap *infracfg;
struct regmap *smi;
struct regulator *supply;
@@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
return pd->infracfg;
}
+static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
+ const struct scpsys_bus_prot_data *bpd)
+{
+ if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
+ return pd->infracfg_nao;
+ else
+ return scpsys_bus_protect_get_regmap(pd, bpd);
+}
+
static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
+ u32 expected_ack;
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
+ expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0);
+
if (bpd->flags & BUS_PROT_REG_UPDATE)
regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask);
else
@@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK)
return 0;
- return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
- val, !(val & sta_mask),
+ return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
+ val, (val & sta_mask) == expected_ack,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
static int scpsys_bus_protect_set(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
+ struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 val;
u32 sta_mask = bpd->bus_prot_sta_mask;
@@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
else
regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask);
- return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta,
+ return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta,
val, (val & sta_mask) == sta_mask,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
@@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
if (!bpd->bus_prot_set_clr_mask)
break;
- ret = scpsys_bus_protect_set(pd, bpd);
+ if (bpd->flags & BUS_PROT_INVERTED)
+ ret = scpsys_bus_protect_clear(pd, bpd);
+ else
+ ret = scpsys_bus_protect_set(pd, bpd);
if (ret)
return ret;
}
@@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
if (!bpd->bus_prot_set_clr_mask)
continue;
- ret = scpsys_bus_protect_clear(pd, bpd);
+ if (bpd->flags & BUS_PROT_INVERTED)
+ ret = scpsys_bus_protect_set(pd, bpd);
+ else
+ ret = scpsys_bus_protect_clear(pd, bpd);
if (ret)
return ret;
}
@@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
return ERR_CAST(pd->smi);
}
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
+ pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
+ if (IS_ERR(pd->infracfg_nao))
+ return ERR_CAST(pd->infracfg_nao);
+ } else {
+ pd->infracfg_nao = NULL;
+ }
+
num_clks = of_clk_get_parent_count(node);
if (num_clks > 0) {
/* Calculate number of subsys_clks */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 209f68dcaeac..17c033217704 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -11,6 +11,7 @@
/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
#define MTK_SCPD_ALWAYS_ON BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
+#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -45,8 +46,10 @@
enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1),
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
+ BUS_PROT_INVERTED = BIT(3),
BUS_PROT_COMPONENT_INFRA = BIT(4),
BUS_PROT_COMPONENT_SMI = BIT(5),
+ BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6),
};
#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \
--
2.40.1
Il 27/06/23 15:10, Markus Schneider-Pargmann ha scritto:
> From: Fabien Parent <[email protected]>
>
> Add the needed board data to support MT8365 SoC.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
..snip..
> diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> index 07f67b3d8e97..f853397697b5 100644
> --- a/include/linux/soc/mediatek/infracfg.h
> +++ b/include/linux/soc/mediatek/infracfg.h
> @@ -2,6 +2,47 @@
> #ifndef __SOC_MEDIATEK_INFRACFG_H
> #define __SOC_MEDIATEK_INFRACFG_H
>
> +#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
> +#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
> +#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
> +# define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
Personally, I like this kind of indentation, but more like
#define REGADDRESS
#define REGMASK
instead of
#define REGADDRESS
# define REGMASK
...but this doesn't count, because this header doesn't follow *either* formats,
not my preferred, nor yours: this means that, for consistency, you have to follow
what's in there already, so you have to change that to
#define REGADDRESS
#define REGMASK
...so please change that to retain consistency across the infracfg.h header,
after which:
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
P.S.: I'm sorry for not noticing this in v5.
Cheers,
Angelo
Il 27/06/23 15:10, Markus Schneider-Pargmann ha scritto:
> From: Alexandre Bailon <[email protected]>
>
> This updates the power domain to support WAY_EN operations. WAY_EN
> operations on mt8365 are using a different component to check for the
> acknowledgment, namely the infracfg-nao component. Also to enable a way
> it the bit needs to be cleared while disabling a way needs a bit to be
> set. To support these two operations two flags are added,
> BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
> another regmap is created if the INFRA_NAO capability is set.
>
> This operation is required by the mt8365 for the MM power domain.
>
> Signed-off-by: Alexandre Bailon <[email protected]>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Hi Angelo,
On Tue, Jul 04, 2023 at 12:31:23PM +0200, AngeloGioacchino Del Regno wrote:
> Il 27/06/23 15:10, Markus Schneider-Pargmann ha scritto:
> > From: Fabien Parent <[email protected]>
> >
> > Add the needed board data to support MT8365 SoC.
> >
> > Signed-off-by: Fabien Parent <[email protected]>
> > Signed-off-by: Markus Schneider-Pargmann <[email protected]>
>
>
>
> ..snip..
>
>
> > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> > index 07f67b3d8e97..f853397697b5 100644
> > --- a/include/linux/soc/mediatek/infracfg.h
> > +++ b/include/linux/soc/mediatek/infracfg.h
> > @@ -2,6 +2,47 @@
> > #ifndef __SOC_MEDIATEK_INFRACFG_H
> > #define __SOC_MEDIATEK_INFRACFG_H
> > +#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
> > +#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
> > +#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
> > +# define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
>
> Personally, I like this kind of indentation, but more like
>
> #define REGADDRESS
> #define REGMASK
>
> instead of
>
> #define REGADDRESS
> # define REGMASK
>
> ...but this doesn't count, because this header doesn't follow *either* formats,
> not my preferred, nor yours: this means that, for consistency, you have to follow
> what's in there already, so you have to change that to
>
> #define REGADDRESS
> #define REGMASK
>
> ...so please change that to retain consistency across the infracfg.h header,
> after which:
>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Thank you for your review. I fixed both issues you pointed out for the
next version.
Best,
Markus
Reviewed-by: Alexandre Mergnat <[email protected]>
Tested-by: Alexandre Mergnat <[email protected]>
On 27/06/2023 15:10, Markus Schneider-Pargmann wrote:
> This updates the power domain to support WAY_EN operations. WAY_EN
> operations on mt8365 are using a different component to check for the
> acknowledgment, namely the infracfg-nao component. Also to enable a way
> it the bit needs to be cleared while disabling a way needs a bit to be
> set. To support these two operations two flags are added,
> BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally
> another regmap is created if the INFRA_NAO capability is set.
>
> This operation is required by the mt8365 for the MM power domain.
--
Regards,
Alexandre
Reviewed-by: Alexandre Mergnat <[email protected]>
Tested-by: Alexandre Mergnat <[email protected]>
On 27/06/2023 15:10, Markus Schneider-Pargmann wrote:
> Add the needed board data to support MT8365 SoC.
--
Regards,
Alexandre