2022-05-02 14:15:43

by Viraj Shah

Subject: [PATCH v1 1/4] soc: imx8mm: gpcv2: Power sequence for DISP

As per the imx8mm reference manual, read bit 25(GPC_DISPMIX_
PWRDNACKN) of the power handshake register and wait for ack during
power on/off.

Signed-off-by: Viraj Shah <[email protected]>
---
drivers/soc/imx/gpcv2.c | 36 +++++++++++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 3cb123016b3e..8ee70c30964f 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -254,11 +254,24 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
+ *
+ * As per "5.2.9.5 Example Code 5" in i.MX-8MMini-yhsc.pdf
+ * Display power on section checks for bit 25 of
+ * Power handshake register to be cleared.
*/
- ret = regmap_read_poll_timeout(domain->regmap,
- GPC_PU_PGC_SW_PUP_REQ, reg_val,
- !(reg_val & domain->bits.pxx),
- 0, USEC_PER_MSEC);
+ if (domain->bits.pxx == IMX8MM_DISPMIX_SW_Pxx_REQ) {
+ regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ BIT(7), BIT(7));
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PWRHSK, reg_val,
+ !(reg_val & IMX8MM_DISPMIX_HSK_PWRDNACKN),
+ 0, USEC_PER_MSEC);
+ } else
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PGC_SW_PUP_REQ, reg_val,
+ !(reg_val & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+
if (ret) {
dev_err(domain->dev, "failed to command PGC\n");
goto out_clk_disable;
@@ -355,11 +368,24 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
+ *
+ * As per "5.2.9.5 Example Code 5" in i.MX-8MMini-yhsc.pdf
+ * Display power on section checks for bit 25 of
+ * Power handshake register to be set.
*/
- ret = regmap_read_poll_timeout(domain->regmap,
+ if (domain->bits.pxx == IMX8MM_DISPMIX_SW_Pxx_REQ) {
+ regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
+ BIT(7));
+ ret = regmap_read_poll_timeout(domain->regmap,
+ GPC_PU_PWRHSK, reg_val,
+ !(reg_val & IMX8MM_DISPMIX_HSK_PWRDNACKN),
+ 0, USEC_PER_MSEC);
+ } else {
+ ret = regmap_read_poll_timeout(domain->regmap,
GPC_PU_PGC_SW_PDN_REQ, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
+ }
if (ret) {
dev_err(domain->dev, "failed to command PGC\n");
goto out_clk_disable;
--
2.20.1

2022-05-02 16:52:22

by Lucas Stach

Subject: Re: [PATCH v1 1/4] soc: imx8mm: gpcv2: Power sequence for DISP

Hi Viraj,

Am Montag, dem 02.05.2022 um 12:02 +0200 schrieb Viraj Shah:
> As per the imx8mm reference manual, read bit 25(GPC_DISPMIX_
> PWRDNACKN) of the power handshake register and wait for ack during
> power on/off.
>
> Signed-off-by: Viraj Shah <[email protected]>
> ---
> drivers/soc/imx/gpcv2.c | 36 +++++++++++++++++++++++++++++++-----
> 1 file changed, 31 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 3cb123016b3e..8ee70c30964f 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -254,11 +254,24 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> + *
> + * As per "5.2.9.5 Example Code 5" in i.MX-8MMini-yhsc.pdf
> + * Display power on section checks for bit 25 of
> + * Power handshake register to be cleared.
> */
> - ret = regmap_read_poll_timeout(domain->regmap,
> - GPC_PU_PGC_SW_PUP_REQ, reg_val,
> - !(reg_val & domain->bits.pxx),
> - 0, USEC_PER_MSEC);
> + if (domain->bits.pxx == IMX8MM_DISPMIX_SW_Pxx_REQ) {
> + regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> + BIT(7), BIT(7));
> + ret = regmap_read_poll_timeout(domain->regmap,
> + GPC_PU_PWRHSK, reg_val,
> + !(reg_val & IMX8MM_DISPMIX_HSK_PWRDNACKN),
> + 0, USEC_PER_MSEC);
> + } else
> + ret = regmap_read_poll_timeout(domain->regmap,
> + GPC_PU_PGC_SW_PUP_REQ, reg_val,
> + !(reg_val & domain->bits.pxx),
> + 0, USEC_PER_MSEC);
> +
The driver already handles the PWRHSK bits at the appropriate places.
Please do not hack in random sequences from the reference manual for
specific domains. Also you can not wait for the handshake ack in the
power up sequence, as the blk-ctrl driver only enables the ADB clock,
_after_ the GPC power domain has been powered up, so there is no way
for it to so the handshake here. See the comments in the blk-ctrl
driver.

Regards,
Lucas

> if (ret) {
> dev_err(domain->dev, "failed to command PGC\n");
> goto out_clk_disable;
> @@ -355,11 +368,24 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> + *
> + * As per "5.2.9.5 Example Code 5" in i.MX-8MMini-yhsc.pdf
> + * Display power on section checks for bit 25 of
> + * Power handshake register to be set.
> */
> - ret = regmap_read_poll_timeout(domain->regmap,
> + if (domain->bits.pxx == IMX8MM_DISPMIX_SW_Pxx_REQ) {
> + regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
> + BIT(7));
> + ret = regmap_read_poll_timeout(domain->regmap,
> + GPC_PU_PWRHSK, reg_val,
> + !(reg_val & IMX8MM_DISPMIX_HSK_PWRDNACKN),
> + 0, USEC_PER_MSEC);
> + } else {
> + ret = regmap_read_poll_timeout(domain->regmap,
> GPC_PU_PGC_SW_PDN_REQ, reg_val,
> !(reg_val & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> + }
> if (ret) {
> dev_err(domain->dev, "failed to command PGC\n");
> goto out_clk_disable;