From: "Ivan T. Ivanov" <[email protected]>
Add pin, group and function definitions for SPI#8
controller.
Signed-off-by: Ivan T. Ivanov <[email protected]>
---
drivers/pinctrl/pinctrl-msm8x74.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c
index f944bf2..9aeeb38 100644
--- a/drivers/pinctrl/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/pinctrl-msm8x74.c
@@ -406,6 +406,7 @@ enum msm8x74_functions {
MSM_MUX_blsp_i2c6,
MSM_MUX_blsp_i2c11,
MSM_MUX_blsp_spi1,
+ MSM_MUX_blsp_spi8,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uart8,
MSM_MUX_slimbus,
@@ -416,6 +417,9 @@ static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" };
+static const char * const blsp_spi8_groups[] = {
+ "gpio45", "gpio46", "gpio47", "gpio48"
+};
static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" };
static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" };
static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
@@ -425,6 +429,7 @@ static const struct msm_function msm8x74_functions[] = {
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi8),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart8),
FUNCTION(slimbus),
@@ -476,10 +481,10 @@ static const struct msm_pingroup msm8x74_groups[] = {
PINGROUP(42, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(43, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(44, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA),
- PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA),
- PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(45, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
+ PINGROUP(46, blsp_spi8, blsp_uart8, NA, NA, NA, NA, NA),
+ PINGROUP(47, blsp_spi8, NA, NA, NA, NA, NA, NA),
+ PINGROUP(48, blsp_spi8, NA, NA, NA, NA, NA, NA),
PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
--
1.7.9.5
From: "Ivan T. Ivanov" <[email protected]>
Add the pin control node and pin definitions of SPI8.
Signed-off-by: Ivan T. Ivanov <[email protected]>
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9e5dadb..395603f 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -117,5 +117,34 @@
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
+
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8974-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 208 0>;
+
+ spi8_default: spi8_default {
+ mosi {
+ pins = "gpio45";
+ function = "blsp_spi8";
+ };
+ miso {
+ pins = "gpio46";
+ function = "blsp_spi8";
+ };
+ cs {
+ pins = "gpio47";
+ function = "blsp_spi8";
+ };
+ clk {
+ pins = "gpio48";
+ function = "blsp_spi8";
+ };
+ };
+ };
};
};
--
1.7.9.5
On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov <[email protected]> wrote:
> From: "Ivan T. Ivanov" <[email protected]>
>
> Add pin, group and function definitions for SPI#8
> controller.
>
> Signed-off-by: Ivan T. Ivanov <[email protected]>
Bj?rn can I have your ACK on this patch?
Yours,
Linus Walleij
On Mon, Feb 10, 2014 at 1:14 AM, Linus Walleij <[email protected]> wrote:
> On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov <[email protected]> wrote:
>
>> From: "Ivan T. Ivanov" <[email protected]>
>>
>> Add pin, group and function definitions for SPI#8
>> controller.
>>
>> Signed-off-by: Ivan T. Ivanov <[email protected]>
>
> Bj?rn can I have your ACK on this patch?
Indeed,
Acked-by: Bjorn Andersson <[email protected]>
On Thu, Feb 6, 2014 at 7:28 AM, Ivan T. Ivanov <[email protected]> wrote:
> From: "Ivan T. Ivanov" <[email protected]>
>
> Add the pin control node and pin definitions of SPI8.
>
> Signed-off-by: Ivan T. Ivanov <[email protected]>
> ---
> arch/arm/boot/dts/qcom-msm8974.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 9e5dadb..395603f 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -117,5 +117,34 @@
> clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> clock-names = "core", "iface";
> };
> +
> + msmgpio: pinctrl@fd510000 {
> + compatible = "qcom,msm8974-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <0 208 0>;
> +
> + spi8_default: spi8_default {
> + mosi {
> + pins = "gpio45";
> + function = "blsp_spi8";
> + };
> + miso {
> + pins = "gpio46";
> + function = "blsp_spi8";
> + };
> + cs {
> + pins = "gpio47";
> + function = "blsp_spi8";
> + };
> + clk {
> + pins = "gpio48";
> + function = "blsp_spi8";
> + };
> + };
> + };
> };
> };
Nice, listing it like this makes it easy to add the electrical
properties when inheriting these nodes, closer to the product dts
files.
Reviewed-by: Bjorn Andersson <[email protected]>
On Feb 10, 2014, at 12:55 PM, Bjorn Andersson <[email protected]> wrote:
> On Thu, Feb 6, 2014 at 7:28 AM, Ivan T. Ivanov <[email protected]> wrote:
>> From: "Ivan T. Ivanov" <[email protected]>
>>
>> Add the pin control node and pin definitions of SPI8.
>>
>> Signed-off-by: Ivan T. Ivanov <[email protected]>
>> ---
>> arch/arm/boot/dts/qcom-msm8974.dtsi | 29 +++++++++++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
>> index 9e5dadb..395603f 100644
>> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
>> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
>> @@ -117,5 +117,34 @@
>> clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
>> clock-names = "core", "iface";
>> };
>> +
>> + msmgpio: pinctrl@fd510000 {
>> + compatible = "qcom,msm8974-pinctrl";
>> + reg = <0xfd510000 0x4000>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + interrupts = <0 208 0>;
>> +
>> + spi8_default: spi8_default {
>> + mosi {
>> + pins = "gpio45";
>> + function = "blsp_spi8";
>> + };
>> + miso {
>> + pins = "gpio46";
>> + function = "blsp_spi8";
>> + };
>> + cs {
>> + pins = "gpio47";
>> + function = "blsp_spi8";
>> + };
>> + clk {
>> + pins = "gpio48";
>> + function = "blsp_spi8";
>> + };
>> + };
>> + };
>> };
>> };
>
> Nice, listing it like this makes it easy to add the electrical
> properties when inheriting these nodes, closer to the product dts
> files.
>
> Reviewed-by: Bjorn Andersson <[email protected]>
Linus,
I can take the .dts patch via the linux-qcom tree to keep it with other DT changes if you want to provide an ack.
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov <[email protected]> wrote:
> From: "Ivan T. Ivanov" <[email protected]>
>
> Add pin, group and function definitions for SPI#8
> controller.
>
> Signed-off-by: Ivan T. Ivanov <[email protected]>
Patch applied with Bj?rn's ACK.
Thanks!
Linus Walleij
On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov <[email protected]> wrote:
> From: "Ivan T. Ivanov" <[email protected]>
>
> Add the pin control node and pin definitions of SPI8.
>
> Signed-off-by: Ivan T. Ivanov <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Kumar, please take this through your qcom tree.
Yours,
Linus Walleij
On Feb 24, 2014, at 3:57 AM, Linus Walleij <[email protected]> wrote:
> On Thu, Feb 6, 2014 at 4:28 PM, Ivan T. Ivanov <[email protected]> wrote:
>
>> From: "Ivan T. Ivanov" <[email protected]>
>>
>> Add the pin control node and pin definitions of SPI8.
>>
>> Signed-off-by: Ivan T. Ivanov <[email protected]>
>
> Acked-by: Linus Walleij <[email protected]>
>
> Kumar, please take this through your qcom tree.
applied to qcom/dt
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Thu, Feb 6, 2014 at 9:28 AM, Ivan T. Ivanov <[email protected]> wrote:
> + spi8_default: spi8_default {
> + mosi {
> + pins = "gpio45";
> + function = "blsp_spi8";
> + };
> + miso {
> + pins = "gpio46";
> + function = "blsp_spi8";
> + };
> + cs {
> + pins = "gpio47";
> + function = "blsp_spi8";
> + };
> + clk {
> + pins = "gpio48";
> + function = "blsp_spi8";
> + };
I'm confused by this. Isn't this information already defined in the
pinctrl-msm8x74.c driver?
static const char * const blsp_spi8_groups[] = {
"gpio45", "gpio46", "gpio47", "gpio48"
};
On Thu, Feb 6, 2014 at 9:28 AM, Ivan T. Ivanov <[email protected]> wrote:
> + msmgpio: pinctrl@fd510000 {
> + compatible = "qcom,msm8974-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <0 208 0>;
> +
> + spi8_default: spi8_default {
> + mosi {
> + pins = "gpio45";
> + function = "blsp_spi8";
> + };
> + miso {
> + pins = "gpio46";
> + function = "blsp_spi8";
> + };
> + cs {
> + pins = "gpio47";
> + function = "blsp_spi8";
> + };
> + clk {
> + pins = "gpio48";
> + function = "blsp_spi8";
> + };
> + };
> + };
> };
> };
I'm confused by this. Isn't this information already defined in the
pinctrl-msm8x74.c driver?
static const char * const blsp_spi8_groups[] = {
"gpio45", "gpio46", "gpio47", "gpio48"
};
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by The Linux Foundation
Hi,
On Mon, 2014-04-07 at 18:53 -0500, Timur Tabi wrote:
> On Thu, Feb 6, 2014 at 9:28 AM, Ivan T. Ivanov <[email protected]> wrote:
> > + spi8_default: spi8_default {
> > + mosi {
> > + pins = "gpio45";
> > + function = "blsp_spi8";
> > + };
> > + miso {
> > + pins = "gpio46";
> > + function = "blsp_spi8";
> > + };
> > + cs {
> > + pins = "gpio47";
> > + function = "blsp_spi8";
> > + };
> > + clk {
> > + pins = "gpio48";
> > + function = "blsp_spi8";
> > + };
>
> I'm confused by this. Isn't this information already defined in the
> pinctrl-msm8x74.c driver?
>
> static const char * const blsp_spi8_groups[] = {
> "gpio45", "gpio46", "gpio47", "gpio48"
> };
I am not sure that I understand the question. This is one of
possible ways to describe relationship between pins and functions.
As they are described is visible what is their real purpose.
Regards,
Ivan
Ivan T. Ivanov wrote:
>> >I'm confused by this. Isn't this information already defined in the
>> >pinctrl-msm8x74.c driver?
>> >
>> >static const char * const blsp_spi8_groups[] = {
>> > "gpio45", "gpio46", "gpio47", "gpio48"
>> >};
> I am not sure that I understand the question. This is one of
> possible ways to describe relationship between pins and functions.
> As they are described is visible what is their real purpose.
Ok, let me rephrase.
The 8x74 pinctrl driver already contains this information. It already
defines a "blsp_spi8" group consisting of GPIOs 45, 46, 47, and 48.
This patch adds that same exact information into the device tree. Why
are we duplicating that information? Why add it to the device tree when
it's already in the driver (and already working).
Also, I don't see any code anywhere that uses these new device tree nodes.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by The Linux Foundation.
On Tue, 2014-04-08 at 07:33 -0500, Timur Tabi wrote:
> Ivan T. Ivanov wrote:
> >> >I'm confused by this. Isn't this information already defined in the
> >> >pinctrl-msm8x74.c driver?
> >> >
> >> >static const char * const blsp_spi8_groups[] = {
> >> > "gpio45", "gpio46", "gpio47", "gpio48"
> >> >};
> > I am not sure that I understand the question. This is one of
> > possible ways to describe relationship between pins and functions.
> > As they are described is visible what is their real purpose.
>
> Ok, let me rephrase.
>
> The 8x74 pinctrl driver already contains this information. It already
> defines a "blsp_spi8" group consisting of GPIOs 45, 46, 47, and 48.
>
> This patch adds that same exact information into the device tree. Why
> are we duplicating that information? Why add it to the device tree when
> it's already in the driver (and already working).
Probably. It was my natural way of thinking. Pin have a functions.
It is easier if I measure signals to just look at the device
tree file. What are you suggesting?
>
> Also, I don't see any code anywhere that uses these new device tree nodes.
This is easy to fix :-).
Regards,
Ivan
On 04/08/2014 08:46 AM, Ivan T. Ivanov wrote:
>> >This patch adds that same exact information into the device tree. Why
>> >are we duplicating that information? Why add it to the device tree when
>> >it's already in the driver (and already working).
> Probably. It was my natural way of thinking. Pin have a functions.
> It is easier if I measure signals to just look at the device
> tree file. What are you suggesting?
Back in July, Qualcomm submitted a patch that added this information
into the device tree:
http://marc.info/?t=137185166100003&r=1&w=2
However, this was rejected. Now it appears that this information is
again being added to the device tree, but it's being accepted. What's
different now?
Another problem is that these device tree changes makes it difficult to
support ACPI. It's easy to move information between the drivers and the
device tree, because they're kept together. It's not so easy with ACPI.
I'm trying to add ACPI support to the 8x74 pinctrl driver, but it's a
moving target.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by the Linux Foundation.
On 04/08/2014 09:18 AM, Timur Tabi wrote:
>
> Back in July, Qualcomm submitted a patch that added this information
> into the device tree:
>
> http://marc.info/?t=137185166100003&r=1&w=2
>
> However, this was rejected. Now it appears that this information is
> again being added to the device tree, but it's being accepted. What's
> different now?
After re-reading the documentation and having someone kindly explain
this to me, I understand it now. The device tree is only specifying
specific configurations that a driver wants, not the sum total of all
possible groupings.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by the Linux Foundation.
On Tue, Apr 8, 2014 at 7:18 AM, Timur Tabi <[email protected]> wrote:
> On 04/08/2014 08:46 AM, Ivan T. Ivanov wrote:
>>>
>>> >This patch adds that same exact information into the device tree. Why
>>> >are we duplicating that information? Why add it to the device tree when
>>> >it's already in the driver (and already working).
>
>
>> Probably. It was my natural way of thinking. Pin have a functions.
>> It is easier if I measure signals to just look at the device
>> tree file. What are you suggesting?
>
>
> Back in July, Qualcomm submitted a patch that added this information into
> the device tree:
>
> http://marc.info/?t=137185166100003&r=1&w=2
>
> However, this was rejected. Now it appears that this information is again
> being added to the device tree, but it's being accepted. What's different
> now?
The difference is that in the first proposal pins, groups and
functions where defined in DT, in the accepted proposal the devicetree
merely selects pins, functions and their configuration.
>
> Another problem is that these device tree changes makes it difficult to
> support ACPI. It's easy to move information between the drivers and the
> device tree, because they're kept together. It's not so easy with ACPI.
> I'm trying to add ACPI support to the 8x74 pinctrl driver, but it's a moving
> target.
The DT bindings for 8x74 is all standard pinctrl, so I presume that
what you should be looking at is how pinctrl and acpi is interacting,
not the specific case of 8x74...
Maybe Linus have some input on this?
Regards,
Bjorn
On Tue, Apr 8, 2014 at 8:39 PM, Bjorn Andersson <[email protected]> wrote:
> On Tue, Apr 8, 2014 at 7:18 AM, Timur Tabi <[email protected]> wrote:
>> Back in July, Qualcomm submitted a patch that added this information into
>> the device tree:
>>
>> http://marc.info/?t=137185166100003&r=1&w=2
>>
>> However, this was rejected. Now it appears that this information is again
>> being added to the device tree, but it's being accepted. What's different
>> now?
>
> The difference is that in the first proposal pins, groups and
> functions where defined in DT, in the accepted proposal the devicetree
> merely selects pins, functions and their configuration.
Yes and I point this out in this reply:
http://marc.info/?l=linux-kernel&m=137650778624988&w=2
>> Another problem is that these device tree changes makes it difficult to
>> support ACPI. It's easy to move information between the drivers and the
>> device tree, because they're kept together. It's not so easy with ACPI.
>> I'm trying to add ACPI support to the 8x74 pinctrl driver, but it's a moving
>> target.
>
> The DT bindings for 8x74 is all standard pinctrl, so I presume that
> what you should be looking at is how pinctrl and acpi is interacting,
> not the specific case of 8x74...
>
> Maybe Linus have some input on this?
AFAIK ACPI has nothing like official pin control support, last time I
checked it was limited to some custom information that could be
tagged onto GPIO pins (REALLY a bad idea, we don't shoehorn
pin control into the concept of GPIO).
If you are adding this then tell me which ACPI standard document
you're using for it, so I can read and criticize it.
I was under the impression that the ambition of ACPI was to hide
away all "complex stuff" such as pin control in the firmware
and just e.g. call the devices into some D-state and the
pin business happens in the firmware.
Yours,
Linus Walleij