2022-11-26 20:38:07

by Samuel Holland

Subject: [PATCH 4/5] clk: sunxi-ng: d1: Mark cpux clock as critical

From: András Szemző <[email protected]>

Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU.
In that case, the CPUs are driven from the 'cpux' clock, so it needs
to be marked as critical.

Signed-off-by: András Szemző <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
index 8ef3cdeb7962..c5a7df93602c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
@@ -240,7 +240,7 @@ static const struct clk_parent_data cpux_parents[] = {
{ .hw = &pll_periph0_800M_clk.common.hw },
};
static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
- 0x500, 24, 3, CLK_SET_RATE_PARENT);
+ 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);

static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
--
2.37.4

2022-12-03 01:30:51

by Andre Przywara

Subject: Re: [PATCH 4/5] clk: sunxi-ng: d1: Mark cpux clock as critical

On Sat, 26 Nov 2022 13:13:18 -0600
Samuel Holland <[email protected]> wrote:

> From: András Szemző <[email protected]>
>
> Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU.
> In that case, the CPUs are driven from the 'cpux' clock, so it needs
> to be marked as critical.

Yes, my board hangs without that patch somewhere into the boot, and
this patch fixes it.

Can you also explain in the commit message why this is needed? IIRC
the CPU node itself does not "consume" the clock, this would only be
done by DVFS code?
And it might be worth noting that we do this for every other
Allwinner SoC as well.

> Signed-off-by: András Szemző <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>

Reviewed-by: Andre Przywara <[email protected]>

Cheers,
Andre

> ---
>
> drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
> index 8ef3cdeb7962..c5a7df93602c 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
> @@ -240,7 +240,7 @@ static const struct clk_parent_data cpux_parents[] = {
> { .hw = &pll_periph0_800M_clk.common.hw },
> };
> static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
> - 0x500, 24, 3, CLK_SET_RATE_PARENT);
> + 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
>
> static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
> static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",

2022-12-05 20:45:38

by Jernej Škrabec

Subject: Re: [PATCH 4/5] clk: sunxi-ng: d1: Mark cpux clock as critical

Dne sobota, 26. november 2022 ob 20:13:18 CET je Samuel Holland napisal(a):
> From: András Szemző <[email protected]>
>
> Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU.
> In that case, the CPUs are driven from the 'cpux' clock, so it needs
> to be marked as critical.
>
> Signed-off-by: András Szemző <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>

Acked-by: Jernej Skrabec <[email protected]>

Best regards,
Jernej