This series implements EDAC support for error reporting on
Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
based ECC mechanism to report errors.
This series has been tested on SC7180, SDM845, SM8150 SoCs with
Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
Cortex-A76.
This implementation is platform specific in contrast to the
patch posted last time for generic error reporting on arm cortex
implementations with RAS extensions by Kyle Yan.
- https://patchwork.kernel.org/patch/10161955/
Downstream implementation of this can be found at:
- https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/drivers/edac/kryo_arm64_edac.c?h=msm-4.14
Sai Prakash Ranjan (2):
dt-bindings: edac: Add DT bindings for Kryo EDAC
drivers: edac: Add EDAC support for Kryo CPU caches
.../bindings/edac/qcom-kryo-edac.yaml | 67 ++
MAINTAINERS | 7 +
drivers/edac/Kconfig | 20 +
drivers/edac/Makefile | 1 +
drivers/edac/qcom_kryo_edac.c | 679 ++++++++++++++++++
5 files changed, 774 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/qcom-kryo-edac.yaml
create mode 100644 drivers/edac/qcom_kryo_edac.c
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Hi Sai,
(CC: +Tyler)
On 05/12/2019 09:52, Sai Prakash Ranjan wrote:
> This series implements EDAC support for error reporting on
> Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
> in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
> based ECC mechanism to report errors.
>
> This series has been tested on SC7180, SDM845, SM8150 SoCs with
> Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
> Cortex-A76.
>
> This implementation is platform specific in contrast to the
> patch posted last time for generic error reporting on arm cortex
> implementations with RAS extensions by Kyle Yan.
> - https://patchwork.kernel.org/patch/10161955/
I think that series was dropped because it was too soc-specific and overlaps with the v8.2
kernel first support. That series was superseded by:
lore.kernel.org/r/[email protected]
Can you work with Tyler on a combined series? The combined support may need to look quite
different. (DT and big/little being the obvious differences).
I'm afraid this is the tip of the kernel-first-RAS iceberg.
Thanks,
James
Hello James,
On 2020-01-16 00:16, James Morse wrote:
> Hi Sai,
>
> (CC: +Tyler)
>
> On 05/12/2019 09:52, Sai Prakash Ranjan wrote:
>> This series implements EDAC support for error reporting on
>> Kryo{3,4}XX CPU caches L1,L2, L3-SCU. All the cores(big.LITTLE)
>> in Kryo{3,4}XX CPUs implement RAS extensions and use interrupt
>> based ECC mechanism to report errors.
>>
>> This series has been tested on SC7180, SDM845, SM8150 SoCs with
>> Kryo{3,4}XX CPU cores based on ARM Cortex-A55, Cortex-A75 and
>> Cortex-A76.
>>
>> This implementation is platform specific in contrast to the
>> patch posted last time for generic error reporting on arm cortex
>> implementations with RAS extensions by Kyle Yan.
>> - https://patchwork.kernel.org/patch/10161955/
>
> I think that series was dropped because it was too soc-specific and
> overlaps with the v8.2
> kernel first support. That series was superseded by:
> lore.kernel.org/r/[email protected]
>
> Can you work with Tyler on a combined series? The combined support may
> need to look quite
> different. (DT and big/little being the obvious differences).
>
> I'm afraid this is the tip of the kernel-first-RAS iceberg.
>
Sorry for the delayed response. Sure, I will take a look at the series
posted by Tyler.
It might take some time to come up with that but should be doable with
your review :)
Thanks,
Sai
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member
of Code Aurora Forum, hosted by The Linux Foundation