In full duplex mode, rx overflow error is observed. To overcome the error,
wait until the complete data got received and proceed further.
Fixes: 17f84b793c01 ("spi: lantiq-ssc: add support for Lantiq SSC SPI controller")
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/spi-lantiq-ssc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index 1fd7ee53d4510..44600fb71c484 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -184,6 +184,7 @@ struct lantiq_ssc_spi {
unsigned int tx_fifo_size;
unsigned int rx_fifo_size;
unsigned int base_cs;
+ unsigned int fdx_tx_level;
};
static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
@@ -481,6 +482,7 @@ static void tx_fifo_write(struct lantiq_ssc_spi *spi)
u32 data;
unsigned int tx_free = tx_fifo_free(spi);
+ spi->fdx_tx_level = 0;
while (spi->tx_todo && tx_free) {
switch (spi->bits_per_word) {
case 2 ... 8:
@@ -509,6 +511,7 @@ static void tx_fifo_write(struct lantiq_ssc_spi *spi)
lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
tx_free--;
+ spi->fdx_tx_level++;
}
}
@@ -520,6 +523,13 @@ static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
u32 data;
unsigned int rx_fill = rx_fifo_level(spi);
+ /*
+ * Wait until all expected data to be shifted in.
+ * Otherwise, rx overrun may occur.
+ */
+ while (rx_fill != spi->fdx_tx_level)
+ rx_fill = rx_fifo_level(spi);
+
while (rx_fill) {
data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
--
2.11.0
Address of Interrupt control registers are different on new chipsets.
So move them to SoC specific data structure.
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/spi-lantiq-ssc.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index 1073a70a4beba..98e1c5d807597 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -50,8 +50,6 @@
#define LTQ_SPI_RXCNT 0x84
#define LTQ_SPI_DMACON 0xec
#define LTQ_SPI_IRNEN 0xf4
-#define LTQ_SPI_IRNICR 0xf8
-#define LTQ_SPI_IRNCR 0xfc
#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
@@ -159,8 +157,10 @@
#define LTQ_SPI_IRNEN_ALL 0x1F
struct lantiq_ssc_hwcfg {
- unsigned int irnen_r;
- unsigned int irnen_t;
+ unsigned int irnen_r;
+ unsigned int irnen_t;
+ unsigned int irncr;
+ unsigned int irnicr;
};
struct lantiq_ssc_spi {
@@ -793,13 +793,17 @@ static int lantiq_ssc_transfer_one(struct spi_master *master,
}
static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
- .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
- .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
+ .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
+ .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
+ .irnicr = 0xF8,
+ .irncr = 0xFC,
};
static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
- .irnen_r = LTQ_SPI_IRNEN_R_XRX,
- .irnen_t = LTQ_SPI_IRNEN_T_XRX,
+ .irnen_r = LTQ_SPI_IRNEN_R_XRX,
+ .irnen_t = LTQ_SPI_IRNEN_T_XRX,
+ .irnicr = 0xF8,
+ .irncr = 0xFC,
};
static const struct of_device_id lantiq_ssc_match[] = {
--
2.11.0
On newer chipsets interrupt need to be acknowledged as they use
different interrupt controller which does not acknowledge the
interrupts automatically.
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/spi-lantiq-ssc.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index 98e1c5d807597..cbe019f995999 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -161,6 +161,7 @@ struct lantiq_ssc_hwcfg {
unsigned int irnen_t;
unsigned int irncr;
unsigned int irnicr;
+ bool irq_ack;
};
struct lantiq_ssc_spi {
@@ -623,9 +624,14 @@ static void rx_request(struct lantiq_ssc_spi *spi)
static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
{
struct lantiq_ssc_spi *spi = data;
+ const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
+ u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
unsigned long flags;
spin_lock_irqsave(&spi->lock, flags);
+ if (hwcfg->irq_ack)
+ lantiq_ssc_writel(spi, val, hwcfg->irncr);
+
if (spi->tx) {
if (spi->rx && spi->rx_todo)
rx_fifo_read_full_duplex(spi);
@@ -660,13 +666,18 @@ static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
{
struct lantiq_ssc_spi *spi = data;
+ const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
+ u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
unsigned long flags;
if (!(stat & LTQ_SPI_STAT_ERRORS))
return IRQ_NONE;
spin_lock_irqsave(&spi->lock, flags);
+ if (hwcfg->irq_ack)
+ lantiq_ssc_writel(spi, val, hwcfg->irncr);
+
if (stat & LTQ_SPI_STAT_RUE)
dev_err(spi->dev, "receive underflow error\n");
if (stat & LTQ_SPI_STAT_TUE)
@@ -797,6 +808,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
.irnicr = 0xF8,
.irncr = 0xFC,
+ .irq_ack = false,
};
static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
@@ -804,6 +816,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
.irnen_t = LTQ_SPI_IRNEN_T_XRX,
.irnicr = 0xF8,
.irncr = 0xFC,
+ .irq_ack = false,
};
static const struct of_device_id lantiq_ssc_match[] = {
--
2.11.0
Moving interrupt configuration to SoC specific data structure helps to add
support for newer SoCs on which SPI controller with lesser interrupt lines
compared to existing chipsets.
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/spi-lantiq-ssc.c | 64 +++++++++++++++++++++++++++-----------------
1 file changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index a0d1f82d309f9..2a433d9b5d8fe 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -150,7 +150,10 @@
#define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
#define LTQ_SPI_IRNEN_ALL 0x1F
+struct lantiq_ssc_spi;
+
struct lantiq_ssc_hwcfg {
+ int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
unsigned int irnen_r;
unsigned int irnen_t;
unsigned int irncr;
@@ -800,7 +803,40 @@ static int lantiq_ssc_transfer_one(struct spi_master *master,
return transfer_start(spi, spidev, t);
}
+static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
+{
+ int irq, err;
+
+ irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
+ 0, LTQ_SPI_RX_IRQ_NAME, spi);
+ if (err)
+ return err;
+
+ irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_xmit_interrupt,
+ 0, LTQ_SPI_TX_IRQ_NAME, spi);
+
+ if (err)
+ return err;
+
+ irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_irq(&pdev->dev, irq, lantiq_ssc_err_interrupt,
+ 0, LTQ_SPI_ERR_IRQ_NAME, spi);
+ return err;
+}
+
static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
+ .cfg_irq = lantiq_cfg_irq,
.irnen_r = LTQ_SPI_IRNEN_R_XWAY,
.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
.irnicr = 0xF8,
@@ -810,6 +846,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
};
static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
+ .cfg_irq = lantiq_cfg_irq,
.irnen_r = LTQ_SPI_IRNEN_R_XRX,
.irnen_t = LTQ_SPI_IRNEN_T_XRX,
.irnicr = 0xF8,
@@ -833,9 +870,9 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
struct lantiq_ssc_spi *spi;
const struct lantiq_ssc_hwcfg *hwcfg;
const struct of_device_id *match;
- int err, rx_irq, tx_irq, err_irq;
u32 id, supports_dma, revision;
unsigned int num_cs;
+ int err;
match = of_match_device(lantiq_ssc_match, dev);
if (!match) {
@@ -844,18 +881,6 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
}
hwcfg = match->data;
- rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
- if (rx_irq < 0)
- return -ENXIO;
-
- tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
- if (tx_irq < 0)
- return -ENXIO;
-
- err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
- if (err_irq < 0)
- return -ENXIO;
-
master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
if (!master)
return -ENOMEM;
@@ -871,18 +896,7 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
goto err_master_put;
}
- err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
- 0, LTQ_SPI_RX_IRQ_NAME, spi);
- if (err)
- goto err_master_put;
-
- err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
- 0, LTQ_SPI_TX_IRQ_NAME, spi);
- if (err)
- goto err_master_put;
-
- err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
- 0, LTQ_SPI_ERR_IRQ_NAME, spi);
+ err = hwcfg->cfg_irq(pdev, spi);
if (err)
goto err_master_put;
--
2.11.0
Add support to SPI controller on Intel Atom based Lightning Mountain SoC
which reuses Lantiq SPI controller IP.
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/Kconfig | 4 ++--
drivers/spi/spi-lantiq-ssc.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 878849a33781b..be40310840d04 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -498,11 +498,11 @@ config SPI_NPCM_PSPI
config SPI_LANTIQ_SSC
tristate "Lantiq SSC SPI controller"
- depends on LANTIQ || COMPILE_TEST
+ depends on LANTIQ || X86 || COMPILE_TEST
help
This driver supports the Lantiq SSC SPI controller in master
mode. This controller is found on Intel (former Lantiq) SoCs like
- the Danube, Falcon, xRX200, xRX300.
+ the Danube, Falcon, xRX200, xRX300, Lightning Mountain.
config SPI_OC_TINY
tristate "OpenCores tiny SPI"
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index 2a433d9b5d8fe..81cb1c06e2ce5 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -703,6 +703,24 @@ static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
return IRQ_HANDLED;
}
+static irqreturn_t intel_lgm_ssc_isr(int irq, void *data)
+{
+ struct lantiq_ssc_spi *spi = data;
+ const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
+ u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
+
+ if (!(val & LTQ_SPI_IRNEN_ALL))
+ return IRQ_NONE;
+
+ if (val & LTQ_SPI_IRNEN_E)
+ return lantiq_ssc_err_interrupt(irq, data);
+
+ if ((val & hwcfg->irnen_t) || (val & hwcfg->irnen_r))
+ return lantiq_ssc_xmit_interrupt(irq, data);
+
+ return IRQ_HANDLED;
+}
+
static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
struct spi_transfer *t)
{
@@ -803,6 +821,17 @@ static int lantiq_ssc_transfer_one(struct spi_master *master,
return transfer_start(spi, spidev, t);
}
+static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
+{
+ int irq;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi);
+}
+
static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
{
int irq, err;
@@ -855,10 +884,21 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
.irq_ack = false,
};
+static const struct lantiq_ssc_hwcfg intel_ssc_lgm = {
+ .cfg_irq = intel_lgm_cfg_irq,
+ .irnen_r = LTQ_SPI_IRNEN_R_XRX,
+ .irnen_t = LTQ_SPI_IRNEN_T_XRX,
+ .irnicr = 0xFC,
+ .irncr = 0xF8,
+ .fifo_size_mask = GENMASK(7, 0),
+ .irq_ack = true,
+};
+
static const struct of_device_id lantiq_ssc_match[] = {
{ .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
{ .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
{ .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
+ { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
{},
};
MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
--
2.11.0
Existing driver supports only single core SoC. New multicore platforms uses
the same driver/IP so SMP support is required. This patch adds multicore
support in the driver.
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/spi-lantiq-ssc.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index 44600fb71c484..1073a70a4beba 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -623,7 +623,9 @@ static void rx_request(struct lantiq_ssc_spi *spi)
static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
{
struct lantiq_ssc_spi *spi = data;
+ unsigned long flags;
+ spin_lock_irqsave(&spi->lock, flags);
if (spi->tx) {
if (spi->rx && spi->rx_todo)
rx_fifo_read_full_duplex(spi);
@@ -645,10 +647,12 @@ static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
}
}
+ spin_unlock_irqrestore(&spi->lock, flags);
return IRQ_HANDLED;
completed:
queue_work(spi->wq, &spi->work);
+ spin_unlock_irqrestore(&spi->lock, flags);
return IRQ_HANDLED;
}
@@ -657,10 +661,12 @@ static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
{
struct lantiq_ssc_spi *spi = data;
u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
+ unsigned long flags;
if (!(stat & LTQ_SPI_STAT_ERRORS))
return IRQ_NONE;
+ spin_lock_irqsave(&spi->lock, flags);
if (stat & LTQ_SPI_STAT_RUE)
dev_err(spi->dev, "receive underflow error\n");
if (stat & LTQ_SPI_STAT_TUE)
@@ -681,6 +687,7 @@ static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
if (spi->master->cur_msg)
spi->master->cur_msg->status = -EIO;
queue_work(spi->wq, &spi->work);
+ spin_unlock_irqrestore(&spi->lock, flags);
return IRQ_HANDLED;
}
--
2.11.0
On newer chipsets, SPI controller has fifos of larger size.
So add the fifo size bit mask entry in SoC specific data structure.
Signed-off-by: Dilip Kota <[email protected]>
---
drivers/spi/spi-lantiq-ssc.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index cbe019f995999..a0d1f82d309f9 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -59,9 +59,7 @@
#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
-#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S)
#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
-#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S)
#define LTQ_SPI_ID_MOD_S 8 /* Module ID */
#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
@@ -124,19 +122,15 @@
LTQ_SPI_WHBSTATE_CLRTUE)
#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
-#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
-#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
#define LTQ_SPI_FSTAT_RXFFL_S 0
-#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
#define LTQ_SPI_FSTAT_TXFFL_S 8
-#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S)
#define LTQ_SPI_GPOCON_ISCSBN_S 8
#define LTQ_SPI_GPOCON_INVOUTN_S 0
@@ -162,6 +156,7 @@ struct lantiq_ssc_hwcfg {
unsigned int irncr;
unsigned int irnicr;
bool irq_ack;
+ u32 fifo_size_mask;
};
struct lantiq_ssc_spi {
@@ -211,16 +206,18 @@ static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
{
+ const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
- return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
+ return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask;
}
static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
{
+ const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
- return fstat & LTQ_SPI_FSTAT_RXFFL_M;
+ return (fstat >> LTQ_SPI_FSTAT_RXFFL_S) & hwcfg->fifo_size_mask;
}
static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
@@ -808,6 +805,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
.irnicr = 0xF8,
.irncr = 0xFC,
+ .fifo_size_mask = GENMASK(5, 0),
.irq_ack = false,
};
@@ -816,6 +814,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
.irnen_t = LTQ_SPI_IRNEN_T_XRX,
.irnicr = 0xF8,
.irncr = 0xFC,
+ .fifo_size_mask = GENMASK(5, 0),
.irq_ack = false,
};
@@ -941,8 +940,8 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
- spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
- spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
+ spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
+ spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
revision = id & LTQ_SPI_ID_REV_M;
--
2.11.0
Add support to SPI controller on Intel Atom based Lightning Mountain
SoC which reuses the Lantiq SPI controller IP.
Signed-off-by: Dilip Kota <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/spi/spi-lantiq-ssc.txt | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
index ce3230c8e28dc..76a3dd35f7960 100644
--- a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
+++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
@@ -1,11 +1,17 @@
Lantiq Synchronous Serial Controller (SSC) SPI master driver
Required properties:
-- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
+- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
+ "intel,lgm-spi"
- #address-cells: see spi-bus.txt
- #size-cells: see spi-bus.txt
- reg: address and length of the spi master registers
-- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
+- interrupts:
+ For compatible "intel,lgm-ssc" - the common interrupt number for
+ all of tx rx & err interrupts.
+ or
+ For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
+ "spi_err" interrupt.
Optional properties:
@@ -27,3 +33,14 @@ spi: spi@e100800 {
num-cs = <6>;
base-cs = <1>;
};
+
+ssc0: spi@e0800000 {
+ compatible = "intel,lgm-spi";
+ reg = <0xe0800000 0x400>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <35 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
+ clock-names = "freq", "gate";
+};
--
2.11.0
On Fri, 17 Jul 2020 14:27:50 +0800, Dilip Kota wrote:
> In full duplex mode, rx overflow error is observed. To overcome the error,
> wait until the complete data got received and proceed further.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/8] spi: lantiq: fix: Rx overflow error in full duplex mode
commit: 661ccf2b3f1360be50242726f7c26ced6a9e7d52
[2/8] spi: lantiq: Add SMP support
commit: ddf41bf782d2fb1df605407c7fff1160f488c949
[3/8] spi: lantiq: Move interrupt control register offesets to SoC specific data structure
commit: 8d19d665e0aca28c4bd8a024241b05f74841a315
[4/8] spi: lantiq: Add support to acknowledge interrupt
commit: 94eca904cb97f9cfa90e3e558fb73c49d2e42f91
[5/8] spi: lantiq: Add fifo size bit mask in SoC specific data structure
commit: 8743d2155aed9236202294e293ab13d33b3a7682
[6/8] spi: lantiq: Move interrupt configuration to SoC specific data structure
commit: 744cd0f212d72758fb094c1d13ec61b27ab6de3f
[7/8] spi: Add bindings for Lightning Mountain SoC
commit: 956284a304dd7d100730b85d90eac3f472b7d2a0
[8/8] spi: lantiq: Add support to Lightning Mountain SoC
commit: 040f7f9729785363eb062a36f76467c7b7c9b7c1
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark