Hi,
This patchset brings a series of improvements for the Actions Semi S500
SoCs family, by adding support for Clock & Reset Management Units, DMA,
MMC, I2C & SIRQ controllers.
Please note the patches consist mostly of DTS and bindings/compatibles
changes, since all the work they depend on has been already merged,
i.e. clock fixes/additions, pinctrl driver, sirq driver.
For the moment, I have only enabled the features I could test on
RoseapplePi SBC.
Thanks,
Cristi
Changes in v3:
- Squashed 'arm: dts: owl-s500-roseapplepi: Use UART clock from CMU' with
'arm: dts: owl-s500: Set CMU clocks for UARTs', according to Mani's review
- Rebased series on v5.11-rc1 and dropped the already merged patches:
* dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC
* dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema
* MAINTAINERS: Update entry for Actions Semi Owl I2C binding
* i2c: owl: Add compatible for the Actions Semi S500 I2C controller
Changes in v2:
- Added new bindings/compatibles for S500 DMA, MMC & I2C controllers
- Added support for the SIRQ controller
- Added new entries in MAINTAINERS
- Updated naming of some patches in v1
Cristian Ciocaltea (13):
arm: dts: owl-s500: Add Clock Management Unit
arm: dts: owl-s500: Set CMU clocks for UARTs
arm: dts: owl-s500: Add Reset controller
dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC
dmaengine: owl: Add compatible for the Actions Semi S500 DMA
controller
arm: dts: owl-s500: Add DMA controller
arm: dts: owl-s500: Add pinctrl & GPIO support
arm: dts: owl-s500: Add MMC support
arm: dts: owl-s500: Add I2C support
arm: dts: owl-s500: Add SIRQ controller
arm: dts: owl-s500-roseapplepi: Add uSD support
arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
MAINTAINERS: Add linux-actions ML for Actions Semi Arch
.../devicetree/bindings/dma/owl-dma.yaml | 7 +-
MAINTAINERS | 1 +
arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 -
.../arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 -
.../arm/boot/dts/owl-s500-labrador-base-m.dts | 7 -
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++-
arch/arm/boot/dts/owl-s500-sparky.dts | 7 -
arch/arm/boot/dts/owl-s500.dtsi | 140 ++++++++++++++++++
drivers/dma/owl-dma.c | 3 +-
9 files changed, 239 insertions(+), 37 deletions(-)
--
2.30.0
Add Clock Management Unit for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 1dbe4e8b38ac..5d5ad9db549b 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2016-2017 Andreas Färber
*/
+#include <dt-bindings/clock/actions,s500-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/owl-s500-powergate.h>
@@ -70,6 +71,12 @@ hosc: hosc {
#clock-cells = <0>;
};
+ losc: losc {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -169,6 +176,13 @@ uart6: serial@b012c000 {
status = "disabled";
};
+ cmu: clock-controller@b0160000 {
+ compatible = "actions,s500-cmu";
+ reg = <0xb0160000 0x8000>;
+ clocks = <&hosc>, <&losc>;
+ #clock-cells = <1>;
+ };
+
timer: timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x8000>;
--
2.30.0
Add a new compatible string corresponding to the DMA controller found
in the S500 variant of the Actions Semi Owl SoCs family. Additionally,
order the entries alphabetically.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes in v3:
- Added Reviewed-by tags from Mani and Rob
- Ordered the entries per Mani's suggestion
Documentation/devicetree/bindings/dma/owl-dma.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
index 256d62af2c64..93b4847554fb 100644
--- a/Documentation/devicetree/bindings/dma/owl-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
@@ -8,8 +8,8 @@ title: Actions Semi Owl SoCs DMA controller
description: |
The OWL DMA is a general-purpose direct memory access controller capable of
- supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
- respectively.
+ supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
+ independent DMA channels for the S500 and S900 SoC variants.
maintainers:
- Manivannan Sadhasivam <[email protected]>
@@ -20,8 +20,9 @@ allOf:
properties:
compatible:
enum:
- - actions,s900-dma
+ - actions,s500-dma
- actions,s700-dma
+ - actions,s900-dma
reg:
maxItems: 1
--
2.30.0
Add pinctrl node for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 449e9807c4ec..b16172615db0 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/actions,s500-cmu.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/owl-s500-powergate.h>
#include <dt-bindings/reset/actions,s500-reset.h>
@@ -208,6 +209,25 @@ sps: power-controller@b01b0100 {
#power-domain-cells = <1>;
};
+ pinctrl: pinctrl@b01b0000 {
+ compatible = "actions,s500-pinctrl";
+ reg = <0xb01b0000 0x40>, /* GPIO */
+ <0xb01b0040 0x10>, /* Multiplexing Control */
+ <0xb01b0060 0x18>, /* PAD Control */
+ <0xb01b0080 0xc>; /* PAD Drive Capacity */
+ clocks = <&cmu CLK_GPIO>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 132>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */
+ };
+
dma: dma-controller@b0260000 {
compatible = "actions,s500-dma";
reg = <0xb0260000 0xd00>;
--
2.30.0
Add reset controller property and bindings header for the
Actions Semi S500 SoC DTS.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index ac3d04c75dd5..a57ce7d6d745 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/actions,s500-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/owl-s500-powergate.h>
+#include <dt-bindings/reset/actions,s500-reset.h>
/ {
compatible = "actions,s500";
@@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 {
reg = <0xb0160000 0x8000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@b0168000 {
--
2.30.0
Set Clock Management Unit clocks for the UART nodes of Actions Semi
S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
- Removed the dummy 'uart2_clk' and 'uart3_clk' nodes from all owl-s500 DTS,
per Mani's review
arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 -------
arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 -------
arch/arm/boot/dts/owl-s500-labrador-base-m.dts | 7 -------
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 -------
arch/arm/boot/dts/owl-s500-sparky.dts | 7 -------
arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++
6 files changed, 7 insertions(+), 35 deletions(-)
diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts
index 7c96c59b610d..c2b02895910c 100644
--- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts
+++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts
@@ -25,12 +25,6 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
-
- uart3_clk: uart3-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};
&timer {
@@ -39,5 +33,4 @@ &timer {
&uart3 {
status = "okay";
- clocks = <&uart3_clk>;
};
diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
index e610d49395d2..7ae34a23e320 100644
--- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
+++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
@@ -18,15 +18,8 @@ aliases {
chosen {
stdout-path = "serial3:115200n8";
};
-
- uart3_clk: uart3-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};
&uart3 {
status = "okay";
- clocks = <&uart3_clk>;
};
diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
index c92f8bdcb331..1585e33f703b 100644
--- a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
+++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
@@ -21,15 +21,8 @@ aliases {
chosen {
stdout-path = "serial3:115200n8";
};
-
- uart3_clk: uart3-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};
&uart3 {
status = "okay";
- clocks = <&uart3_clk>;
};
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index a2087e617cb2..800edf5d2d12 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -25,12 +25,6 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
-
- uart2_clk: uart2-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};
&twd_timer {
@@ -43,5 +37,4 @@ &timer {
&uart2 {
status = "okay";
- clocks = <&uart2_clk>;
};
diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/owl-s500-sparky.dts
index c665ce8b88b4..9d8f7336bec0 100644
--- a/arch/arm/boot/dts/owl-s500-sparky.dts
+++ b/arch/arm/boot/dts/owl-s500-sparky.dts
@@ -25,12 +25,6 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>; /* 1 or 2 GiB */
};
-
- uart3_clk: uart3-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};
&timer {
@@ -39,5 +33,4 @@ &timer {
&uart3 {
status = "okay";
- clocks = <&uart3_clk>;
};
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 5d5ad9db549b..ac3d04c75dd5 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -131,6 +131,7 @@ uart0: serial@b0120000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0120000 0x2000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART0>;
status = "disabled";
};
@@ -138,6 +139,7 @@ uart1: serial@b0122000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0122000 0x2000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART1>;
status = "disabled";
};
@@ -145,6 +147,7 @@ uart2: serial@b0124000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0124000 0x2000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART2>;
status = "disabled";
};
@@ -152,6 +155,7 @@ uart3: serial@b0126000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0126000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART3>;
status = "disabled";
};
@@ -159,6 +163,7 @@ uart4: serial@b0128000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0128000 0x2000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART4>;
status = "disabled";
};
@@ -166,6 +171,7 @@ uart5: serial@b012a000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb012a000 0x2000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART5>;
status = "disabled";
};
@@ -173,6 +179,7 @@ uart6: serial@b012c000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb012c000 0x2000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART6>;
status = "disabled";
};
--
2.30.0
The DMA controller present on the Actions Semi S500 SoC is compatible
with the S900 variant, so add it to the list of devices supported by
the Actions Semi Owl DMA driver. Additionally, order the entries
alphabetically.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
- Ordered the entries to be consistent with the related dt-bindings
drivers/dma/owl-dma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
index 9fede32641e9..25cbd363e513 100644
--- a/drivers/dma/owl-dma.c
+++ b/drivers/dma/owl-dma.c
@@ -1080,8 +1080,9 @@ static struct dma_chan *owl_dma_of_xlate(struct of_phandle_args *dma_spec,
}
static const struct of_device_id owl_dma_match[] = {
- { .compatible = "actions,s900-dma", .data = (void *)S900_DMA,},
+ { .compatible = "actions,s500-dma", .data = (void *)S900_DMA,},
{ .compatible = "actions,s700-dma", .data = (void *)S700_DMA,},
+ { .compatible = "actions,s900-dma", .data = (void *)S900_DMA,},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, owl_dma_match);
--
2.30.0
Add the linux-actions mailing list for the Actions Semi architecture.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 546aa66428c9..74a6eaae7b31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1512,6 +1512,7 @@ ARM/ACTIONS SEMI ARCHITECTURE
M: Andreas Färber <[email protected]>
M: Manivannan Sadhasivam <[email protected]>
L: [email protected] (moderated for non-subscribers)
+L: [email protected] (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/actions.yaml
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
--
2.30.0
Add MMC controller nodes for Actions Semi S500 SoC, in order to
facilitate access to SD/EMMC/SDIO cards.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Ulf Hansson <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by tags from Ulf and Mani
arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index b16172615db0..7af7c9e1119d 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -241,5 +241,38 @@ dma: dma-controller@b0260000 {
clocks = <&cmu CLK_DMAC>;
power-domains = <&sps S500_PD_DMA>;
};
+
+ mmc0: mmc@b0230000 {
+ compatible = "actions,s500-mmc", "actions,owl-mmc";
+ reg = <0xb0230000 0x38>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD0>;
+ resets = <&cmu RESET_SD0>;
+ dmas = <&dma 2>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc1: mmc@b0234000 {
+ compatible = "actions,s500-mmc", "actions,owl-mmc";
+ reg = <0xb0234000 0x38>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD1>;
+ resets = <&cmu RESET_SD1>;
+ dmas = <&dma 3>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc2: mmc@b0238000 {
+ compatible = "actions,s500-mmc", "actions,owl-mmc";
+ reg = <0xb0238000 0x38>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD2>;
+ resets = <&cmu RESET_SD2>;
+ dmas = <&dma 4>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
};
};
--
2.30.0
Add SIRQ controller node for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 55f8b8c2e149..cd635f222d26 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -233,6 +233,16 @@ i2c3: i2c@b017c000 {
status = "disabled";
};
+ sirq: interrupt-controller@b01b0200 {
+ compatible = "actions,s500-sirq";
+ reg = <0xb01b0200 0x4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
+ };
+
timer: timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x8000>;
--
2.30.0
Add uSD support for RoseapplePi SBC using a fixed regulator as a
temporary solution until PMIC support becomes available.
Signed-off-by: Cristian Ciocaltea <[email protected]>
---
Changes in v3:
- None
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index 800edf5d2d12..fe9ae3619422 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -14,6 +14,7 @@ / {
model = "Roseapple Pi";
aliases {
+ mmc0 = &mmc0;
serial2 = &uart2;
};
@@ -25,6 +26,55 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
+
+ /* Fixed regulator used in the absence of PMIC */
+ sd_vcc: sd-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.1V";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
+};
+
+&pinctrl {
+ mmc0_pins: mmc0-pins {
+ pinmux {
+ groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
+ "sd0_cmd_mfp", "sd0_clk_mfp";
+ function = "sd0";
+ };
+
+ drv-pinconf {
+ groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
+ drive-strength = <8>;
+ };
+
+ bias0-pinconf {
+ pins = "sd0_d0", "sd0_d1", "sd0_d2",
+ "sd0_d3", "sd0_cmd";
+ bias-pull-up;
+ };
+
+ bias1-pinconf {
+ pins = "sd0_clk";
+ bias-pull-down;
+ };
+ };
+};
+
+/* uSD */
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ no-sdio;
+ no-mmc;
+ no-1-8-v;
+ cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <&sd_vcc>;
+ vqmmc-supply = <&sd_vcc>;
};
&twd_timer {
--
2.30.0
Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC.
For the moment enable only I2C0, which is used by the ATC2603C PMIC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index fe9ae3619422..ff91561ca99c 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -37,7 +37,51 @@ sd_vcc: sd-vcc {
};
};
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+};
+
&pinctrl {
+ i2c0_pins: i2c0-pins {
+ pinmux {
+ groups = "i2c0_mfp";
+ function = "i2c0";
+ };
+
+ pinconf {
+ pins = "i2c0_sclk", "i2c0_sdata";
+ bias-pull-up;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pinconf {
+ pins = "i2c1_sclk", "i2c1_sdata";
+ bias-pull-up;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pinconf {
+ pins = "i2c2_sclk", "i2c2_sdata";
+ bias-pull-up;
+ };
+ };
+
mmc0_pins: mmc0-pins {
pinmux {
groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
--
2.30.0
Add I2C controller nodes for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500.dtsi | 40 +++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 7af7c9e1119d..55f8b8c2e149 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -193,6 +193,46 @@ cmu: clock-controller@b0160000 {
#reset-cells = <1>;
};
+ i2c0: i2c@b0170000 {
+ compatible = "actions,s500-i2c";
+ reg = <0xb0170000 0x4000>;
+ clocks = <&cmu CLK_I2C0>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@b0174000 {
+ compatible = "actions,s500-i2c";
+ reg = <0xb0174000 0x4000>;
+ clocks = <&cmu CLK_I2C1>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@b0178000 {
+ compatible = "actions,s500-i2c";
+ reg = <0xb0178000 0x4000>;
+ clocks = <&cmu CLK_I2C2>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@b017c000 {
+ compatible = "actions,s500-i2c";
+ reg = <0xb017c000 0x4000>;
+ clocks = <&cmu CLK_I2C3>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
timer: timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x8000>;
--
2.30.0
Add DMA controller node for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Reviewed-by from Mani
arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index a57ce7d6d745..449e9807c4ec 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -207,5 +207,19 @@ sps: power-controller@b01b0100 {
reg = <0xb01b0100 0x100>;
#power-domain-cells = <1>;
};
+
+ dma: dma-controller@b0260000 {
+ compatible = "actions,s500-dma";
+ reg = <0xb0260000 0xd00>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <12>;
+ dma-requests = <46>;
+ clocks = <&cmu CLK_DMAC>;
+ power-domains = <&sps S500_PD_DMA>;
+ };
};
};
--
2.30.0
On Tue, Dec 29, 2020 at 11:17:26PM +0200, Cristian Ciocaltea wrote:
> Add uSD support for RoseapplePi SBC using a fixed regulator as a
> temporary solution until PMIC support becomes available.
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> Changes in v3:
> - None
>
> arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index 800edf5d2d12..fe9ae3619422 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -14,6 +14,7 @@ / {
> model = "Roseapple Pi";
>
> aliases {
> + mmc0 = &mmc0;
> serial2 = &uart2;
> };
>
> @@ -25,6 +26,55 @@ memory@0 {
> device_type = "memory";
> reg = <0x0 0x80000000>; /* 2GB */
> };
> +
> + /* Fixed regulator used in the absence of PMIC */
> + sd_vcc: sd-vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.1V";
> + regulator-min-microvolt = <3100000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-always-on;
> + };
> +};
> +
> +&pinctrl {
> + mmc0_pins: mmc0-pins {
> + pinmux {
> + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> + "sd0_cmd_mfp", "sd0_clk_mfp";
> + function = "sd0";
> + };
> +
> + drv-pinconf {
> + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
> + drive-strength = <8>;
> + };
> +
> + bias0-pinconf {
> + pins = "sd0_d0", "sd0_d1", "sd0_d2",
> + "sd0_d3", "sd0_cmd";
> + bias-pull-up;
> + };
> +
> + bias1-pinconf {
> + pins = "sd0_clk";
> + bias-pull-down;
> + };
> + };
> +};
> +
> +/* uSD */
> +&mmc0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + no-sdio;
> + no-mmc;
> + no-1-8-v;
> + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + vmmc-supply = <&sd_vcc>;
> + vqmmc-supply = <&sd_vcc>;
> };
>
> &twd_timer {
> --
> 2.30.0
>
On Tue, Dec 29, 2020 at 11:17:15PM +0200, Cristian Ciocaltea wrote:
> Hi,
>
> This patchset brings a series of improvements for the Actions Semi S500
> SoCs family, by adding support for Clock & Reset Management Units, DMA,
> MMC, I2C & SIRQ controllers.
>
> Please note the patches consist mostly of DTS and bindings/compatibles
> changes, since all the work they depend on has been already merged,
> i.e. clock fixes/additions, pinctrl driver, sirq driver.
>
> For the moment, I have only enabled the features I could test on
> RoseapplePi SBC.
>
Applied all patches except the 2 dmaengine patches for v5.12. Andreas, please
let me know if you want to do the PR this time. Else I'll proceed.
Thanks,
Mani
> Thanks,
> Cristi
>
> Changes in v3:
> - Squashed 'arm: dts: owl-s500-roseapplepi: Use UART clock from CMU' with
> 'arm: dts: owl-s500: Set CMU clocks for UARTs', according to Mani's review
> - Rebased series on v5.11-rc1 and dropped the already merged patches:
> * dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC
> * dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema
> * MAINTAINERS: Update entry for Actions Semi Owl I2C binding
> * i2c: owl: Add compatible for the Actions Semi S500 I2C controller
>
> Changes in v2:
> - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers
> - Added support for the SIRQ controller
> - Added new entries in MAINTAINERS
> - Updated naming of some patches in v1
>
> Cristian Ciocaltea (13):
> arm: dts: owl-s500: Add Clock Management Unit
> arm: dts: owl-s500: Set CMU clocks for UARTs
> arm: dts: owl-s500: Add Reset controller
> dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC
> dmaengine: owl: Add compatible for the Actions Semi S500 DMA
> controller
> arm: dts: owl-s500: Add DMA controller
> arm: dts: owl-s500: Add pinctrl & GPIO support
> arm: dts: owl-s500: Add MMC support
> arm: dts: owl-s500: Add I2C support
> arm: dts: owl-s500: Add SIRQ controller
> arm: dts: owl-s500-roseapplepi: Add uSD support
> arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
> MAINTAINERS: Add linux-actions ML for Actions Semi Arch
>
> .../devicetree/bindings/dma/owl-dma.yaml | 7 +-
> MAINTAINERS | 1 +
> arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 -
> .../arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 -
> .../arm/boot/dts/owl-s500-labrador-base-m.dts | 7 -
> arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++-
> arch/arm/boot/dts/owl-s500-sparky.dts | 7 -
> arch/arm/boot/dts/owl-s500.dtsi | 140 ++++++++++++++++++
> drivers/dma/owl-dma.c | 3 +-
> 9 files changed, 239 insertions(+), 37 deletions(-)
>
> --
> 2.30.0
>
On Thu, Dec 31, 2020 at 12:57:10PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Dec 29, 2020 at 11:17:26PM +0200, Cristian Ciocaltea wrote:
> > Add uSD support for RoseapplePi SBC using a fixed regulator as a
> > temporary solution until PMIC support becomes available.
> >
> > Signed-off-by: Cristian Ciocaltea <[email protected]>
>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thank you, Mani!
> Thanks,
> Mani
>
> > ---
> > Changes in v3:
> > - None
> >
> > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++
> > 1 file changed, 50 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > index 800edf5d2d12..fe9ae3619422 100644
> > --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> > @@ -14,6 +14,7 @@ / {
> > model = "Roseapple Pi";
> >
> > aliases {
> > + mmc0 = &mmc0;
> > serial2 = &uart2;
> > };
> >
> > @@ -25,6 +26,55 @@ memory@0 {
> > device_type = "memory";
> > reg = <0x0 0x80000000>; /* 2GB */
> > };
> > +
> > + /* Fixed regulator used in the absence of PMIC */
> > + sd_vcc: sd-vcc {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fixed-3.1V";
> > + regulator-min-microvolt = <3100000>;
> > + regulator-max-microvolt = <3100000>;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&pinctrl {
> > + mmc0_pins: mmc0-pins {
> > + pinmux {
> > + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> > + "sd0_cmd_mfp", "sd0_clk_mfp";
> > + function = "sd0";
> > + };
> > +
> > + drv-pinconf {
> > + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
> > + drive-strength = <8>;
> > + };
> > +
> > + bias0-pinconf {
> > + pins = "sd0_d0", "sd0_d1", "sd0_d2",
> > + "sd0_d3", "sd0_cmd";
> > + bias-pull-up;
> > + };
> > +
> > + bias1-pinconf {
> > + pins = "sd0_clk";
> > + bias-pull-down;
> > + };
> > + };
> > +};
> > +
> > +/* uSD */
> > +&mmc0 {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc0_pins>;
> > + no-sdio;
> > + no-mmc;
> > + no-1-8-v;
> > + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>;
> > + bus-width = <4>;
> > + vmmc-supply = <&sd_vcc>;
> > + vqmmc-supply = <&sd_vcc>;
> > };
> >
> > &twd_timer {
> > --
> > 2.30.0
> >
On Thu, Dec 31, 2020 at 01:24:35PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Dec 29, 2020 at 11:17:15PM +0200, Cristian Ciocaltea wrote:
> > Hi,
> >
> > This patchset brings a series of improvements for the Actions Semi S500
> > SoCs family, by adding support for Clock & Reset Management Units, DMA,
> > MMC, I2C & SIRQ controllers.
> >
> > Please note the patches consist mostly of DTS and bindings/compatibles
> > changes, since all the work they depend on has been already merged,
> > i.e. clock fixes/additions, pinctrl driver, sirq driver.
> >
> > For the moment, I have only enabled the features I could test on
> > RoseapplePi SBC.
> >
>
> Applied all patches except the 2 dmaengine patches for v5.12. Andreas, please
> let me know if you want to do the PR this time. Else I'll proceed.
Thank you, Mani!
The dmaengine patches should be picked up by Vinod, right?
> Thanks,
> Mani
>
> > Thanks,
> > Cristi
> >
> > Changes in v3:
> > - Squashed 'arm: dts: owl-s500-roseapplepi: Use UART clock from CMU' with
> > 'arm: dts: owl-s500: Set CMU clocks for UARTs', according to Mani's review
> > - Rebased series on v5.11-rc1 and dropped the already merged patches:
> > * dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC
> > * dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema
> > * MAINTAINERS: Update entry for Actions Semi Owl I2C binding
> > * i2c: owl: Add compatible for the Actions Semi S500 I2C controller
> >
> > Changes in v2:
> > - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers
> > - Added support for the SIRQ controller
> > - Added new entries in MAINTAINERS
> > - Updated naming of some patches in v1
> >
> > Cristian Ciocaltea (13):
> > arm: dts: owl-s500: Add Clock Management Unit
> > arm: dts: owl-s500: Set CMU clocks for UARTs
> > arm: dts: owl-s500: Add Reset controller
> > dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC
> > dmaengine: owl: Add compatible for the Actions Semi S500 DMA
> > controller
> > arm: dts: owl-s500: Add DMA controller
> > arm: dts: owl-s500: Add pinctrl & GPIO support
> > arm: dts: owl-s500: Add MMC support
> > arm: dts: owl-s500: Add I2C support
> > arm: dts: owl-s500: Add SIRQ controller
> > arm: dts: owl-s500-roseapplepi: Add uSD support
> > arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
> > MAINTAINERS: Add linux-actions ML for Actions Semi Arch
> >
> > .../devicetree/bindings/dma/owl-dma.yaml | 7 +-
> > MAINTAINERS | 1 +
> > arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 -
> > .../arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 -
> > .../arm/boot/dts/owl-s500-labrador-base-m.dts | 7 -
> > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++-
> > arch/arm/boot/dts/owl-s500-sparky.dts | 7 -
> > arch/arm/boot/dts/owl-s500.dtsi | 140 ++++++++++++++++++
> > drivers/dma/owl-dma.c | 3 +-
> > 9 files changed, 239 insertions(+), 37 deletions(-)
> >
> > --
> > 2.30.0
> >
On 31 December 2020 2:42:02 PM IST, Cristian Ciocaltea <[email protected]> wrote:
>On Thu, Dec 31, 2020 at 01:24:35PM +0530, Manivannan Sadhasivam wrote:
>> On Tue, Dec 29, 2020 at 11:17:15PM +0200, Cristian Ciocaltea wrote:
>> > Hi,
>> >
>> > This patchset brings a series of improvements for the Actions Semi
>S500
>> > SoCs family, by adding support for Clock & Reset Management Units,
>DMA,
>> > MMC, I2C & SIRQ controllers.
>> >
>> > Please note the patches consist mostly of DTS and
>bindings/compatibles
>> > changes, since all the work they depend on has been already merged,
>> > i.e. clock fixes/additions, pinctrl driver, sirq driver.
>> >
>> > For the moment, I have only enabled the features I could test on
>> > RoseapplePi SBC.
>> >
>>
>> Applied all patches except the 2 dmaengine patches for v5.12.
>Andreas, please
>> let me know if you want to do the PR this time. Else I'll proceed.
>
>Thank you, Mani!
>The dmaengine patches should be picked up by Vinod, right?
>
Yes! Vinod is just back from vacation, so he will :)
Thanks,
Mani
>> Thanks,
>> Mani
>>
>> > Thanks,
>> > Cristi
>> >
>> > Changes in v3:
>> > - Squashed 'arm: dts: owl-s500-roseapplepi: Use UART clock from
>CMU' with
>> > 'arm: dts: owl-s500: Set CMU clocks for UARTs', according to
>Mani's review
>> > - Rebased series on v5.11-rc1 and dropped the already merged
>patches:
>> > * dt-bindings: mmc: owl: Add compatible string for Actions Semi
>S500 SoC
>> > * dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a
>schema
>> > * MAINTAINERS: Update entry for Actions Semi Owl I2C binding
>> > * i2c: owl: Add compatible for the Actions Semi S500 I2C
>controller
>> >
>> > Changes in v2:
>> > - Added new bindings/compatibles for S500 DMA, MMC & I2C
>controllers
>> > - Added support for the SIRQ controller
>> > - Added new entries in MAINTAINERS
>> > - Updated naming of some patches in v1
>> >
>> > Cristian Ciocaltea (13):
>> > arm: dts: owl-s500: Add Clock Management Unit
>> > arm: dts: owl-s500: Set CMU clocks for UARTs
>> > arm: dts: owl-s500: Add Reset controller
>> > dt-bindings: dma: owl: Add compatible string for Actions Semi
>S500 SoC
>> > dmaengine: owl: Add compatible for the Actions Semi S500 DMA
>> > controller
>> > arm: dts: owl-s500: Add DMA controller
>> > arm: dts: owl-s500: Add pinctrl & GPIO support
>> > arm: dts: owl-s500: Add MMC support
>> > arm: dts: owl-s500: Add I2C support
>> > arm: dts: owl-s500: Add SIRQ controller
>> > arm: dts: owl-s500-roseapplepi: Add uSD support
>> > arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration
>> > MAINTAINERS: Add linux-actions ML for Actions Semi Arch
>> >
>> > .../devicetree/bindings/dma/owl-dma.yaml | 7 +-
>> > MAINTAINERS | 1 +
>> > arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 -
>> > .../arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 -
>> > .../arm/boot/dts/owl-s500-labrador-base-m.dts | 7 -
>> > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++-
>> > arch/arm/boot/dts/owl-s500-sparky.dts | 7 -
>> > arch/arm/boot/dts/owl-s500.dtsi | 140
>++++++++++++++++++
>> > drivers/dma/owl-dma.c | 3 +-
>> > 9 files changed, 239 insertions(+), 37 deletions(-)
>> >
>> > --
>> > 2.30.0
>> >
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
On 29-12-20, 23:17, Cristian Ciocaltea wrote:
> Add a new compatible string corresponding to the DMA controller found
> in the S500 variant of the Actions Semi Owl SoCs family. Additionally,
> order the entries alphabetically.
Applied, thanks
--
~Vinod
On 29-12-20, 23:17, Cristian Ciocaltea wrote:
> The DMA controller present on the Actions Semi S500 SoC is compatible
> with the S900 variant, so add it to the list of devices supported by
> the Actions Semi Owl DMA driver. Additionally, order the entries
> alphabetically.
Applied, thanks
--
~Vinod
On Sat, Jan 09, 2021 at 12:38:13AM -0300, Matheus Castello wrote:
>
>
> Em 12/29/2020 6:17 PM, Cristian Ciocaltea escreveu:
> > Add Clock Management Unit for Actions Semi S500 SoC.
> >
> > Signed-off-by: Cristian Ciocaltea <[email protected]>
> > Reviewed-by: Manivannan Sadhasivam <[email protected]>
[...]
> Tested-by: Matheus Castello <[email protected]>
Thanks for testing this patch series!
Regards,
Cristi