LinuxLists.cc - [PATCH v3] irqchip: gic-v3: Extend collection table

2023-06-21 10:52:40

Subject: [PATCH v3] irqchip: gic-v3: Extend collection table

Only single level table is supported to the collection table, and only
one page is allocated.

Extend collection table to support more CPUs:
1. Recalculate the page number of collection table based on the number
of CPUs.
2. Add 2 level tables to collection table when HCC field is zero.
3. Add GITS_TYPER_CIDBITS macros.

It is noticed in an internal simulation research:
- the page_size of collection table is 4 KB
- the entry_size of collection table is 16 Byte
- with 512 CPUs

And I don't find a have a GIC500 platform to test this path.

Cc: Thomas Gleixner <[email protected]>
Cc: Marc Zyngier <[email protected]>
Signed-off-by: wangwudi <[email protected]>
---

ChangeLog:
v1-->v2:
1. Support 2 level table.
2. Rewrite the commit log.
v2-->v3
1. Fixed the error when HCC is field is not zero.
2. Modifiy the commit log.

drivers/irqchip/irq-gic-v3-its.c | 67 +++++++++++++++++++++++++++++++-------
include/linux/irqchip/arm-gic-v3.h | 3 ++
2 files changed, 58 insertions(+), 12 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 0ec2b1e1df75..c37e010fd50c 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -126,6 +126,7 @@ struct its_node {
#define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
#define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
#define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
+#define collection_ids(its) (FIELD_GET(GITS_TYPER_CIDBITS, (its)->typer) + 1)

#define ITS_ITT_ALIGN SZ_256

@@ -2626,6 +2627,10 @@ static int its_alloc_tables(struct its_node *its)
indirect = its_parse_indirect_baser(its, baser, &order,
ITS_MAX_VPEID_BITS);
break;
+ case GITS_BASER_TYPE_COLLECTION:
+ indirect = its_parse_indirect_baser(its, baser, &order,
+ order_base_2(num_possible_cpus()));
+ break;
}

err = its_setup_baser(its, baser, cache, shr, order, indirect);
@@ -3230,18 +3235,6 @@ static void its_cpu_init_collection(struct its_node *its)
its_send_invall(its, &its->collections[cpu]);
}

-static void its_cpu_init_collections(void)
-{
- struct its_node *its;
-
- raw_spin_lock(&its_lock);
-
- list_for_each_entry(its, &its_nodes, entry)
- its_cpu_init_collection(its);
-
- raw_spin_unlock(&its_lock);
-}
-
static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
{
struct its_device *its_dev = NULL, *tmp;
@@ -3316,6 +3309,56 @@ static bool its_alloc_table_entry(struct its_node *its,
return true;
}

+static bool its_alloc_collection_table(struct its_node *its, struct its_baser *baser)
+{
+ int cpu = smp_processor_id();
+ int cpu_ids = 16;
+
+ if (its->typer & GITS_TYPER_CIL)
+ cpu_ids = collection_ids(its);
+
+ if (!(ilog2(cpu) < cpu_ids)) {
+ pr_warn("ITS: CPU%d out of Collection ID range for %dbits", cpu, cpu_ids);
+ return false;
+ }
+
+ if (!its_alloc_table_entry(its, baser, cpu)) {
+ pr_warn("ITS: CPU%d failed to allocate collection l2 table", cpu);
+ return false;
+ }
+
+ return true;
+}
+
+static bool its_cpu_init_collections(void)
+{
+ struct its_node *its;
+ struct its_baser *baser;
+ void __iomem *base;
+
+ raw_spin_lock(&its_lock);
+
+ list_for_each_entry(its, &its_nodes, entry) {
+ base = its->base;
+ if (!GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) {
+ baser = its_get_baser(its, GITS_BASER_TYPE_COLLECTION);
+ if (!baser) {
+ raw_spin_unlock(&its_lock);
+ return false;
+ }
+
+ if (!its_alloc_collection_table(its, baser)) {
+ raw_spin_unlock(&its_lock);
+ return false;
+ }
+ }
+
+ its_cpu_init_collection(its);
+ }
+ raw_spin_unlock(&its_lock);
+ return true;
+}
+
static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
{
struct its_baser *baser;
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 728691365464..35e83da8961f 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -400,6 +400,9 @@
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HCC_SHIFT 24
#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
+#define GITS_TYPER_CIDBITS_SHIFT 32
+#define GITS_TYPER_CIDBITS GENMASK_ULL(35, 32)
+#define GITS_TYPER_CIL (1ULL << 36)
#define GITS_TYPER_VMOVP (1ULL << 37)
#define GITS_TYPER_VMAPP (1ULL << 40)
#define GITS_TYPER_SVPET GENMASK_ULL(42, 41)
--
2.7.4

2023-07-07 09:42:06

by wangwudi

[permalink] [raw]

Subject: Re: [PATCH v3] irqchip: gic-v3: Extend collection table

Hi Marc,

A gentle ping.

Thanks,
Wudi

在 2023/7/7 17:04, wangwudi 写道:
>
>
> -----邮件原件-----
> 发件人: wangwudi
> 发送时间: 2023年6月21日 18:02
> 收件人: [email protected]
> 抄送: liaochang (A) <[email protected]>; wangwudi <[email protected]>; Thomas Gleixner <[email protected]>; Marc Zyngier <[email protected]>
> 主题: [PATCH v3] irqchip: gic-v3: Extend collection table
>
> Only single level table is supported to the collection table, and only one page is allocated.
>
> Extend collection table to support more CPUs:
> 1. Recalculate the page number of collection table based on the number of CPUs.
> 2. Add 2 level tables to collection table when HCC field is zero.
> 3. Add GITS_TYPER_CIDBITS macros.
>
> It is noticed in an internal simulation research:
> - the page_size of collection table is 4 KB
> - the entry_size of collection table is 16 Byte
> - with 512 CPUs
>
> And I don't find a have a GIC500 platform to test this path.
>
> Cc: Thomas Gleixner <[email protected]>
> Cc: Marc Zyngier <[email protected]>
> Signed-off-by: wangwudi <[email protected]>
> ---
>
> ChangeLog:
> v1-->v2:
> 1. Support 2 level table.
> 2. Rewrite the commit log.
> v2-->v3
> 1. Fixed the error when HCC is field is not zero.
> 2. Modifiy the commit log.
>
> drivers/irqchip/irq-gic-v3-its.c | 67 +++++++++++++++++++++++++++++++-------
> include/linux/irqchip/arm-gic-v3.h | 3 ++
> 2 files changed, 58 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 0ec2b1e1df75..c37e010fd50c 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -126,6 +126,7 @@ struct its_node {
> #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
> #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
> #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
> +#define collection_ids(its) (FIELD_GET(GITS_TYPER_CIDBITS, (its)->typer) + 1)
>
> #define ITS_ITT_ALIGN SZ_256
>
> @@ -2626,6 +2627,10 @@ static int its_alloc_tables(struct its_node *its)
> indirect = its_parse_indirect_baser(its, baser, &order,
> ITS_MAX_VPEID_BITS);
> break;
> + case GITS_BASER_TYPE_COLLECTION:
> + indirect = its_parse_indirect_baser(its, baser, &order,
> + order_base_2(num_possible_cpus()));
> + break;
> }
>
> err = its_setup_baser(its, baser, cache, shr, order, indirect); @@ -3230,18 +3235,6 @@ static void its_cpu_init_collection(struct its_node *its)
> its_send_invall(its, &its->collections[cpu]); }
>
> -static void its_cpu_init_collections(void) -{
> - struct its_node *its;
> -
> - raw_spin_lock(&its_lock);
> -
> - list_for_each_entry(its, &its_nodes, entry)
> - its_cpu_init_collection(its);
> -
> - raw_spin_unlock(&its_lock);
> -}
> -
> static struct its_device *its_find_device(struct its_node *its, u32 dev_id) {
> struct its_device *its_dev = NULL, *tmp; @@ -3316,6 +3309,56 @@ static bool its_alloc_table_entry(struct its_node *its,
> return true;
> }
>
> +static bool its_alloc_collection_table(struct its_node *its, struct
> +its_baser *baser) {
> + int cpu = smp_processor_id();
> + int cpu_ids = 16;
> +
> + if (its->typer & GITS_TYPER_CIL)
> + cpu_ids = collection_ids(its);
> +
> + if (!(ilog2(cpu) < cpu_ids)) {
> + pr_warn("ITS: CPU%d out of Collection ID range for %dbits", cpu, cpu_ids);
> + return false;
> + }
> +
> + if (!its_alloc_table_entry(its, baser, cpu)) {
> + pr_warn("ITS: CPU%d failed to allocate collection l2 table", cpu);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool its_cpu_init_collections(void) {
> + struct its_node *its;
> + struct its_baser *baser;
> + void __iomem *base;
> +
> + raw_spin_lock(&its_lock);
> +
> + list_for_each_entry(its, &its_nodes, entry) {
> + base = its->base;
> + if (!GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) {
> + baser = its_get_baser(its, GITS_BASER_TYPE_COLLECTION);
> + if (!baser) {
> + raw_spin_unlock(&its_lock);
> + return false;
> + }
> +
> + if (!its_alloc_collection_table(its, baser)) {
> + raw_spin_unlock(&its_lock);
> + return false;
> + }
> + }
> +
> + its_cpu_init_collection(its);
> + }
> + raw_spin_unlock(&its_lock);
> + return true;
> +}
> +
> static bool its_alloc_device_table(struct its_node *its, u32 dev_id) {
> struct its_baser *baser;
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 728691365464..35e83da8961f 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -400,6 +400,9 @@
> #define GITS_TYPER_PTA (1UL << 19)
> #define GITS_TYPER_HCC_SHIFT 24
> #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
> +#define GITS_TYPER_CIDBITS_SHIFT 32
> +#define GITS_TYPER_CIDBITS GENMASK_ULL(35, 32)
> +#define GITS_TYPER_CIL (1ULL << 36)
> #define GITS_TYPER_VMOVP (1ULL << 37)
> #define GITS_TYPER_VMAPP (1ULL << 40)
> #define GITS_TYPER_SVPET GENMASK_ULL(42, 41)
> --
> 2.7.4
>

2023-07-14 10:48:13

by wangwudi

[permalink] [raw]

Subject: Re: [PATCH v3] irqchip: gic-v3: Extend collection table

Hi Marc,

A gentle ping.

Thanks,
Wudi

在 2023/7/14 17:57, wangwudi 写道:
>
>
> -----邮件原件-----
> 发件人: wangwudi
> 发送时间: 2023年6月21日 18:02
> 收件人: [email protected]
> 抄送: liaochang (A) <[email protected]>; wangwudi <[email protected]>; Thomas Gleixner <[email protected]>; Marc Zyngier <[email protected]>
> 主题: [PATCH v3] irqchip: gic-v3: Extend collection table
>
> Only single level table is supported to the collection table, and only one page is allocated.
>
> Extend collection table to support more CPUs:
> 1. Recalculate the page number of collection table based on the number of CPUs.
> 2. Add 2 level tables to collection table when HCC field is zero.
> 3. Add GITS_TYPER_CIDBITS macros.
>
> It is noticed in an internal simulation research:
> - the page_size of collection table is 4 KB
> - the entry_size of collection table is 16 Byte
> - with 512 CPUs
>
> And I don't find a have a GIC500 platform to test this path.
>
> Cc: Thomas Gleixner <[email protected]>
> Cc: Marc Zyngier <[email protected]>
> Signed-off-by: wangwudi <[email protected]>
> ---
>
> ChangeLog:
> v1-->v2:
> 1. Support 2 level table.
> 2. Rewrite the commit log.
> v2-->v3
> 1. Fixed the error when HCC is field is not zero.
> 2. Modifiy the commit log.
>
> drivers/irqchip/irq-gic-v3-its.c | 67 +++++++++++++++++++++++++++++++-------
> include/linux/irqchip/arm-gic-v3.h | 3 ++
> 2 files changed, 58 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 0ec2b1e1df75..c37e010fd50c 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -126,6 +126,7 @@ struct its_node {
> #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
> #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
> #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
> +#define collection_ids(its) (FIELD_GET(GITS_TYPER_CIDBITS, (its)->typer) + 1)
>
> #define ITS_ITT_ALIGN SZ_256
>
> @@ -2626,6 +2627,10 @@ static int its_alloc_tables(struct its_node *its)
> indirect = its_parse_indirect_baser(its, baser, &order,
> ITS_MAX_VPEID_BITS);
> break;
> + case GITS_BASER_TYPE_COLLECTION:
> + indirect = its_parse_indirect_baser(its, baser, &order,
> + order_base_2(num_possible_cpus()));
> + break;
> }
>
> err = its_setup_baser(its, baser, cache, shr, order, indirect); @@ -3230,18 +3235,6 @@ static void its_cpu_init_collection(struct its_node *its)
> its_send_invall(its, &its->collections[cpu]); }
>
> -static void its_cpu_init_collections(void) -{
> - struct its_node *its;
> -
> - raw_spin_lock(&its_lock);
> -
> - list_for_each_entry(its, &its_nodes, entry)
> - its_cpu_init_collection(its);
> -
> - raw_spin_unlock(&its_lock);
> -}
> -
> static struct its_device *its_find_device(struct its_node *its, u32 dev_id) {
> struct its_device *its_dev = NULL, *tmp; @@ -3316,6 +3309,56 @@ static bool its_alloc_table_entry(struct its_node *its,
> return true;
> }
>
> +static bool its_alloc_collection_table(struct its_node *its, struct
> +its_baser *baser) {
> + int cpu = smp_processor_id();
> + int cpu_ids = 16;
> +
> + if (its->typer & GITS_TYPER_CIL)
> + cpu_ids = collection_ids(its);
> +
> + if (!(ilog2(cpu) < cpu_ids)) {
> + pr_warn("ITS: CPU%d out of Collection ID range for %dbits", cpu, cpu_ids);
> + return false;
> + }
> +
> + if (!its_alloc_table_entry(its, baser, cpu)) {
> + pr_warn("ITS: CPU%d failed to allocate collection l2 table", cpu);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool its_cpu_init_collections(void) {
> + struct its_node *its;
> + struct its_baser *baser;
> + void __iomem *base;
> +
> + raw_spin_lock(&its_lock);
> +
> + list_for_each_entry(its, &its_nodes, entry) {
> + base = its->base;
> + if (!GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) {
> + baser = its_get_baser(its, GITS_BASER_TYPE_COLLECTION);
> + if (!baser) {
> + raw_spin_unlock(&its_lock);
> + return false;
> + }
> +
> + if (!its_alloc_collection_table(its, baser)) {
> + raw_spin_unlock(&its_lock);
> + return false;
> + }
> + }
> +
> + its_cpu_init_collection(its);
> + }
> + raw_spin_unlock(&its_lock);
> + return true;
> +}
> +
> static bool its_alloc_device_table(struct its_node *its, u32 dev_id) {
> struct its_baser *baser;
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 728691365464..35e83da8961f 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -400,6 +400,9 @@
> #define GITS_TYPER_PTA (1UL << 19)
> #define GITS_TYPER_HCC_SHIFT 24
> #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
> +#define GITS_TYPER_CIDBITS_SHIFT 32
> +#define GITS_TYPER_CIDBITS GENMASK_ULL(35, 32)
> +#define GITS_TYPER_CIL (1ULL << 36)
> #define GITS_TYPER_VMOVP (1ULL << 37)
> #define GITS_TYPER_VMAPP (1ULL << 40)
> #define GITS_TYPER_SVPET GENMASK_ULL(42, 41)
> --
> 2.7.4
>

2023-07-29 07:43:42

by wangwudi

[permalink] [raw]

Subject: [PATCH v3] irqchip: gic-v3: Extend collection table

2023-07-29 11:48:17

by Marc Zyngier

[permalink] [raw]

Subject: Re: [PATCH v3] irqchip: gic-v3: Extend collection table

On 2023-07-29 07:54, wangwudi wrote:
> Hi Marc,
>
> A gentle ping.

Look, you keep pinging me for a patch that you haven't tested.

What do you think happens? This patch goes to the back of the queue
until I find enough time to test it on a GIC500 platform.

It is even of a lower priority given that this doesn't fix any
*real* issue, and is only for the purpose of your simulation with
non-sensical parameters (16 bytes for collection entries? let's
get real -- this only needs to be at most an affinity, for which
4 bytes are enough).

M.

>
> Thanks,
> Wudi
>
>
> 在 2023/7/7 17:04, wangwudi 写道:
>>
>>
>> -----邮件原件-----
>> 发件人: wangwudi
>> 发送时间: 2023年6月21日 18:02
>> 收件人: [email protected]
>> 抄送: liaochang (A) <[email protected]>; wangwudi
>> <[email protected]>; Thomas Gleixner <[email protected]>; Marc
>> Zyngier <[email protected]>
>> 主题: [PATCH v3] irqchip: gic-v3: Extend collection table
>>
>> Only single level table is supported to the collection table, and only
>> one page is allocated.
>>
>> Extend collection table to support more CPUs:
>> 1. Recalculate the page number of collection table based on the number
>> of CPUs.
>> 2. Add 2 level tables to collection table when HCC field is zero.
>> 3. Add GITS_TYPER_CIDBITS macros.
>>
>> It is noticed in an internal simulation research:
>> - the page_size of collection table is 4 KB
>> - the entry_size of collection table is 16 Byte
>> - with 512 CPUs
>>
>> And I don't find a have a GIC500 platform to test this path.
>>
>> Cc: Thomas Gleixner <[email protected]>
>> Cc: Marc Zyngier <[email protected]>
>> Signed-off-by: wangwudi <[email protected]>
>> ---
>>
>> ChangeLog:
>> v1-->v2:
>> 1. Support 2 level table.
>> 2. Rewrite the commit log.
>> v2-->v3
>> 1. Fixed the error when HCC is field is not zero.
>> 2. Modifiy the commit log.
>>
>> drivers/irqchip/irq-gic-v3-its.c | 67
>> +++++++++++++++++++++++++++++++-------
>> include/linux/irqchip/arm-gic-v3.h | 3 ++
>> 2 files changed, 58 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c
>> b/drivers/irqchip/irq-gic-v3-its.c
>> index 0ec2b1e1df75..c37e010fd50c 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -126,6 +126,7 @@ struct its_node {
>> #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
>> #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
>> #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer)
>> + 1)
>> +#define collection_ids(its) (FIELD_GET(GITS_TYPER_CIDBITS,
>> (its)->typer) + 1)
>>
>> #define ITS_ITT_ALIGN SZ_256
>>
>> @@ -2626,6 +2627,10 @@ static int its_alloc_tables(struct its_node
>> *its)
>> indirect = its_parse_indirect_baser(its, baser, &order,
>> ITS_MAX_VPEID_BITS);
>> break;
>> + case GITS_BASER_TYPE_COLLECTION:
>> + indirect = its_parse_indirect_baser(its, baser, &order,
>> + order_base_2(num_possible_cpus()));
>> + break;
>> }
>>
>> err = its_setup_baser(its, baser, cache, shr, order, indirect); @@
>> -3230,18 +3235,6 @@ static void its_cpu_init_collection(struct
>> its_node *its)
>> its_send_invall(its, &its->collections[cpu]); }
>>
>> -static void its_cpu_init_collections(void) -{
>> - struct its_node *its;
>> -
>> - raw_spin_lock(&its_lock);
>> -
>> - list_for_each_entry(its, &its_nodes, entry)
>> - its_cpu_init_collection(its);
>> -
>> - raw_spin_unlock(&its_lock);
>> -}
>> -
>> static struct its_device *its_find_device(struct its_node *its, u32
>> dev_id) {
>> struct its_device *its_dev = NULL, *tmp; @@ -3316,6 +3309,56 @@
>> static bool its_alloc_table_entry(struct its_node *its,
>> return true;
>> }
>>
>> +static bool its_alloc_collection_table(struct its_node *its, struct
>> +its_baser *baser) {
>> + int cpu = smp_processor_id();
>> + int cpu_ids = 16;
>> +
>> + if (its->typer & GITS_TYPER_CIL)
>> + cpu_ids = collection_ids(its);
>> +
>> + if (!(ilog2(cpu) < cpu_ids)) {
>> + pr_warn("ITS: CPU%d out of Collection ID range for %dbits", cpu,
>> cpu_ids);
>> + return false;
>> + }
>> +
>> + if (!its_alloc_table_entry(its, baser, cpu)) {
>> + pr_warn("ITS: CPU%d failed to allocate collection l2 table", cpu);
>> + return false;
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static bool its_cpu_init_collections(void) {
>> + struct its_node *its;
>> + struct its_baser *baser;
>> + void __iomem *base;
>> +
>> + raw_spin_lock(&its_lock);
>> +
>> + list_for_each_entry(its, &its_nodes, entry) {
>> + base = its->base;
>> + if (!GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) {
>> + baser = its_get_baser(its, GITS_BASER_TYPE_COLLECTION);
>> + if (!baser) {
>> + raw_spin_unlock(&its_lock);
>> + return false;
>> + }
>> +
>> + if (!its_alloc_collection_table(its, baser)) {
>> + raw_spin_unlock(&its_lock);
>> + return false;
>> + }
>> + }
>> +
>> + its_cpu_init_collection(its);
>> + }
>> + raw_spin_unlock(&its_lock);
>> + return true;
>> +}
>> +
>> static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
>> {
>> struct its_baser *baser;
>> diff --git a/include/linux/irqchip/arm-gic-v3.h
>> b/include/linux/irqchip/arm-gic-v3.h
>> index 728691365464..35e83da8961f 100644
>> --- a/include/linux/irqchip/arm-gic-v3.h
>> +++ b/include/linux/irqchip/arm-gic-v3.h
>> @@ -400,6 +400,9 @@
>> #define GITS_TYPER_PTA (1UL << 19)
>> #define GITS_TYPER_HCC_SHIFT 24
>> #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
>> +#define GITS_TYPER_CIDBITS_SHIFT 32
>> +#define GITS_TYPER_CIDBITS GENMASK_ULL(35, 32)
>> +#define GITS_TYPER_CIL (1ULL << 36)
>> #define GITS_TYPER_VMOVP (1ULL << 37)
>> #define GITS_TYPER_VMAPP (1ULL << 40)
>> #define GITS_TYPER_SVPET GENMASK_ULL(42, 41)
>> --
>> 2.7.4
>>

--
Jazz is not dead. It just smells funny...