2014-11-21 05:08:59

by Dinh Nguyen

Subject: [PATCH 1/2] arm: socfpga: update l2 cache settings

From: Dinh Nguyen <[email protected]>

Enable D and I prefetch helps improve SDRAM preformance.

Signed-off-by: Dinh Nguyen <[email protected]>
---
arch/arm/mach-socfpga/socfpga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf383..13b1858 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -104,7 +104,8 @@ static const char *altera_dt_match[] = {
};

DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
- .l2c_aux_val = 0,
+ .l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
+ L310_AUX_CTRL_INSTR_PREFETCH,
.l2c_aux_mask = ~0,
.smp = smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
--
2.0.3

2014-11-21 05:09:18

by Dinh Nguyen

Subject: [PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

From: Dinh Nguyen <[email protected]>

By not having bit 22 set in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <[email protected]>
---
arch/arm/mach-socfpga/socfpga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 13b1858..afc009f 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -105,7 +105,8 @@ static const char *altera_dt_match[] = {

DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
- L310_AUX_CTRL_INSTR_PREFETCH,
+ L310_AUX_CTRL_INSTR_PREFETCH |
+ L2C_AUX_CTRL_SHARED_OVERRIDE,
.l2c_aux_mask = ~0,
.smp = smp_ops(socfpga_smp_ops),
.map_io = socfpga_map_io,
--
2.0.3

2014-11-21 11:05:16

by Arnd Bergmann

Subject: Re: [PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

On Thursday 20 November 2014 23:04:40 [email protected] wrote:
>
> ---
> arch/arm/mach-socfpga/socfpga.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
> index 13b1858..afc009f 100644
> --- a/arch/arm/mach-socfpga/socfpga.c
> +++ b/arch/arm/mach-socfpga/socfpga.c
> @@ -105,7 +105,8 @@ static const char *altera_dt_match[] = {
>
> DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
> .l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
> - L310_AUX_CTRL_INSTR_PREFETCH,
> + L310_AUX_CTRL_INSTR_PREFETCH |
> + L2C_AUX_CTRL_SHARED_OVERRIDE,
> .l2c_aux_mask = ~0,
> .smp = smp_ops(socfpga_smp_ops),
> .map_io = socfpga_map_io,

Hi Dinh,

Please do this by putting the appropriate proterties into the
l2x0 DT node instead.

Arnd

2014-11-21 15:27:38

by Dinh Nguyen

Subject: Re: [PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

Hi Arnd,

On 11/21/14, 5:04 AM, Arnd Bergmann wrote:
> On Thursday 20 November 2014 23:04:40 [email protected] wrote:
>>
>> ---
>> arch/arm/mach-socfpga/socfpga.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
>> index 13b1858..afc009f 100644
>> --- a/arch/arm/mach-socfpga/socfpga.c
>> +++ b/arch/arm/mach-socfpga/socfpga.c
>> @@ -105,7 +105,8 @@ static const char *altera_dt_match[] = {
>>
>> DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
>> .l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
>> - L310_AUX_CTRL_INSTR_PREFETCH,
>> + L310_AUX_CTRL_INSTR_PREFETCH |
>> + L2C_AUX_CTRL_SHARED_OVERRIDE,
>> .l2c_aux_mask = ~0,
>> .smp = smp_ops(socfpga_smp_ops),
>> .map_io = socfpga_map_io,
>
> Hi Dinh,
>
> Please do this by putting the appropriate proterties into the
> l2x0 DT node instead.
>

I don't see a way to do this yet in DT. Perhaps I'm missing a patchset
to allow this?

Thanks,
Dinh

2014-12-17 19:46:30

by Dinh Nguyen

Subject: Re: [PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

Hi Arnd,

On 11/21/14, 5:04 AM, Arnd Bergmann wrote:
> On Thursday 20 November 2014 23:04:40 [email protected] wrote:
>>
>> ---
>> arch/arm/mach-socfpga/socfpga.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
>> index 13b1858..afc009f 100644
>> --- a/arch/arm/mach-socfpga/socfpga.c
>> +++ b/arch/arm/mach-socfpga/socfpga.c
>> @@ -105,7 +105,8 @@ static const char *altera_dt_match[] = {
>>
>> DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
>> .l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
>> - L310_AUX_CTRL_INSTR_PREFETCH,
>> + L310_AUX_CTRL_INSTR_PREFETCH |
>> + L2C_AUX_CTRL_SHARED_OVERRIDE,
>> .l2c_aux_mask = ~0,
>> .smp = smp_ops(socfpga_smp_ops),
>> .map_io = socfpga_map_io,
>
> Hi Dinh,
>
> Please do this by putting the appropriate proterties into the
> l2x0 DT node instead.
>

I don't see a way to do this using the l2x0 DT node.

Thanks,
Dinh