Fix typo in a macro which was not used until now. It explains why there
is no error at compilation time.
Signed-off-by: Ludovic Desroches <[email protected]>
Fixes: e1f7c9eee707 "dmaengine: at_xdmac: creation of the atmel eXtended
DMA Controller driver"
Cc: [email protected] # 3.19 and later
---
drivers/dma/at_xdmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 7f039de..d09277f 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -156,7 +156,7 @@
#define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
#define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
#define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
-#define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
+#define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */
#define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
#define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
#define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
--
2.5.0
When setting the channel configuration register, the perid field is not
set to 0 since it is useless for mem2mem transfers. Unfortunately, a
device has 0 as perid. It could cause spurious flags status because
the controller could mix some events from the two channels.
For that reason, use the highest perid value for mem2mem transfers since it
doesn't match the perid of other devices.
Signed-off-by: Ludovic Desroches <[email protected]>
---
drivers/dma/at_xdmac.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index d09277f..b90e62f 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -863,8 +863,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
* access. Hopefully we can access DDR through both ports (at least on
* SAMA5D4x), so we can use the same interface for source and dest,
* that solves the fact we don't know the direction.
+ * ERRATA: Even if useless for memory transfers, the PERID has to not
+ * match the one of another channel. If not, it could lead to spurious
+ * flag status.
*/
- u32 chan_cc = AT_XDMAC_CC_DIF(0)
+ u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+ | AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
| AT_XDMAC_CC_MBSIZE_SIXTEEN
| AT_XDMAC_CC_TYPE_MEM_TRAN;
@@ -1039,8 +1043,12 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
* access DDR through both ports (at least on SAMA5D4x), so we can use
* the same interface for source and dest, that solves the fact we
* don't know the direction.
+ * ERRATA: Even if useless for memory transfers, the PERID has to not
+ * match the one of another channel. If not, it could lead to spurious
+ * flag status.
*/
- u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
+ u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+ | AT_XDMAC_CC_DAM_INCREMENTED_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
@@ -1140,8 +1148,12 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
* access. Hopefully we can access DDR through both ports (at least on
* SAMA5D4x), so we can use the same interface for source and dest,
* that solves the fact we don't know the direction.
+ * ERRATA: Even if useless for memory transfers, the PERID has to not
+ * match the one of another channel. If not, it could lead to spurious
+ * flag status.
*/
- u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
+ u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
+ | AT_XDMAC_CC_DAM_UBS_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0)
--
2.5.0
Le 23/11/2015 14:09, Ludovic Desroches a ?crit :
> Fix typo in a macro which was not used until now. It explains why there
> is no error at compilation time.
>
> Signed-off-by: Ludovic Desroches <[email protected]>
> Fixes: e1f7c9eee707 "dmaengine: at_xdmac: creation of the atmel eXtended
> DMA Controller driver"
> Cc: [email protected] # 3.19 and later
Acked-by: Nicolas Ferre <[email protected]>
> ---
> drivers/dma/at_xdmac.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
> index 7f039de..d09277f 100644
> --- a/drivers/dma/at_xdmac.c
> +++ b/drivers/dma/at_xdmac.c
> @@ -156,7 +156,7 @@
> #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
> #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
> #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
> -#define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
> +#define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */
> #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
> #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
> #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
>
--
Nicolas Ferre
Le 23/11/2015 14:09, Ludovic Desroches a ?crit :
> When setting the channel configuration register, the perid field is not
> set to 0 since it is useless for mem2mem transfers. Unfortunately, a
> device has 0 as perid. It could cause spurious flags status because
> the controller could mix some events from the two channels.
> For that reason, use the highest perid value for mem2mem transfers since it
> doesn't match the perid of other devices.
>
> Signed-off-by: Ludovic Desroches <[email protected]>
Indeed: thanks Ludovic:
Acked-by: Nicolas Ferre <[email protected]>
> ---
> drivers/dma/at_xdmac.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
> index d09277f..b90e62f 100644
> --- a/drivers/dma/at_xdmac.c
> +++ b/drivers/dma/at_xdmac.c
> @@ -863,8 +863,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
> * access. Hopefully we can access DDR through both ports (at least on
> * SAMA5D4x), so we can use the same interface for source and dest,
> * that solves the fact we don't know the direction.
> + * ERRATA: Even if useless for memory transfers, the PERID has to not
> + * match the one of another channel. If not, it could lead to spurious
> + * flag status.
> */
> - u32 chan_cc = AT_XDMAC_CC_DIF(0)
> + u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
> + | AT_XDMAC_CC_DIF(0)
> | AT_XDMAC_CC_SIF(0)
> | AT_XDMAC_CC_MBSIZE_SIXTEEN
> | AT_XDMAC_CC_TYPE_MEM_TRAN;
> @@ -1039,8 +1043,12 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
> * access DDR through both ports (at least on SAMA5D4x), so we can use
> * the same interface for source and dest, that solves the fact we
> * don't know the direction.
> + * ERRATA: Even if useless for memory transfers, the PERID has to not
> + * match the one of another channel. If not, it could lead to spurious
> + * flag status.
> */
> - u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
> + u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
> + | AT_XDMAC_CC_DAM_INCREMENTED_AM
> | AT_XDMAC_CC_SAM_INCREMENTED_AM
> | AT_XDMAC_CC_DIF(0)
> | AT_XDMAC_CC_SIF(0)
> @@ -1140,8 +1148,12 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
> * access. Hopefully we can access DDR through both ports (at least on
> * SAMA5D4x), so we can use the same interface for source and dest,
> * that solves the fact we don't know the direction.
> + * ERRATA: Even if useless for memory transfers, the PERID has to not
> + * match the one of another channel. If not, it could lead to spurious
> + * flag status.
> */
> - u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
> + u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
> + | AT_XDMAC_CC_DAM_UBS_AM
> | AT_XDMAC_CC_SAM_INCREMENTED_AM
> | AT_XDMAC_CC_DIF(0)
> | AT_XDMAC_CC_SIF(0)
>
--
Nicolas Ferre
On Mon, Nov 23, 2015 at 02:09:38PM +0100, Ludovic Desroches wrote:
> Fix typo in a macro which was not used until now. It explains why there
> is no error at compilation time.
>
Applied both, thanks
--
~Vinod