v2 updates:
- Style fixes
- Updated to use MACROs for interrupt and gpio property
- Remove dma-coherent for remaining nodes under SoC
Hou Zhiqiang (1):
arm64: dts: ls1046a: Add big-endian property for PCIe nodes
Laurentiu Tudor (2):
arm64: dts: ls1046a: add missing dma ranges property
arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma
size
Li Yang (4):
arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node
arm64: dts: ls1046a: make dma-coherent global to the SoC
arm64: dts: ls1046a: add gpios based i2c recovery information
arm64: dts: ls1046a-qds: add mmio based mdio-mux nodes for FPGA
Pankaj Bansal (1):
arm64: dts: ls1046a-qds: Modify the qspi flash frequency
Xiaowei Bao (1):
arm64: dts: ls1046a: Add the PME interrupt and big-endian to PCIe EP
nodes
.../boot/dts/freescale/fsl-ls1046a-qds.dts | 157 +++++++++++++++++-
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 117 ++++++++-----
2 files changed, 225 insertions(+), 49 deletions(-)
--
2.37.1
Enable USB3 HW LPM feature for ls1046a.
Signed-off-by: Ran Wang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index feab604322cf..ddae3cb0a977 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -717,6 +717,7 @@ usb0: usb@2f00000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
usb1: usb@3000000 {
@@ -727,6 +728,7 @@ usb1: usb@3000000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
usb2: usb@3100000 {
@@ -737,6 +739,7 @@ usb2: usb@3100000 {
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
};
sata: sata@3200000 {
--
2.37.1
From: Xiaowei Bao <[email protected]>
Add the PME interrupt porperty and big-endian property in PCIe EP nodes.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index ddae3cb0a977..8002d83b341b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -813,8 +813,11 @@ pcie_ep1: pcie_ep@3400000 {
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
@@ -849,8 +852,11 @@ pcie_ep2: pcie_ep@3500000 {
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
@@ -885,8 +891,11 @@ pcie_ep3: pcie_ep@3600000 {
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
+ big-endian;
status = "disabled";
};
--
2.37.1
Add scl-gpios property for i2c recovery and add SoC specific
compatible string for SoC specific fixup.
Signed-off-by: Zhang Ying <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 132d7893b4b8..3d9e29824bb2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "fsl,ls1046a";
@@ -501,7 +502,7 @@ dspi: spi@2100000 {
};
i2c0: i2c@2180000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
@@ -515,35 +516,38 @@ i2c0: i2c@2180000 {
};
i2c1: i2c@2190000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
i2c2: i2c@21a0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
i2c3: i2c@21b0000 {
- compatible = "fsl,vf610-i2c";
+ compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
+ scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
--
2.37.1
These SoCs are really completely dma coherent in their entirety so add
the dma-coherent property at the soc level in the device tree and drop
the instances where it's specifically added to a few select devices.
Signed-off-by: Laurentiu Tudor <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 27033c558e3e..e406499a26b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -273,6 +273,7 @@ soc: soc {
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
@@ -355,7 +356,6 @@ crypto: crypto@1700000 {
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
@@ -794,7 +794,6 @@ pcie1: pcie@3400000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
--
2.37.1
From: Pankaj Bansal <[email protected]>
The qspi flash in ls1046a QDS board can operate at 50MHz frequency.
Therefore, update the maximum supported freq in dts file.
Signed-off-by: Pankaj Bansal <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index f969173fb337..b2fcbba60d3a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -182,7 +182,7 @@ qflash0: flash@0 {
compatible = "spansion,m25p80";
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
reg = <0>;
--
2.37.1
There is mmio based mdio mux function in the FPGA device on ls1046a-qds
board. Add the mmio based mdio-mux nodes to ls1043a-qds boards and
add simple-mfd as a compatbile for the FPGA node to reflect the
multi-function nature of it.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Pankaj Bansal <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-ls1046a-qds.dts | 155 +++++++++++++++++-
1 file changed, 153 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index eec62c63dafe..f969173fb337 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*
* Shaohui Xie <[email protected]>
*/
@@ -17,14 +17,26 @@ / {
compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
aliases {
+ emi1-slot1 = &ls1046mdio_s1;
+ emi1-slot2 = &ls1046mdio_s2;
+ emi1-slot4 = &ls1046mdio_s4;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+ sgmii-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-s1-p2 = &sgmii_phy_s1_p2;
+ sgmii-s1-p3 = &sgmii_phy_s1_p3;
+ sgmii-s1-p4 = &sgmii_phy_s1_p4;
+ sgmii-s4-p1 = &sgmii_phy_s4_p1;
};
chosen {
@@ -153,8 +165,9 @@ nand@1,0 {
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <0x2 0x0 0x0000100>;
+ ranges = <0 2 0 0x100>;
};
};
@@ -177,3 +190,141 @@ qflash0: flash@0 {
};
#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&sgmii_phy_s4_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&sgmii_phy_s1_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&sgmii_phy_s1_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ phy-handle = <&sgmii_phy_s1_p1>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* DTSEC10/10GEC2 */
+ phy-handle = <&sgmii_phy_s1_p2>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mdio-mux-emi1 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1046mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1046mdio1: mdio@1 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1046mdio_s1: mdio@2 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ sgmii_phy_s1_p2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy_s1_p3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy_s1_p4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1046mdio_s2: mdio@3 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1046mdio_s4: mdio@5 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--
2.37.1
From: Laurentiu Tudor <[email protected]>
These chips have a 48-bit address size so make sure that the dma-ranges
reflects this. Otherwise the linux kernel's dma sub-system will set
the default dma masks to full 64-bit, badly breaking dmas.
Signed-off-by: Laurentiu Tudor <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index a0619a45f3b8..27033c558e3e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -272,6 +272,7 @@ soc: soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
--
2.37.1
From: Hou Zhiqiang <[email protected]>
Add the big-endian property for LS1046A PCIe RC nodes.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 8002d83b341b..a0619a45f3b8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -805,6 +805,7 @@ pcie1: pcie@3400000 {
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -844,6 +845,7 @@ pcie2: pcie@3500000 {
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
@@ -883,6 +885,7 @@ pcie3: pcie@3600000 {
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
status = "disabled";
};
--
2.37.1
From: Laurentiu Tudor <[email protected]>
Wrap the usb and sata controllers in an intermediate simple-bus and use
it to constrain the dma address size of these usb controllers to the 40
bits that they generate toward the interconnect. This is required
because the SoC uses 48 bits address sizes and this mismatch would lead
to smmu context faults because the usb generates 40-bit addresses while
the smmu page tables are populated with 48-bit wide addresses.
Suggested-by: Robin Murphy <[email protected]>
Signed-off-by: Laurentiu Tudor <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 90 ++++++++++---------
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index e406499a26b4..132d7893b4b8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -710,47 +710,55 @@ QORIQ_CLK_PLL_DIV(2)>,
QORIQ_CLK_PLL_DIV(2)>;
};
- usb0: usb@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb1: usb@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb2: usb@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- sata: sata@3200000 {
- compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
- QORIQ_CLK_PLL_DIV(2)>;
+ aux_bus: aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
+
+ usb0: usb@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb1: usb@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb2: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1046a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ };
};
msi1: msi-controller@1580000 {
--
2.37.1
Hi All,
On 9/15/22 7:34 PM, Li Yang wrote:
> These SoCs are really completely dma coherent in their entirety so add
> the dma-coherent property at the soc level in the device tree and drop
> the instances where it's specifically added to a few select devices.
>
> Signed-off-by: Laurentiu Tudor <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 27033c558e3e..e406499a26b4 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -273,6 +273,7 @@ soc: soc {
> #size-cells = <2>;
> ranges;
> dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> + dma-coherent;
>
> ddr: memory-controller@1080000 {
> compatible = "fsl,qoriq-memory-controller";
> @@ -355,7 +356,6 @@ crypto: crypto@1700000 {
> ranges = <0x0 0x00 0x1700000 0x100000>;
> reg = <0x00 0x1700000 0x0 0x100000>;
> interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> - dma-coherent;
>
> sec_jr0: jr@10000 {
> compatible = "fsl,sec-v5.4-job-ring",
> @@ -794,7 +794,6 @@ pcie1: pcie@3400000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
>
I'd like to summarize the conclusions of [1] below. This patch breaks
I2C0, which is the only user of eDMA at the moment. eDMA is noncoherent
because snooping is not enabled for it. I have submitted a patch [2] to
U-Boot to enable snooping for eDMA. For now, this patch must add
dma-noncoherent to the i2c0 node.
--Sean
[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#t
[2] https://lore.kernel.org/u-boot/[email protected]/T/#u
> -----Original Message-----
> From: Sean Anderson <[email protected]>
> Sent: Friday, September 23, 2022 11:11 AM
> To: Leo Li <[email protected]>; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; Laurentiu Tudor <[email protected]>
> Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global
> to the SoC
>
>
> Hi All,
>
> On 9/15/22 7:34 PM, Li Yang wrote:
> > These SoCs are really completely dma coherent in their entirety so add
> > the dma-coherent property at the soc level in the device tree and drop
> > the instances where it's specifically added to a few select devices.
> >
> > Signed-off-by: Laurentiu Tudor <[email protected]>
> > Signed-off-by: Li Yang <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
> > 1 file changed, 1 insertion(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > index 27033c558e3e..e406499a26b4 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> > @@ -273,6 +273,7 @@ soc: soc {
> > #size-cells = <2>;
> > ranges;
> > dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> > + dma-coherent;
> >
> > ddr: memory-controller@1080000 {
> > compatible = "fsl,qoriq-memory-controller"; @@ -
> 355,7 +356,6 @@
> > crypto: crypto@1700000 {
> > ranges = <0x0 0x00 0x1700000 0x100000>;
> > reg = <0x00 0x1700000 0x0 0x100000>;
> > interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > - dma-coherent;
> >
> > sec_jr0: jr@10000 {
> > compatible = "fsl,sec-v5.4-job-ring", @@ -
> 794,7 +794,6 @@ pcie1:
> > pcie@3400000 {
> > #address-cells = <3>;
> > #size-cells = <2>;
> > device_type = "pci";
> > - dma-coherent;
> > num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > ranges = <0x81000000 0x0 0x00000000 0x40
> 0x00010000 0x0 0x00010000 /* downstream I/O */
> > @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
> > #address-cells = <3>;
> > #size-cells = <2>;
> > device_type = "pci";
> > - dma-coherent;
> > num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > ranges = <0x81000000 0x0 0x00000000 0x48
> 0x00010000 0x0 0x00010000 /* downstream I/O */
> > @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
> > #address-cells = <3>;
> > #size-cells = <2>;
> > device_type = "pci";
> > - dma-coherent;
> > num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > ranges = <0x81000000 0x0 0x00000000 0x50
> 0x00010000 0x0 0x00010000 /* downstream I/O */
> >
>
> I'd like to summarize the conclusions of [1] below. This patch breaks I2C0,
> which is the only user of eDMA at the moment. eDMA is noncoherent
> because snooping is not enabled for it. I have submitted a patch [2] to U-
> Boot to enable snooping for eDMA. For now, this patch must add dma-
> noncoherent to the i2c0 node.
I have sent a V3 yesterday to set dma-noncoherent on edma node. But are you saying that the dma-noncoherent need to be added to the i2c node to make it work?
For the u-boot patch, I will check with the hardware team to see if it is safe to set the reserved bit for edma snooping. There is a problem with this is that it breaks the i2c for older u-boot. Probably the best way is to make the default to be non-coherent in dts and update it in u-boot when snooping is enabled?
Regards,
Leo
On 9/23/22 12:26 PM, Leo Li wrote:
>
>
>> -----Original Message-----
>> From: Sean Anderson <[email protected]>
>> Sent: Friday, September 23, 2022 11:11 AM
>> To: Leo Li <[email protected]>; [email protected];
>> [email protected]
>> Cc: [email protected]; [email protected]; linux-
>> [email protected]; Laurentiu Tudor <[email protected]>
>> Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global
>> to the SoC
>>
>>
>> Hi All,
>>
>> On 9/15/22 7:34 PM, Li Yang wrote:
>> > These SoCs are really completely dma coherent in their entirety so add
>> > the dma-coherent property at the soc level in the device tree and drop
>> > the instances where it's specifically added to a few select devices.
>> >
>> > Signed-off-by: Laurentiu Tudor <[email protected]>
>> > Signed-off-by: Li Yang <[email protected]>
>> > ---
>> > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
>> > 1 file changed, 1 insertion(+), 4 deletions(-)
>> >
>> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> > b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> > index 27033c558e3e..e406499a26b4 100644
>> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> > @@ -273,6 +273,7 @@ soc: soc {
>> > #size-cells = <2>;
>> > ranges;
>> > dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
>> > + dma-coherent;
>> >
>> > ddr: memory-controller@1080000 {
>> > compatible = "fsl,qoriq-memory-controller"; @@ -
>> 355,7 +356,6 @@
>> > crypto: crypto@1700000 {
>> > ranges = <0x0 0x00 0x1700000 0x100000>;
>> > reg = <0x00 0x1700000 0x0 0x100000>;
>> > interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> > - dma-coherent;
>> >
>> > sec_jr0: jr@10000 {
>> > compatible = "fsl,sec-v5.4-job-ring", @@ -
>> 794,7 +794,6 @@ pcie1:
>> > pcie@3400000 {
>> > #address-cells = <3>;
>> > #size-cells = <2>;
>> > device_type = "pci";
>> > - dma-coherent;
>> > num-viewport = <8>;
>> > bus-range = <0x0 0xff>;
>> > ranges = <0x81000000 0x0 0x00000000 0x40
>> 0x00010000 0x0 0x00010000 /* downstream I/O */
>> > @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
>> > #address-cells = <3>;
>> > #size-cells = <2>;
>> > device_type = "pci";
>> > - dma-coherent;
>> > num-viewport = <8>;
>> > bus-range = <0x0 0xff>;
>> > ranges = <0x81000000 0x0 0x00000000 0x48
>> 0x00010000 0x0 0x00010000 /* downstream I/O */
>> > @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
>> > #address-cells = <3>;
>> > #size-cells = <2>;
>> > device_type = "pci";
>> > - dma-coherent;
>> > num-viewport = <8>;
>> > bus-range = <0x0 0xff>;
>> > ranges = <0x81000000 0x0 0x00000000 0x50
>> 0x00010000 0x0 0x00010000 /* downstream I/O */
>> >
>>
>> I'd like to summarize the conclusions of [1] below. This patch breaks I2C0,
>> which is the only user of eDMA at the moment. eDMA is noncoherent
>> because snooping is not enabled for it. I have submitted a patch [2] to U-
>> Boot to enable snooping for eDMA. For now, this patch must add dma-
>> noncoherent to the i2c0 node.
>
> I have sent a V3 yesterday to set dma-noncoherent on edma node. But are you saying that the dma-noncoherent need to be added to the i2c node to make it work?
I believe dma coherency is a property of the consumer, not the provider. See
e.g. really_probe/platform_dma_configure/of_dma_configure/of_dma_is_coherent.
> For the u-boot patch, I will check with the hardware team to see if it is safe to set the reserved bit for edma snooping.
Thanks. I'm curious as to whether this omission is intentional or not.
> There is a problem with this is that it breaks the i2c for older u-boot. Probably the best way is to make the default to be non-coherent in dts and update it in u-boot when snooping is enabled?
Yes, that is what I propose.
--Sean
> -----Original Message-----
> From: Sean Anderson <[email protected]>
> Sent: Friday, September 23, 2022 11:35 AM
> To: Leo Li <[email protected]>; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; Laurentiu Tudor <[email protected]>
> Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global
> to the SoC
>
>
>
> On 9/23/22 12:26 PM, Leo Li wrote:
> >
> >
> >> -----Original Message-----
> >> From: Sean Anderson <[email protected]>
> >> Sent: Friday, September 23, 2022 11:11 AM
> >> To: Leo Li <[email protected]>; [email protected];
> >> [email protected]
> >> Cc: [email protected]; [email protected]; linux-
> >> [email protected]; Laurentiu Tudor <[email protected]>
> >> Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent
> >> global to the SoC
> >>
> >>
> >> Hi All,
> >>
> >> On 9/15/22 7:34 PM, Li Yang wrote:
> >> > These SoCs are really completely dma coherent in their entirety so
> >> > add the dma-coherent property at the soc level in the device tree
> >> > and drop the instances where it's specifically added to a few select
> devices.
> >> >
> >> > Signed-off-by: Laurentiu Tudor <[email protected]>
> >> > Signed-off-by: Li Yang <[email protected]>
> >> > ---
> >> > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
> >> > 1 file changed, 1 insertion(+), 4 deletions(-)
> >> >
> >> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> >> > b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> >> > index 27033c558e3e..e406499a26b4 100644
> >> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> >> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> >> > @@ -273,6 +273,7 @@ soc: soc {
> >> > #size-cells = <2>;
> >> > ranges;
> >> > dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> >> > + dma-coherent;
> >> >
> >> > ddr: memory-controller@1080000 {
> >> > compatible = "fsl,qoriq-memory-controller"; @@ -
> >> 355,7 +356,6 @@
> >> > crypto: crypto@1700000 {
> >> > ranges = <0x0 0x00 0x1700000 0x100000>;
> >> > reg = <0x00 0x1700000 0x0 0x100000>;
> >> > interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> >> > - dma-coherent;
> >> >
> >> > sec_jr0: jr@10000 {
> >> > compatible = "fsl,sec-v5.4-job-ring", @@ -
> >> 794,7 +794,6 @@ pcie1:
> >> > pcie@3400000 {
> >> > #address-cells = <3>;
> >> > #size-cells = <2>;
> >> > device_type = "pci";
> >> > - dma-coherent;
> >> > num-viewport = <8>;
> >> > bus-range = <0x0 0xff>;
> >> > ranges = <0x81000000 0x0 0x00000000 0x40
> >> 0x00010000 0x0 0x00010000 /* downstream I/O */
> >> > @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
> >> > #address-cells = <3>;
> >> > #size-cells = <2>;
> >> > device_type = "pci";
> >> > - dma-coherent;
> >> > num-viewport = <8>;
> >> > bus-range = <0x0 0xff>;
> >> > ranges = <0x81000000 0x0 0x00000000 0x48
> >> 0x00010000 0x0 0x00010000 /* downstream I/O */
> >> > @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
> >> > #address-cells = <3>;
> >> > #size-cells = <2>;
> >> > device_type = "pci";
> >> > - dma-coherent;
> >> > num-viewport = <8>;
> >> > bus-range = <0x0 0xff>;
> >> > ranges = <0x81000000 0x0 0x00000000 0x50
> >> 0x00010000 0x0 0x00010000 /* downstream I/O */
> >> >
> >>
> >> I'd like to summarize the conclusions of [1] below. This patch breaks
> >> I2C0, which is the only user of eDMA at the moment. eDMA is
> >> noncoherent because snooping is not enabled for it. I have submitted
> >> a patch [2] to U- Boot to enable snooping for eDMA. For now, this
> >> patch must add dma- noncoherent to the i2c0 node.
> >
> > I have sent a V3 yesterday to set dma-noncoherent on edma node. But are
> you saying that the dma-noncoherent need to be added to the i2c node to
> make it work?
>
> I believe dma coherency is a property of the consumer, not the provider. See
> e.g.
> really_probe/platform_dma_configure/of_dma_configure/of_dma_is_cohe
> rent.
You are probably right. The provider dma driver only maps the MMIO register while the consumer i2c driver maps the data buffer in memory which needs correct coherency setting.
>
> > For the u-boot patch, I will check with the hardware team to see if it is safe
> to set the reserved bit for edma snooping.
>
> Thanks. I'm curious as to whether this omission is intentional or not.
I have asked around but no one seems to know why LS1046a is different. So from your experiment, changing the reserved bit does make a impact on the final result? And setting it together with i2c nodes having dma-coherent enabled make it work. Right? If that's the case, probably it is just a documentation issue that we should fix.
- Leo
On 9/28/22 7:15 PM, Leo Li wrote:
>
>
>> -----Original Message-----
>> From: Sean Anderson <[email protected]>
>> Sent: Friday, September 23, 2022 11:35 AM
>> To: Leo Li <[email protected]>; [email protected];
>> [email protected]
>> Cc: [email protected]; [email protected]; linux-
>> [email protected]; Laurentiu Tudor <[email protected]>
>> Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global
>> to the SoC
>>
>>
>>
>> On 9/23/22 12:26 PM, Leo Li wrote:
>> >
>> >
>> >> -----Original Message-----
>> >> From: Sean Anderson <[email protected]>
>> >> Sent: Friday, September 23, 2022 11:11 AM
>> >> To: Leo Li <[email protected]>; [email protected];
>> >> [email protected]
>> >> Cc: [email protected]; [email protected]; linux-
>> >> [email protected]; Laurentiu Tudor <[email protected]>
>> >> Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent
>> >> global to the SoC
>> >>
>> >>
>> >> Hi All,
>> >>
>> >> On 9/15/22 7:34 PM, Li Yang wrote:
>> >> > These SoCs are really completely dma coherent in their entirety so
>> >> > add the dma-coherent property at the soc level in the device tree
>> >> > and drop the instances where it's specifically added to a few select
>> devices.
>> >> >
>> >> > Signed-off-by: Laurentiu Tudor <[email protected]>
>> >> > Signed-off-by: Li Yang <[email protected]>
>> >> > ---
>> >> > arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
>> >> > 1 file changed, 1 insertion(+), 4 deletions(-)
>> >> >
>> >> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> >> > b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> >> > index 27033c558e3e..e406499a26b4 100644
>> >> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> >> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
>> >> > @@ -273,6 +273,7 @@ soc: soc {
>> >> > #size-cells = <2>;
>> >> > ranges;
>> >> > dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
>> >> > + dma-coherent;
>> >> >
>> >> > ddr: memory-controller@1080000 {
>> >> > compatible = "fsl,qoriq-memory-controller"; @@ -
>> >> 355,7 +356,6 @@
>> >> > crypto: crypto@1700000 {
>> >> > ranges = <0x0 0x00 0x1700000 0x100000>;
>> >> > reg = <0x00 0x1700000 0x0 0x100000>;
>> >> > interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> >> > - dma-coherent;
>> >> >
>> >> > sec_jr0: jr@10000 {
>> >> > compatible = "fsl,sec-v5.4-job-ring", @@ -
>> >> 794,7 +794,6 @@ pcie1:
>> >> > pcie@3400000 {
>> >> > #address-cells = <3>;
>> >> > #size-cells = <2>;
>> >> > device_type = "pci";
>> >> > - dma-coherent;
>> >> > num-viewport = <8>;
>> >> > bus-range = <0x0 0xff>;
>> >> > ranges = <0x81000000 0x0 0x00000000 0x40
>> >> 0x00010000 0x0 0x00010000 /* downstream I/O */
>> >> > @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
>> >> > #address-cells = <3>;
>> >> > #size-cells = <2>;
>> >> > device_type = "pci";
>> >> > - dma-coherent;
>> >> > num-viewport = <8>;
>> >> > bus-range = <0x0 0xff>;
>> >> > ranges = <0x81000000 0x0 0x00000000 0x48
>> >> 0x00010000 0x0 0x00010000 /* downstream I/O */
>> >> > @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
>> >> > #address-cells = <3>;
>> >> > #size-cells = <2>;
>> >> > device_type = "pci";
>> >> > - dma-coherent;
>> >> > num-viewport = <8>;
>> >> > bus-range = <0x0 0xff>;
>> >> > ranges = <0x81000000 0x0 0x00000000 0x50
>> >> 0x00010000 0x0 0x00010000 /* downstream I/O */
>> >> >
>> >>
>> >> I'd like to summarize the conclusions of [1] below. This patch breaks
>> >> I2C0, which is the only user of eDMA at the moment. eDMA is
>> >> noncoherent because snooping is not enabled for it. I have submitted
>> >> a patch [2] to U- Boot to enable snooping for eDMA. For now, this
>> >> patch must add dma- noncoherent to the i2c0 node.
>> >
>> > I have sent a V3 yesterday to set dma-noncoherent on edma node. But are
>> you saying that the dma-noncoherent need to be added to the i2c node to
>> make it work?
>>
>> I believe dma coherency is a property of the consumer, not the provider. See
>> e.g.
>> really_probe/platform_dma_configure/of_dma_configure/of_dma_is_cohe
>> rent.
>
> You are probably right. The provider dma driver only maps the MMIO register while the consumer i2c driver maps the data buffer in memory which needs correct coherency setting.
>
>>
>> > For the u-boot patch, I will check with the hardware team to see if it is safe
>> to set the reserved bit for edma snooping.
>>
>> Thanks. I'm curious as to whether this omission is intentional or not.
>
> I have asked around but no one seems to know why LS1046a is different. So from your experiment, changing the reserved bit does make a impact on the final result?
Yes.
> And setting it together with i2c nodes having dma-coherent enabled make it work. Right?
Yes. But I only tested I2C0.
> If that's the case, probably it is just a documentation issue that we should fix.
Sounds like it.
--Sean