In preparation for adding CPU idle states, hook up the sun4i timer.
Having a non-c3stop clockevent source available is necessary for all
CPUs to simultaneously enter a local-timer-stop idle state.
Changes from v1:
- Removed H616 changes (depends on an unmerged patch set)
- Reworded the patch 4-5 commit messages for clarity
- Added Acked-by tags
Samuel Holland (5):
dt-bindings: timer: Simplify conditional expressions
dt-bindings: timer: Add compatibles for sun50i timers
arm64: dts: allwinner: a64: Sort watchdog node
arm64: dts: allwinner: Add sun4i MMIO timer nodes
arm64: sunxi: Build the sun4i timer driver
.../timer/allwinner,sun4i-a10-timer.yaml | 42 +++++++++----------
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 ++++
4 files changed, 46 insertions(+), 31 deletions(-)
--
2.26.2
On 22/03/2021 05:47, Samuel Holland wrote:
> In preparation for adding CPU idle states, hook up the sun4i timer.
> Having a non-c3stop clockevent source available is necessary for all
> CPUs to simultaneously enter a local-timer-stop idle state.
Why simultaneously ?
> Changes from v1:
> - Removed H616 changes (depends on an unmerged patch set)
> - Reworded the patch 4-5 commit messages for clarity
> - Added Acked-by tags
>
> Samuel Holland (5):
> dt-bindings: timer: Simplify conditional expressions
> dt-bindings: timer: Add compatibles for sun50i timers
> arm64: dts: allwinner: a64: Sort watchdog node
> arm64: dts: allwinner: Add sun4i MMIO timer nodes
> arm64: sunxi: Build the sun4i timer driver
>
> .../timer/allwinner,sun4i-a10-timer.yaml | 42 +++++++++----------
> arch/arm64/Kconfig.platforms | 1 +
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 ++++
> 4 files changed, 46 insertions(+), 31 deletions(-)
>
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On 3/22/21 9:18 AM, Daniel Lezcano wrote:
> On 22/03/2021 05:47, Samuel Holland wrote:
>> In preparation for adding CPU idle states, hook up the sun4i timer.
>> Having a non-c3stop clockevent source available is necessary for all
>> CPUs to simultaneously enter a local-timer-stop idle state.
>
> Why simultaneously ?
Because the CPU providing (the hrtimer providing) the broadcast timer
cannot enter an idle state which would stop that timer. So in my case,
with 4 CPUs, I was seeing at most 3 CPUs enter idle at any given time.
This prevented any cluster-level idle states from doing anything. After
applying this series, I was able to observe the whole cluster powering
down when appropriate.
Regards,
Samuel
>> Changes from v1:
>> - Removed H616 changes (depends on an unmerged patch set)
>> - Reworded the patch 4-5 commit messages for clarity
>> - Added Acked-by tags
>>
>> Samuel Holland (5):
>> dt-bindings: timer: Simplify conditional expressions
>> dt-bindings: timer: Add compatibles for sun50i timers
>> arm64: dts: allwinner: a64: Sort watchdog node
>> arm64: dts: allwinner: Add sun4i MMIO timer nodes
>> arm64: sunxi: Build the sun4i timer driver
>>
>> .../timer/allwinner,sun4i-a10-timer.yaml | 42 +++++++++----------
>> arch/arm64/Kconfig.platforms | 1 +
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
>> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 ++++
>> 4 files changed, 46 insertions(+), 31 deletions(-)
>>
>
>
On 24/03/2021 04:51, Samuel Holland wrote:
> On 3/22/21 9:18 AM, Daniel Lezcano wrote:
>> On 22/03/2021 05:47, Samuel Holland wrote:
>>> In preparation for adding CPU idle states, hook up the sun4i timer.
>>> Having a non-c3stop clockevent source available is necessary for all
>>> CPUs to simultaneously enter a local-timer-stop idle state.
>>
>> Why simultaneously ?
> Because the CPU providing (the hrtimer providing) the broadcast timer
> cannot enter an idle state which would stop that timer. So in my case,
> with 4 CPUs, I was seeing at most 3 CPUs enter idle at any given time.
> This prevented any cluster-level idle states from doing anything. After
> applying this series, I was able to observe the whole cluster powering
> down when appropriate.
Ah, ok. I did not realize this fourth CPU was acting as the broadcast
timer, so allowing at least a CPU power down. This setup is unusual.
The changes make sense.
Acked-by: Daniel Lezcano <[email protected]>
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