The receive_chars function is designed to handle the case where the port
is jammed full on by aborting after 256 characters in one IRQ.
Unfortunately the author of this code forgot that some systems are level
triggered. On these systems the IRQ simply gets invoked again and the
count loop just makes the problem take longer to clear.
In the non level case it appears that a jam could leave the IRQ jammed
forever and ignored - the remaining bytes never appearing.
As far as I can see the code would actually need to clear the interrupt
enable and then restore it on a timer event or similar in order to get
the intended effect.
Alan
AC> The receive_chars function is designed to handle the case where the port
AC> is jammed full on by aborting after 256 characters in one IRQ.
AC> Unfortunately the author of this code forgot that some systems are level
AC> triggered. On these systems the IRQ simply gets invoked again and the
AC> count loop just makes the problem take longer to clear.
Could this be connected wiht the massive amount of these messages when I
use minicom on a PC to see another computers serial console?
serial8250: too much work for irq4
I've seen this on different PC-s, PIIX3+K6 and ICH2+Celeron are the
last ones that I certainly remember behaving like this.
--
Meelis Roos
On Wed, Dec 14, 2005 at 03:23:23PM +0000, Alan Cox wrote:
> The receive_chars function is designed to handle the case where the port
> is jammed full on by aborting after 256 characters in one IRQ.
> Unfortunately the author of this code forgot that some systems are level
> triggered. On these systems the IRQ simply gets invoked again and the
> count loop just makes the problem take longer to clear.
If we trigger this, we can assume that the port is dead anyway, or
we're in a situation where the host CPU can not keep up with the
data stream.
If we want to handle this more gracefully as you suggest, we need
to disable the interrupt from the chip entirely, and flag an error
to the TTY layer.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
On Wed, Dec 14, 2005 at 06:07:00PM +0200, Meelis Roos wrote:
> AC> The receive_chars function is designed to handle the case where the port
> AC> is jammed full on by aborting after 256 characters in one IRQ.
> AC> Unfortunately the author of this code forgot that some systems are level
> AC> triggered. On these systems the IRQ simply gets invoked again and the
> AC> count loop just makes the problem take longer to clear.
>
> Could this be connected wiht the massive amount of these messages when
> I use minicom on a PC to see another computers serial console?
>
> serial8250: too much work for irq4
>
> I've seen this on different PC-s, PIIX3+K6 and ICH2+Celeron are the
> last ones that I certainly remember behaving like this.
Hmm, possibly, but could you apply this patch and provide the resulting
messages please? It'll probably cause some character loss when it
decides to dump some debugging.
diff -up -x BitKeeper -x ChangeSet -x SCCS -x _xlk -x '*.orig' -x '*.rej' -r orig/drivers/serial/8250.c linux/drivers/serial/8250.c
--- orig/drivers/serial/8250.c Mon Apr 4 22:54:05 2005
+++ linux/drivers/serial/8250.c Mon Apr 11 15:39:33 2005
@@ -69,7 +69,8 @@ unsigned int share_irqs = SERIAL8250_SHA
#define DEBUG_INTR(fmt...) do { } while (0)
#endif
-#define PASS_LIMIT 256
+//#define PASS_LIMIT 256
+#define PASS_LIMIT 32
/*
* We default to IRQ0 for the "no irq" hack. Some
@@ -135,6 +137,18 @@ struct uart_8250_port {
*/
void (*pm)(struct uart_port *port,
unsigned int state, unsigned int old);
+
+ struct log {
+ unsigned long jiffies;
+ unsigned char type;
+ unsigned char num;
+ unsigned char unused[2];
+ unsigned char lsr_b;
+ unsigned char iir_b;
+ unsigned char lsr_e;
+ unsigned char iir_e;
+ } log[64];
+ unsigned char log_idx;
};
struct irq_info {
@@ -1284,6 +1304,8 @@ serial8250_handle_port(struct uart_8250_
{
unsigned int status = serial_inp(up, UART_LSR);
+ up->log[up->log_idx].lsr_b = status;
+
DEBUG_INTR("status = %x...", status);
if (status & UART_LSR_DR)
@@ -1291,6 +1313,8 @@ serial8250_handle_port(struct uart_8250_
check_modem_status(up);
if (status & UART_LSR_THRE)
transmit_chars(up);
+
+ up->log[up->log_idx].lsr_e = status;
}
/*
@@ -1318,6 +1342,7 @@ static irqreturn_t serial8250_interrupt(
spin_lock(&i->lock);
l = i->head;
+ again:
do {
struct uart_8250_port *up;
unsigned int iir;
@@ -1325,6 +1350,12 @@ static irqreturn_t serial8250_interrupt(
up = list_entry(l, struct uart_8250_port, list);
iir = serial_in(up, UART_IIR);
+
+ up->log[up->log_idx].jiffies = jiffies;
+ up->log[up->log_idx].type = 0;
+ up->log[up->log_idx].num = pass_counter;
+ up->log[up->log_idx].iir_b = iir;
+
if (!(iir & UART_IIR_NO_INT)) {
spin_lock(&up->port.lock);
serial8250_handle_port(up, regs);
@@ -1336,16 +1367,62 @@ static irqreturn_t serial8250_interrupt(
} else if (end == NULL)
end = l;
+ up->log[up->log_idx].iir_e = serial_in(up, UART_IIR);
+ up->log_idx = (up->log_idx + 1) & 63;
+
l = l->next;
if (l == i->head && pass_counter++ > PASS_LIMIT) {
/* If we hit this, we're dead. */
printk(KERN_ERR "serial8250: too much work for "
"irq%d\n", irq);
+ goto debug;
break;
}
} while (l != end);
+ if (handled)
+ goto out;
+
+ /*
+ * We didn't recognise the interrupt. This could be because the
+ * port raised a receiver interrupt, but left the IIR indicating
+ * no interrupt pending. Scan all ports on this interrupt and
+ * rely upon the LSR only. Luckily this seems to be rare, but
+ * does happen with 16550As. --rmk
+ */
+ l = i->head;
+ do {
+ struct uart_8250_port *up;
+
+ up = list_entry(l, struct uart_8250_port, list);
+ spin_lock(&up->port.lock);
+ serial8250_handle_port(up, regs);
+ spin_unlock(&up->port.lock);
+ l = l->next;
+ } while (l != i->head);
+ goto again;
+
+ debug:
+ l = i->head;
+ do {
+ struct uart_8250_port *up = list_entry(l, struct uart_8250_port, list);
+ int i;
+
+ printk("serial8250: port %p(%d)\n", up, up->port.line);
+ for (i = 0; i < 64; i++)
+ printk("%d: jif=%08lx type=%02x num=%02x iir=%02x lsr=%02x => iir=%02x lsr=%02x\n", i,
+ up->log[(up->log_idx + i) & 63].jiffies,
+ up->log[(up->log_idx + i) & 63].type,
+ up->log[(up->log_idx + i) & 63].num,
+ up->log[(up->log_idx + i) & 63].iir_b,
+ up->log[(up->log_idx + i) & 63].lsr_b,
+ up->log[(up->log_idx + i) & 63].iir_e,
+ up->log[(up->log_idx + i) & 63].lsr_e);
+ l = l->next;
+ } while (l != i->head);
+
+ out:
spin_unlock(&i->lock);
DEBUG_INTR("end.\n");
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> Hmm, possibly, but could you apply this patch and provide the resulting
> messages please? It'll probably cause some character loss when it
> decides to dump some debugging.
Not before friday unfortunately, but I will try then.
--
Meelis Roos ([email protected])
On Mer, 2005-12-14 at 16:55 +0000, Russell King wrote:
> If we trigger this, we can assume that the port is dead anyway, or
> we're in a situation where the host CPU can not keep up with the
> data stream.
Not actually true in some cases.
- When your UART has a large FIFO and pretends to be an 8250 you can get
a 256 byte burst triggered by the box sleeping for a moment or the BIOS
SMI crap going to chat to the battery
- On a virtualised system this trap can trigger because the emulations
don't emulate the bit arrival and baud rate.
In both of those cases recovery is viable. For that matter so is
recovery when the user responds to the complaint message by unplugging
the cable, or where a long burst of framing errors hits you from a
misconfiguration.
Possibly the first two just argue for a larger limit ?
Alan
On Wed, Dec 14, 2005 at 07:08:08PM +0000, Alan Cox wrote:
> On Mer, 2005-12-14 at 16:55 +0000, Russell King wrote:
> > If we trigger this, we can assume that the port is dead anyway, or
> > we're in a situation where the host CPU can not keep up with the
> > data stream.
>
> Not actually true in some cases.
>
> - When your UART has a large FIFO and pretends to be an 8250 you can get
> a 256 byte burst triggered by the box sleeping for a moment or the BIOS
> SMI crap going to chat to the battery
In which case the receive_chars() function gobbles up to 255 characters
from the device before relinquishing to the main interrupt loop. The
main interrupt loop has two exit conditions - no further interrupts
are pending from any device, or we run this loop 256 times.
In the case where further characters are waiting, we will re-run the
receive_chars() function.
Hence, we will check the device up to 256 times and each will potentially
receive 255 characters, which gives about 64K of character reception
before the warning triggers.
Therefore, this scenario is _very_ _very_ unlikely.
> - On a virtualised system this trap can trigger because the emulations
> don't emulate the bit arrival and baud rate.
Again, only if there's more than about 64K of data waiting.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
On Mer, 2005-12-14 at 18:07 +0200, Meelis Roos wrote:
> Could this be connected wiht the massive amount of these messages when I
> use minicom on a PC to see another computers serial console?
I don't think so. The bug as such is something I can only see being
triggerable either by a virtual machine or by something like serious
noise on the signal lines (eg put a 10Khz carrier on the carrier detect
line)
Alan
From: On Behalf Of Alan Cox
> I don't think so. The bug as such is something I can only see being
> triggerable either by a virtual machine or by something like serious
> noise on the signal lines (eg put a 10Khz carrier on the
> carrier detect
> line)
We found and patched this bug in one of our products. The patch was to
raise the loop counter to something more appropriate for our hardware.
The condition: the not-to-speedy embedded CPU and all ports in use.
The interrupt handler would hit the loop limit because the combination
of all ports running meant usually there was one port that needed
servicing, upping the loop count by one.
..Stu
On Wed, Dec 14, 2005 at 08:43:27PM +0200, Meelis Roos wrote:
> >Hmm, possibly, but could you apply this patch and provide the resulting
> >messages please? It'll probably cause some character loss when it
> >decides to dump some debugging.
>
> Not before friday unfortunately, but I will try then.
Any news?
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> Hmm, possibly, but could you apply this patch and provide the resulting
> messages please? It'll probably cause some character loss when it
> decides to dump some debugging.
Here is the full dmesg with it, from ICH2. First messages are from
serial port initialisation and the last ones are from running minicom at
9600 as thje console for a cisco.
Linux version 2.6.15-rc6-g3e1ec1f4 (mroos@rhn) (gcc version 4.0.3 20051201 (prerelease) (Debian 4.0.2-5)) #113 PREEMPT Wed Dec 21 20:14:15 EET 2005
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001ffc0000 (usable)
BIOS-e820: 000000001ffc0000 - 000000001fff8000 (ACPI data)
BIOS-e820: 000000001fff8000 - 0000000020000000 (ACPI NVS)
BIOS-e820: 00000000ffb80000 - 00000000ffc00000 (reserved)
BIOS-e820: 00000000fff00000 - 0000000100000000 (reserved)
511MB LOWMEM available.
On node 0 totalpages: 131008
DMA zone: 4096 pages, LIFO batch:0
DMA32 zone: 0 pages, LIFO batch:0
Normal zone: 126912 pages, LIFO batch:31
HighMem zone: 0 pages, LIFO batch:0
DMI 2.3 present.
ACPI: RSDP (v000 AMI ) @ 0x000ff980
ACPI: RSDT (v001 D815EA D815EEA2 0x20021106 MSFT 0x00001011) @ 0x1fff0000
ACPI: FADT (v001 D815EA EA81510A 0x20021106 MSFT 0x00001011) @ 0x1fff1000
ACPI: DSDT (v001 D815E2 EA81520A 0x00000023 MSFT 0x0100000b) @ 0x00000000
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 30000000 (gap: 20000000:dfb80000)
Built 1 zonelists
Kernel command line: root=/dev/hda3 ro nmi_watchdog=1 lapic
Found and enabled local APIC!
mapped APIC to ffffd000 (fee00000)
Initializing CPU#0
CPU 0 irqstacks, hard=c0414000 soft=c0413000
PID hash table entries: 2048 (order: 11, 32768 bytes)
Detected 897.209 MHz processor.
Using pmtmr for high-res timesource
Console: colour VGA+ 80x25
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 515136k/524032k available (2050k kernel code, 8424k reserved, 917k data, 152k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1795.99 BogoMIPS (lpj=3591986)
Mount-cache hash table entries: 512
CPU: After generic identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: After vendor identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 128K
CPU: After all inits, caps: 0383fbff 00000000 00000000 00000040 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
mtrr: v2.0 (20020519)
CPU: Intel Celeron (Coppermine) stepping 0a
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0e00)
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: PCI BIOS revision 2.10 entry at 0xfda95, last bus=2
PCI: Using configuration type 1
ACPI: Subsystem revision 20050902
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI: Probing PCI hardware (bus 00)
PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO
PCI quirk: region 0500-053f claimed by ICH4 GPIO
Boot video device is 0000:02:00.0
PCI: Transparent bridge - 0000:00:1e.0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCI1._PRT]
ACPI: Power Resource [FDDP] (off)
ACPI: Power Resource [URP1] (off)
ACPI: Power Resource [URP2] (off)
ACPI: Power Resource [LPTP] (off)
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *9 10 11 12)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 *10 11 12)
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 12 devices
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report
TC classifier action (bugs to [email protected] cc [email protected])
PCI: Bridge: 0000:00:01.0
IO window: d000-dfff
MEM window: ff900000-ff9fffff
PREFETCH window: eea00000-f6afffff
PCI: Bridge: 0000:00:1e.0
IO window: c000-cfff
MEM window: ff800000-ff8fffff
PREFETCH window: ee900000-ee9fffff
PCI: Setting latency timer of device 0000:00:1e.0 to 64
Installing knfsd (copyright (C) 1996 [email protected]).
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
ACPI: Power Button (FF) [PWRF]
ACPI: Power Button (CM) [PBTN]
lp: driver loaded but no devices found
Real Time Clock Driver v1.12
Non-volatile memory driver v1.2
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: Detected an Intel i815 Chipset.
agpgart: AGP aperture is 64M @ 0xf8000000
[drm] Initialized drm 1.0.0 20040925
Hangcheck: starting hangcheck timer 0.9.0 (tick is 180 seconds, margin is 60 seconds).
Hangcheck: Using monotonic_clock().
PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
00:07: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:08: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
parport: PnPBIOS parport detected.
parport0: PC-style at 0x378 (0x778), irq 7, dma 3 [PCSPP,TRISTATE,COMPAT,ECP,DMA]
parport0: faking semi-colon
parport0: Printer, Hewlett-Packard HP LaserJet 1100
lp0: using parport0 (interrupt-driven).
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
pktcdvd: v0.2.0a 2004-07-14 Jens Axboe ([email protected]) and [email protected]
e100: Intel(R) PRO/100 Network Driver, 3.4.14-k4-NAPI
e100: Copyright(c) 1999-2005 Intel Corporation
ACPI: PCI Interrupt Link [LNKE] enabled at IRQ 11
PCI: setting IRQ 11 as level-triggered
ACPI: PCI Interrupt 0000:01:08.0[A] -> Link [LNKE] -> GSI 11 (level, low) -> IRQ 11
e100: eth0: e100_probe: addr 0xff8ff000, irq 11, MAC addr 00:03:47:A4:64:D5
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
ICH2: IDE controller at PCI slot 0000:00:1f.1
ICH2: chipset revision 2
ICH2: not 100% native mode: will probe irqs later
ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio
ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:DMA, hdd:pio
Probing IDE interface ide0...
hda: ST380011A, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: CDU5211, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
hda: max request size: 1024KiB
hda: 156301488 sectors (80026 MB) w/2048KiB Cache, CHS=16383/255/63, UDMA(100)
hda: cache flushes supported
hda: hda1 hda2 hda3 hda4
hdc: ATAPI 52X CD-ROM drive, 120kB Cache, UDMA(33)
Uniform CD-ROM driver Revision: 3.20
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
NET: Registered protocol family 2
input: AT Translated Set 2 keyboard as /class/input/input1
IP route cache hash table entries: 8192 (order: 3, 32768 bytes)
TCP established hash table entries: 32768 (order: 5, 131072 bytes)
TCP bind hash table entries: 32768 (order: 5, 131072 bytes)
TCP: Hash tables configured (established 32768 bind 32768)
TCP reno registered
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
Testing NMI watchdog ... OK.
Using IPI Shortcut mode
ACPI wakeup devices:
PBTN PCI1 UAR1 USB USB2 AC9 SMB
ACPI: (supports S0 S1 S4 S5)
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 152k freed
kjournald starting. Commit interval 5 seconds
logips2pp: Detected unknown logitech mouse model 99
input: ImExPS/2 Logitech Explorer Mouse as /class/input/input2
device-mapper: 4.4.0-ioctl (2005-01-12) initialised: [email protected]
usbcore: registered new driver usbfs
usbcore: registered new driver hub
USB Universal Host Controller Interface driver v2.3
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11
ACPI: PCI Interrupt 0000:00:1f.2[D] -> Link [LNKD] -> GSI 11 (level, low) -> IRQ 11
PCI: Setting latency timer of device 0000:00:1f.2 to 64
uhci_hcd 0000:00:1f.2: UHCI Host Controller
uhci_hcd 0000:00:1f.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:1f.2: irq 11, io base 0x0000ef40
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKH] enabled at IRQ 10
PCI: setting IRQ 10 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.4[C] -> Link [LNKH] -> GSI 10 (level, low) -> IRQ 10
PCI: Setting latency timer of device 0000:00:1f.4 to 64
uhci_hcd 0000:00:1f.4: UHCI Host Controller
uhci_hcd 0000:00:1f.4: new USB bus registered, assigned bus number 2
uhci_hcd 0000:00:1f.4: irq 10, io base 0x0000ef80
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 9
PCI: setting IRQ 9 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.5[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:1f.5 to 64
intel8x0_measure_ac97_clock: measured 55398 usecs
intel8x0: clocking to 41147
Adding 1004052k swap on /dev/hda2. Priority:-1 extents:1 across:1004052k
EXT3 FS on hda3, internal journal
NTFS driver 2.1.25 [Flags: R/W MODULE].
SCSI subsystem initialized
Initializing USB Mass Storage driver...
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
smsc47m1: Found SMSC LPC47M10x/LPC47M13x
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda4, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
lp0: ECP mode
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
30: jif=fffef262 type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef262 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef262 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef262 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef262 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef262 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef262 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef262 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef262 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef262 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef262 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef262 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef262 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef262 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef262 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef262 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef262 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef262 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef262 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef262 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef262 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef262 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef262 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef262 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef262 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef262 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef262 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef262 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef262 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef262 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef262 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef262 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef262 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef262 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=fffef262 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef262 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef262 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef262 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef262 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef262 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef262 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef262 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef262 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef262 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef262 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef262 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef262 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef262 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef262 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef262 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef262 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef262 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef262 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef262 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef262 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef262 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef262 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef262 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef262 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef262 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef262 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef262 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef2c8 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
29: jif=fffef2c8 type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00
30: jif=fffef307 type=00 num=00 iir=c1 lsr=00 => iir=c1 lsr=00
31: jif=fffef307 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef307 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef307 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef307 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef307 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef307 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef307 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef307 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef307 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef307 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef307 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef307 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef307 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef307 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef307 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef307 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef307 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef307 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef307 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef307 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef307 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef307 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef307 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef307 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef307 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef307 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef307 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef307 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef307 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef307 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef307 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef307 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef307 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=fffef307 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef307 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef307 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef307 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef307 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef307 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef307 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef307 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef307 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef307 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef307 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef307 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef307 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef307 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef307 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef307 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef307 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef307 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef307 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef307 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef307 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef307 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef307 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef307 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef307 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef307 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef307 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef307 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef307 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef307 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef308 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef308 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef308 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef308 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef308 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef308 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef308 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef308 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef308 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef308 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef308 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef308 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef308 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef308 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef308 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef308 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef308 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef308 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef308 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef308 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef308 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef308 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef308 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef308 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef308 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef308 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef308 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef308 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef308 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef308 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef308 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef308 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef308 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef308 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
30: jif=fffef309 type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef309 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef309 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef309 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef309 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef309 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef309 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef309 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef309 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef309 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef309 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef309 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef309 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef309 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef309 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef309 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef309 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef309 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef309 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef309 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef309 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef309 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef309 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef309 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef309 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef309 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef309 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef309 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef309 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef309 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef309 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef309 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef309 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef309 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef309 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef309 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef309 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef309 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef309 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef309 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef309 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef309 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef309 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef309 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef309 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef309 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef309 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef309 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef309 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef309 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef309 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef309 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef309 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef309 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef309 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef309 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef309 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef309 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef309 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef309 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef309 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef309 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef309 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef309 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef30a type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef30a type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef30a type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef30a type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef30a type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef30a type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef30a type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef30a type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef30a type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef30a type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef30a type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef30a type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef30a type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef30a type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef30a type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef30a type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef30a type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef30a type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef30a type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef30a type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef30a type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef30a type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef30a type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef30a type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef30a type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef30a type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef30a type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef30a type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef30a type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef30a type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef30a type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef30a type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef30a type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef30a type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef30a type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef30a type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef30a type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef30a type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef30a type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef30a type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef30a type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef30a type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef30a type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef30a type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef30a type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef30a type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef30a type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef30a type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef30a type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef30a type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef30a type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef30a type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef30a type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef30a type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef30a type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef30a type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef30a type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef30a type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef30a type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef30a type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef30a type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef30a type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef371 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
29: jif=fffef371 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef3b0 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef3b0 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef3b0 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef3b0 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef3b0 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef3b0 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef3b0 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef3b0 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef3b0 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef3b0 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef3b0 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef3b0 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef3b0 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef3b0 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef3b0 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef3b0 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef3b0 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef3b0 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef3b0 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef3b0 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef3b0 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef3b0 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef3b0 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef3b0 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef3b0 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef3b0 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef3b0 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef3b0 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef3b0 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef3b0 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef3b0 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef3b0 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef3b0 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef3b0 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef3b0 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef3b0 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef3b0 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef3b0 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef3b0 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef3b0 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef3b0 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef3b0 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef3b0 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef3b0 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef3b0 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef3b0 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef3b0 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef3b0 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef3b0 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef3b0 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef3b0 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef3b0 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef3b0 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef3b0 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef3b0 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef3b0 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef3b0 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef3b0 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef3b0 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef3b0 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef3b0 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef3b0 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef3b0 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef3b0 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef3b0 type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60
31: jif=fffef3b0 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef3b0 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef3b0 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef3b0 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef3b0 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef3b0 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef3b0 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef3b0 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef3b0 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef3b0 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef3b0 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef3b0 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef3b0 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef3b0 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef3b0 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef3b0 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef3b0 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef3b1 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef3b1 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef3b1 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef3b1 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef3b1 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef3b1 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef3b1 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef3b1 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef3b1 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef3b1 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef3b1 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef3b1 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef3b1 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef3b1 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef3b1 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef3b1 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef3b0 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef3b0 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef3b0 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef3b0 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef3b0 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef3b0 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef3b0 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef3b0 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef3b0 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef3b0 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef3b0 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef3b0 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef3b0 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef3b0 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef3b1 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef3b1 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef3b1 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef3b1 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef3b1 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef3b1 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef3b1 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef3b1 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef3b1 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef3b1 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef3b1 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef3b1 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef3b1 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef3b1 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef3b1 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef3b1 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef3b1 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef3b1 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef3b1 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef3b1 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef3b1 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef3b1 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef3b1 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef3b1 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef3b1 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef3b1 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef3b1 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef3b1 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef3b1 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef3b1 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef3b1 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef3b1 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef3b1 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef3b1 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef3b1 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef3b1 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef3b1 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef3b1 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef3b1 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef3b1 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef3b1 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef3b1 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef3b1 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef3b1 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef3b1 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef3b1 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef3b1 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef3b1 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef3b1 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef3b1 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
e100: eth0: e100_watchdog: link up, 100Mbps, full-duplex
NET: Registered protocol family 10
lo: Disabled Privacy Extensions
IPv6 over IPv4 tunneling driver
lp0: ECP mode
lp0: ECP mode
lp0: ECP mode
NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
NFSD: recovery directory /var/lib/nfs/v4recovery doesn't exist
NFSD: starting 90-second grace period
eth0: no IPv6 routers present
ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 11
ACPI: PCI Interrupt 0000:02:00.0[A] -> Link [LNKA] -> GSI 11 (level, low) -> IRQ 11
[drm] Initialized r128 2.5.0 20030725 on minor 0:
agpgart: Found an AGP 2.0 compliant device at 0000:00:00.0.
agpgart: Putting AGP V2 device at 0000:00:00.0 into 2x mode
agpgart: Putting AGP V2 device at 0000:02:00.0 into 2x mode
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=fffef308 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef308 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef308 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef308 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef308 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef308 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef308 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef308 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef308 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef308 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef308 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef308 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef308 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef308 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef308 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef308 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef308 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef308 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef308 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef308 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef308 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef308 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef308 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef308 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef308 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef308 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef308 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef308 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef308 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef308 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff388a type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60
31: jif=ffff388a type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=ffff388a type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=ffff388a type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=ffff388a type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=ffff388a type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=ffff388a type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=ffff388a type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=ffff388a type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=ffff388a type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=ffff388a type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=ffff388a type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=ffff388a type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=ffff388a type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=ffff388a type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=ffff388a type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=ffff388a type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=ffff388a type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=ffff388a type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=ffff388a type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=ffff388a type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=ffff388a type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=ffff388a type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=ffff388a type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=ffff388a type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=ffff388a type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=ffff388a type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=ffff388a type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=ffff388a type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=ffff388a type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=ffff388a type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=ffff388a type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=ffff388a type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=ffff388a type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=ffff7fc9 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
1: jif=ffff7fc9 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=ffff834e type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
3: jif=ffff834e type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=ffff8350 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
5: jif=ffff8350 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=ffff8352 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
7: jif=ffff8352 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=ffff8354 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
9: jif=ffff8354 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=ffff8356 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
11: jif=ffff8356 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=ffff8358 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
13: jif=ffff8358 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=ffff835a type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
15: jif=ffff835a type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=ffff835c type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
17: jif=ffff835c type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=ffff835e type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
19: jif=ffff835e type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=ffff8360 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
21: jif=ffff8360 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=ffff8362 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
23: jif=ffff8362 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=ffff8364 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
25: jif=ffff8364 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=ffff8366 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
27: jif=ffff8366 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=ffff8369 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
29: jif=ffff8369 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff836a type=00 num=00 iir=c1 lsr=61 => iir=c1 lsr=60
31: jif=ffff836a type=00 num=01 iir=c1 lsr=61 => iir=c1 lsr=60
32: jif=ffff836a type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=ffff836a type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=ffff836a type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=ffff836a type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=ffff836a type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=ffff836a type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=ffff836a type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=ffff836a type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=ffff836a type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=ffff836a type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=ffff836a type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=ffff836a type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=ffff836a type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=ffff836a type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=ffff836a type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=ffff836a type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=ffff836a type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=ffff836a type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=ffff836a type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=ffff836a type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=ffff836a type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=ffff836a type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=ffff836a type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=ffff836a type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=ffff836a type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=ffff836a type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=ffff836a type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=ffff836a type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=ffff836a type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=ffff836a type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=ffff836a type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=ffff836a type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=ffff836a type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=ffff836a type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=ffff836a type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=ffff836a type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=ffff836a type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=ffff836a type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=ffff836a type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=ffff836a type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=ffff836a type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=ffff836a type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=ffff836a type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=ffff836a type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=ffff836a type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=ffff836a type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=ffff836a type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=ffff836a type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=ffff836a type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=ffff836a type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=ffff836a type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=ffff836a type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=ffff836a type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=ffff836a type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=ffff836a type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=ffff836a type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=ffff836a type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=ffff836a type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=ffff836a type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=ffff836a type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=ffff836a type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=ffff836a type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff836b type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=ffff836b type=00 num=01 iir=c1 lsr=61 => iir=c1 lsr=60
32: jif=ffff836b type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=ffff836b type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=ffff836b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=ffff836b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=ffff836b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=ffff836b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=ffff836b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=ffff836b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=ffff836b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=ffff836b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=ffff836b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=ffff836b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=ffff836b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=ffff836b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=ffff836b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=ffff836b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=ffff836b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=ffff836b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=ffff836b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=ffff836b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=ffff836b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=ffff836b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=ffff836b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=ffff836b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=ffff836b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=ffff836b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=ffff836b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=ffff836b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=ffff836b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=ffff836b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=ffff836b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=ffff836b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=ffff836b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=ffff836b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=ffff836b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=ffff836b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=ffff836b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=ffff836b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=ffff836b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=ffff836b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=ffff836b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=ffff836b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=ffff836b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=ffff836b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=ffff836b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=ffff836b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=ffff836b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=ffff836b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=ffff836b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=ffff836b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=ffff836b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=ffff836b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=ffff836b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=ffff836b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=ffff836b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=ffff836b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=ffff836b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=ffff836b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=ffff836b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=ffff836b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=ffff836b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=ffff836b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff84f3 type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60
31: jif=ffff84f3 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=ffff84f3 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=ffff84f3 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=ffff84f3 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=ffff84f3 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=ffff84f3 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=ffff84f3 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=ffff84f3 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=ffff84f3 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=ffff84f3 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=ffff84f3 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=ffff84f3 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=ffff84f3 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=ffff84f3 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=ffff84f3 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=ffff84f3 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=ffff84f3 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=ffff84f3 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=ffff84f3 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=ffff84f3 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=ffff84f3 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=ffff84f3 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=ffff84f3 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=ffff84f3 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=ffff84f3 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=ffff84f3 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=ffff84f3 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=ffff84f3 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=ffff84f3 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=ffff84f3 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=ffff84f3 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=ffff84f3 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=ffff84f3 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=ffff84f3 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
1: jif=ffff84f3 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
2: jif=ffff84f3 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
3: jif=ffff84f3 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
4: jif=ffff84f3 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
5: jif=ffff84f3 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
6: jif=ffff84f3 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
7: jif=ffff84f3 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
8: jif=ffff84f3 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
9: jif=ffff84f3 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
10: jif=ffff84f3 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
11: jif=ffff84f3 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
12: jif=ffff84f3 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
13: jif=ffff84f3 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
14: jif=ffff84f3 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
15: jif=ffff84f3 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
16: jif=ffff84f3 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
17: jif=ffff84f3 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
18: jif=ffff86eb type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
19: jif=ffff86eb type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=ffff86eb type=00 num=00 iir=cc lsr=e1 => iir=c1 lsr=60
21: jif=ffff86eb type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=ffff87e6 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
23: jif=ffff87e6 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=ffff87e6 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
25: jif=ffff87e6 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=ffff87e6 type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
27: jif=ffff87e6 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=ffff87e6 type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
29: jif=ffff87e6 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff88e1 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=ffff88e1 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=ffff88e1 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=ffff88e1 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=ffff88e1 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=ffff88e1 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=ffff88e1 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=ffff88e1 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=ffff88e1 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=ffff88e1 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=ffff88e1 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=ffff88e1 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=ffff88e1 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=ffff88e1 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=ffff88e1 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=ffff88e1 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=ffff88e1 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=ffff88e1 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=ffff88e1 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=ffff88e1 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=ffff88e1 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=ffff88e1 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=ffff88e1 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=ffff88e1 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=ffff88e1 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=ffff88e1 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=ffff88e1 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=ffff88e1 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=ffff88e1 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=ffff88e1 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=ffff88e1 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=ffff88e1 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=ffff88e1 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=ffff88e1 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
--
Meelis Roos ([email protected])
On Wed, Dec 21, 2005 at 10:33:37PM +0200, Meelis Roos wrote:
> >Hmm, possibly, but could you apply this patch and provide the resulting
> >messages please? It'll probably cause some character loss when it
> >decides to dump some debugging.
>
> Here is the full dmesg with it, from ICH2. First messages are from
> serial port initialisation and the last ones are from running minicom at
> 9600 as thje console for a cisco.
Urm, this is silly. Lets look at the first instance.
> lp0: ECP mode
> serial8250: too much work for irq4
> serial8250: port c0452c80(0)
> 0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
> ...
> 29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
> 30: jif=fffef262 type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
This is the first interrupt we apparantly recieved. We start with
end = NULL, l = i->head, and pass_counter starts off at zero (as
can be seen in the num line above.)
up = list_entry(l, struct uart_8250_port, list);
iir = serial_in(up, UART_IIR);
The IIR for the device reports 0x01 (IIR_NO_INT set) so no interrupt
was pending, so:
if (!(iir & UART_IIR_NO_INT)) {
} else if (end == NULL)
end = l;
we set our end marker to this port and move on to the next port.
l = l->next;
Since we only have one port open on this IRQ, l is equal to l->next
so this has no effect.
if (l == i->head && pass_counter++ > PASS_LIMIT) {
since l is still equal to i->head, we increment the pass counter.
} while (l != end);
We set end = l above. Given the comments above, that means that l
_is_ equal to end, so we should exit this loop.
> 31: jif=fffef262 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
However, strangely we don't exit the loop, but we go around for
another go - since we can see num=1 here, which means pass_counter
is now '1'.
In addition, what's weirder is that iir is still saying NO_INT,
yet we seem to have taken a completely different path through
the code since the LSR value is now set. This is only set in the
other branch of the if statement, inside serial8250_handle_port().
> 32: jif=fffef262 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
And we go again... and again...
> 62: jif=fffef262 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
> 63: jif=fffef262 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
until we hit the PASS_LIMIT and produce this dump.
The rest of the dumps show a very similar situation. To me, it
looks like your machine is _not_ doing what the C code is telling
it to do. Compiler bug maybe?
> serial8250: too much work for irq4
> serial8250: port c0452c80(0)
> 0: jif=fffef262 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
> 1: jif=fffef262 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
> 2: jif=fffef262 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
> 3: jif=fffef262 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
> 4: jif=fffef262 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
> 5: jif=fffef262 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
> 6: jif=fffef262 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
> 7: jif=fffef262 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
> 8: jif=fffef262 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
> 9: jif=fffef262 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
> 10: jif=fffef262 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
> 11: jif=fffef262 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
> 12: jif=fffef262 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
> 13: jif=fffef262 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
> 14: jif=fffef262 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
> 15: jif=fffef262 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
> 16: jif=fffef262 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
> 17: jif=fffef262 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
> 18: jif=fffef262 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
> 19: jif=fffef262 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
> 20: jif=fffef262 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
> 21: jif=fffef262 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
> 22: jif=fffef262 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
> 23: jif=fffef262 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
> 24: jif=fffef262 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
> 25: jif=fffef262 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
> 26: jif=fffef262 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
> 27: jif=fffef262 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
> 28: jif=fffef2c8 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
Ah, a real interrupt for once - a transmit interrupt which we
service, and then...
> 29: jif=fffef2c8 type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00
recheck the interrupt status and then exit as we should always
do. Why this is any different from the previous one I've no
idea... so maybe it can't be a compiler bug...
Unless the compiler is messing up the initialiser for:
struct list_head *l, *end = NULL;
Could you try placing a:
BUG_ON(end != NULL);
between:
spin_lock(&i->lock);
and:
l = i->head;
in serial8250_interrupt please?
If that doesn't trigger, then I'm all out of ideas.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> Unless the compiler is messing up the initialiser for:
>
> struct list_head *l, *end = NULL;
>
> Could you try placing a:
>
> BUG_ON(end != NULL);
>
> between:
>
> spin_lock(&i->lock);
>
> and:
>
> l = i->head;
>
> in serial8250_interrupt please?
>
> If that doesn't trigger, then I'm all out of ideas.
It did not trigger.
But I might have some more information:
The first bunch of messages did not happen on serial port detection but
when "discover" ran and opened the serial port.
The second bunch of messages happened when minicom opened the port. I
then modprobed tulip to see separating lines in dmesg. Then I used cisco
remote console and no messages appeared. Then I powered down the cisco
and then quited minicom. This took time and produced another bunch of
messages.
Linux version 2.6.15-rc6-gd5ea4e26 (mroos@rhn) (gcc version 4.0.3 20051201 (prerelease) (Debian 4.0.2-5)) #114 PREEMPT Thu Dec 22 12:07:53 EET 2005
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001ffc0000 (usable)
BIOS-e820: 000000001ffc0000 - 000000001fff8000 (ACPI data)
BIOS-e820: 000000001fff8000 - 0000000020000000 (ACPI NVS)
BIOS-e820: 00000000ffb80000 - 00000000ffc00000 (reserved)
BIOS-e820: 00000000fff00000 - 0000000100000000 (reserved)
511MB LOWMEM available.
On node 0 totalpages: 131008
DMA zone: 4096 pages, LIFO batch:0
DMA32 zone: 0 pages, LIFO batch:0
Normal zone: 126912 pages, LIFO batch:31
HighMem zone: 0 pages, LIFO batch:0
DMI 2.3 present.
ACPI: RSDP (v000 AMI ) @ 0x000ff980
ACPI: RSDT (v001 D815EA D815EEA2 0x20021106 MSFT 0x00001011) @ 0x1fff0000
ACPI: FADT (v001 D815EA EA81510A 0x20021106 MSFT 0x00001011) @ 0x1fff1000
ACPI: DSDT (v001 D815E2 EA81520A 0x00000023 MSFT 0x0100000b) @ 0x00000000
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 30000000 (gap: 20000000:dfb80000)
Built 1 zonelists
Kernel command line: root=/dev/hda3 ro nmi_watchdog=1 lapic
Found and enabled local APIC!
mapped APIC to ffffd000 (fee00000)
Initializing CPU#0
CPU 0 irqstacks, hard=c0414000 soft=c0413000
PID hash table entries: 2048 (order: 11, 32768 bytes)
Detected 897.201 MHz processor.
Using pmtmr for high-res timesource
Console: colour VGA+ 80x25
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 515136k/524032k available (2049k kernel code, 8424k reserved, 918k data, 152k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1796.06 BogoMIPS (lpj=3592124)
Mount-cache hash table entries: 512
CPU: After generic identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: After vendor identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 128K
CPU: After all inits, caps: 0383fbff 00000000 00000000 00000040 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
mtrr: v2.0 (20020519)
CPU: Intel Celeron (Coppermine) stepping 0a
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0e00)
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: PCI BIOS revision 2.10 entry at 0xfda95, last bus=2
PCI: Using configuration type 1
ACPI: Subsystem revision 20050902
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI: Probing PCI hardware (bus 00)
PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO
PCI quirk: region 0500-053f claimed by ICH4 GPIO
Boot video device is 0000:02:00.0
PCI: Transparent bridge - 0000:00:1e.0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCI1._PRT]
ACPI: Power Resource [FDDP] (off)
ACPI: Power Resource [URP1] (off)
ACPI: Power Resource [URP2] (off)
ACPI: Power Resource [LPTP] (off)
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *9 10 11 12)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 *10 11 12)
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 12 devices
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report
TC classifier action (bugs to [email protected] cc [email protected])
PCI: Bridge: 0000:00:01.0
IO window: d000-dfff
MEM window: ff900000-ff9fffff
PREFETCH window: eea00000-f6afffff
PCI: Bridge: 0000:00:1e.0
IO window: c000-cfff
MEM window: ff800000-ff8fffff
PREFETCH window: ee900000-ee9fffff
PCI: Setting latency timer of device 0000:00:1e.0 to 64
Installing knfsd (copyright (C) 1996 [email protected]).
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
ACPI: Power Button (FF) [PWRF]
ACPI: Power Button (CM) [PBTN]
lp: driver loaded but no devices found
Real Time Clock Driver v1.12
Non-volatile memory driver v1.2
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: Detected an Intel i815 Chipset.
agpgart: AGP aperture is 64M @ 0xf8000000
[drm] Initialized drm 1.0.0 20040925
Hangcheck: starting hangcheck timer 0.9.0 (tick is 180 seconds, margin is 60 seconds).
Hangcheck: Using monotonic_clock().
PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
00:07: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:08: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
parport: PnPBIOS parport detected.
parport0: PC-style at 0x378 (0x778), irq 7, dma 3 [PCSPP,TRISTATE,COMPAT,ECP,DMA]
parport0: faking semi-colon
parport0: Printer, Hewlett-Packard HP LaserJet 1100
lp0: using parport0 (interrupt-driven).
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
pktcdvd: v0.2.0a 2004-07-14 Jens Axboe ([email protected]) and [email protected]
e100: Intel(R) PRO/100 Network Driver, 3.4.14-k4-NAPI
e100: Copyright(c) 1999-2005 Intel Corporation
ACPI: PCI Interrupt Link [LNKE] enabled at IRQ 11
PCI: setting IRQ 11 as level-triggered
ACPI: PCI Interrupt 0000:01:08.0[A] -> Link [LNKE] -> GSI 11 (level, low) -> IRQ 11
e100: eth0: e100_probe: addr 0xff8ff000, irq 11, MAC addr 00:03:47:A4:64:D5
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
ICH2: IDE controller at PCI slot 0000:00:1f.1
ICH2: chipset revision 2
ICH2: not 100% native mode: will probe irqs later
ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio
ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:DMA, hdd:pio
Probing IDE interface ide0...
hda: ST380011A, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: CDU5211, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
hda: max request size: 1024KiB
hda: 156301488 sectors (80026 MB) w/2048KiB Cache, CHS=16383/255/63, UDMA(100)
hda: cache flushes supported
hda: hda1 hda2 hda3 hda4
hdc: ATAPI 52X CD-ROM drive, 120kB Cache, UDMA(33)
Uniform CD-ROM driver Revision: 3.20
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
NET: Registered protocol family 2
input: AT Translated Set 2 keyboard as /class/input/input1
IP route cache hash table entries: 8192 (order: 3, 32768 bytes)
TCP established hash table entries: 32768 (order: 5, 131072 bytes)
TCP bind hash table entries: 32768 (order: 5, 131072 bytes)
TCP: Hash tables configured (established 32768 bind 32768)
TCP reno registered
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
Testing NMI watchdog ... OK.
Using IPI Shortcut mode
ACPI wakeup devices:
PBTN PCI1 UAR1 USB USB2 AC9 SMB
ACPI: (supports S0 S1 S4 S5)
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 152k freed
kjournald starting. Commit interval 5 seconds
logips2pp: Detected unknown logitech mouse model 99
input: ImExPS/2 Logitech Explorer Mouse as /class/input/input2
device-mapper: 4.4.0-ioctl (2005-01-12) initialised: [email protected]
usbcore: registered new driver usbfs
usbcore: registered new driver hub
USB Universal Host Controller Interface driver v2.3
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11
ACPI: PCI Interrupt 0000:00:1f.2[D] -> Link [LNKD] -> GSI 11 (level, low) -> IRQ 11
PCI: Setting latency timer of device 0000:00:1f.2 to 64
uhci_hcd 0000:00:1f.2: UHCI Host Controller
uhci_hcd 0000:00:1f.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:1f.2: irq 11, io base 0x0000ef40
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKH] enabled at IRQ 10
PCI: setting IRQ 10 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.4[C] -> Link [LNKH] -> GSI 10 (level, low) -> IRQ 10
PCI: Setting latency timer of device 0000:00:1f.4 to 64
uhci_hcd 0000:00:1f.4: UHCI Host Controller
uhci_hcd 0000:00:1f.4: new USB bus registered, assigned bus number 2
uhci_hcd 0000:00:1f.4: irq 10, io base 0x0000ef80
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 9
PCI: setting IRQ 9 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.5[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:1f.5 to 64
intel8x0_measure_ac97_clock: measured 55253 usecs
intel8x0: clocking to 41145
Adding 1004052k swap on /dev/hda2. Priority:-1 extents:1 across:1004052k
EXT3 FS on hda3, internal journal
NTFS driver 2.1.25 [Flags: R/W MODULE].
SCSI subsystem initialized
Initializing USB Mass Storage driver...
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
smsc47m1: Found SMSC LPC47M10x/LPC47M13x
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda4, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
lp0: ECP mode
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
30: jif=fffef7bc type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef7bc type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef7bc type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef7bc type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef7bc type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef7bc type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef7bc type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef7bc type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef7bc type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef7bc type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef7bc type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef7bc type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef7bc type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef7bc type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef7bc type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef7bc type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef7bc type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef7bc type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef7bc type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef7bc type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef7bc type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef7bc type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef7bc type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef7bc type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef7bc type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef7bc type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef7bc type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef7bc type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef7bc type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef7bc type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef7bc type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef7bc type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef7bc type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef7bc type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=fffef7bc type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef7bc type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef7bc type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef7bc type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef7bc type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef7bc type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef7bc type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef7bc type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef7bc type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef7bc type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef7bc type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef7bc type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef7bc type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef7bc type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef7bc type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef7bc type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef7bc type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef7bc type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef7bc type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef7bc type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef7bc type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef7bc type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef7bc type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef7bc type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef7bc type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef7bc type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef7bc type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef7bc type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef823 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
29: jif=fffef823 type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00
30: jif=fffef862 type=00 num=00 iir=c1 lsr=00 => iir=c1 lsr=00
31: jif=fffef862 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef862 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef862 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef862 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef862 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef862 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef862 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef862 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef862 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef862 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef862 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef862 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef862 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef862 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef862 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef862 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef862 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef862 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef862 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef862 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef862 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef862 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef862 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef862 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef862 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef862 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef862 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef862 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef862 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef862 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef862 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef862 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef862 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=fffef862 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef862 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef862 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef862 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef862 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef862 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef862 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef862 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef862 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef862 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef862 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef862 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef862 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef862 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef862 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef862 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef862 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef862 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef862 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef862 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef862 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef862 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef862 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef862 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef862 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef862 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef862 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef862 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef862 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef862 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef863 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef863 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef863 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef863 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef863 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef863 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef863 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef863 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef863 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef863 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef863 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef863 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef863 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef863 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef863 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef863 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef863 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef863 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef863 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef863 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef863 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef863 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef863 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef863 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef863 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef863 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef863 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef863 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef863 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef863 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef863 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef863 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef863 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef863 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
30: jif=fffef864 type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef864 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef864 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef864 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef864 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef864 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef864 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef864 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef864 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef864 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef864 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef864 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef864 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef864 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef864 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef864 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef864 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef864 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef864 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef864 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef864 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef864 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef864 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef864 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef864 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef864 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef864 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef864 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef864 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef864 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef864 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef864 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef864 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef864 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef864 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef864 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef864 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef864 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef864 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef864 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef864 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef864 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef864 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef864 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef864 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef864 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef864 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef864 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef864 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef864 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef864 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef864 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef864 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef864 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef864 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef864 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef864 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef864 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef864 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef864 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef864 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef864 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef864 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef864 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef865 type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef865 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef865 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef865 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef865 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef865 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef865 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef865 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef865 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef865 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef865 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef865 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef865 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef865 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef865 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef865 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef865 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef865 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef865 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef865 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef865 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef865 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef865 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef865 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef865 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef865 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef865 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef865 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef865 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef865 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef865 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef865 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef865 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef865 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef865 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef865 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef865 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef865 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef865 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef865 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef865 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef865 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef865 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef865 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef865 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef865 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef865 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef865 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef865 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef865 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef865 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef865 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef865 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef865 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef865 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef865 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef865 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef865 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef865 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef865 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef865 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef865 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef8cc type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
29: jif=fffef8cc type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef90b type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef90b type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef90b type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef90b type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef90b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef90b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef90b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef90b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef90b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef90b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef90b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef90b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef90b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef90b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef90b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef90b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef90b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef90b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef90b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef90b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef90b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef90b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef90b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef90b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef90b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef90b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef90b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef90b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef90b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef90b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef90b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef90b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef90b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef90b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef90b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef90b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef90b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef90b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef90b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef90b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef90b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef90b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef90b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef90b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef90b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef90b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef90b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef90b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef90b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef90b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef90b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef90b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef90b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef90b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef90b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef90b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef90b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef90b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef90b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef90b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef90b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef90b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef90b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef90b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef90b type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60
31: jif=fffef90b type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef90b type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef90b type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef90b type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef90b type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef90b type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef90b type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef90b type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef90b type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef90b type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef90b type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef90b type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef90b type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef90b type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef90b type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef90b type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef90b type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef90b type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef90b type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef90b type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef90b type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef90b type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef90b type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef90b type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef90b type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef90b type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef90c type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef90c type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef90c type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef90c type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef90c type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef90c type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef90c type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c0453034(1)
0: jif=fffef90b type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef90b type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef90b type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef90b type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef90b type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef90b type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef90b type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef90b type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef90b type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef90b type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef90b type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef90b type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef90b type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef90b type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef90b type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef90b type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef90b type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef90b type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef90b type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef90b type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef90b type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef90b type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef90b type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef90c type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef90c type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef90c type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef90c type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef90c type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef90c type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef90c type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef90c type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef90c type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef90c type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef90c type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef90c type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef90c type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef90c type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef90c type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef90c type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef90c type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef90c type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef90c type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef90c type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef90c type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef90c type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef90c type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef90c type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef90c type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef90c type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef90c type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef90c type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef90c type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef90c type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef90c type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef90c type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef90c type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef90c type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef90c type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef90c type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef90c type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef90c type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef90c type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef90c type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef90c type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
e100: eth0: e100_watchdog: link up, 100Mbps, full-duplex
NET: Registered protocol family 10
lo: Disabled Privacy Extensions
IPv6 over IPv4 tunneling driver
lp0: ECP mode
lp0: ECP mode
lp0: ECP mode
NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
NFSD: recovery directory /var/lib/nfs/v4recovery doesn't exist
NFSD: starting 90-second grace period
eth0: no IPv6 routers present
ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 11
ACPI: PCI Interrupt 0000:02:00.0[A] -> Link [LNKA] -> GSI 11 (level, low) -> IRQ 11
[drm] Initialized r128 2.5.0 20030725 on minor 0:
agpgart: Found an AGP 2.0 compliant device at 0000:00:00.0.
agpgart: Putting AGP V2 device at 0000:00:00.0 into 2x mode
agpgart: Putting AGP V2 device at 0000:02:00.0 into 2x mode
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=fffef863 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef863 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef863 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef863 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef863 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef863 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef863 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef863 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef863 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef863 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef863 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef863 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef863 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef863 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef863 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef863 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef863 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef863 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef863 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef863 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef863 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef863 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef863 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef863 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef863 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef863 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef863 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef863 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef863 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef863 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff36f1 type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60
31: jif=ffff36f1 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=ffff36f1 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=ffff36f1 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=ffff36f1 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=ffff36f1 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=ffff36f1 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=ffff36f1 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=ffff36f1 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=ffff36f1 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=ffff36f1 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=ffff36f1 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=ffff36f1 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=ffff36f1 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=ffff36f1 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=ffff36f1 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=ffff36f1 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=ffff36f1 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=ffff36f1 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=ffff36f1 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=ffff36f1 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=ffff36f1 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=ffff36f1 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=ffff36f1 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=ffff36f1 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=ffff36f1 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=ffff36f1 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=ffff36f1 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=ffff36f1 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=ffff36f1 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=ffff36f1 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=ffff36f1 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=ffff36f1 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=ffff36f1 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
Linux Tulip driver version 1.1.13-NAPI (May 11, 2002)
serial8250: too much work for irq4
serial8250: port c0452c80(0)
0: jif=000023cc type=00 num=00 iir=c0 lsr=61 => iir=c1 lsr=60
1: jif=000023cc type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=000023cc type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
3: jif=000023cc type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=000023cc type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
5: jif=000023cc type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=000023cc type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
7: jif=000023cc type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=000023cc type=00 num=00 iir=c0 lsr=61 => iir=c1 lsr=60
9: jif=000023cc type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
11: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
13: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=000023cd type=00 num=00 iir=c0 lsr=61 => iir=c1 lsr=60
15: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
17: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
19: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
21: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=000023cd type=00 num=00 iir=c6 lsr=e9 => iir=c1 lsr=60
23: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
25: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=000023cd type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
27: jif=000023cd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=000023cf type=00 num=00 iir=c0 lsr=60 => iir=c1 lsr=60
29: jif=000023cf type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=00004773 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=00004773 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=00004773 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=00004773 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=00004773 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=00004773 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=00004773 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=00004773 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=00004773 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=00004773 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=00004773 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=00004773 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=00004773 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=00004773 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=00004773 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=00004773 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=00004773 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=00004773 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=00004773 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=00004773 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=00004773 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=00004773 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=00004773 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=00004773 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=00004773 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=00004773 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=00004773 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=00004773 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=00004773 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=00004773 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=00004773 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=00004773 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=00004773 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=00004773 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
--
Meelis Roos ([email protected])
On Thu, Dec 22, 2005 at 12:35:30PM +0200, Meelis Roos wrote:
> But I might have some more information:
>
> The first bunch of messages did not happen on serial port detection but
> when "discover" ran and opened the serial port.
>
> The second bunch of messages happened when minicom opened the port. I
> then modprobed tulip to see separating lines in dmesg. Then I used cisco
> remote console and no messages appeared. Then I powered down the cisco
> and then quited minicom. This took time and produced another bunch of
> messages.
Thanks for spending the time trying to track this down.
I'm still grasping at straws - it is plainly clear to me from the
debug traces that your machine is _not_ doing what the C code is
asking it to do.
Basically, the characteristics seem to be:
* if the UART indicates no IRQ on invocation of the interrupt
handler, we repeatedly loop in the handler and eventually
hit this "too much work" problem.
* if the UART indicates IRQ on invocation of the interrupt, and
subsequently no IRQ, we exit the interrupt handler as per the
code.
I notice you're using gcc 4.0.3. Have you tried other compiler
versions?
Are you building the kernel with any additional compiler flags?
Are there any other patches applied to the 8250.c file apart from my
debugging patch? What's the diff between a vanilla Linus kernel and
the one you built?
If it isn't a compiler bug and there aren't any other patches applied,
I have no idea what to suggest next, apart from your computer seemingly
following a different set of rules to the rest of the universe. Maybe
you could donate it to some quantum physics lab? 8)
If anyone else has any suggestions, please jump in now.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> I notice you're using gcc 4.0.3. Have you tried other compiler
> versions?
Will try 3.3.
> Are you building the kernel with any additional compiler flags?
No.
> Are there any other patches applied to the 8250.c file apart from my
> debugging patch? What's the diff between a vanilla Linus kernel and
> the one you built?
Clean uptodate -git tree + your patch + BUG_ON
Also have seen this on many earlier kernels that were 100% vanilla.
Both machines having the trouble have kernels that are compiled on this
specific host and with this specific controller.
--
Meelis Roos ([email protected])
> I notice you're using gcc 4.0.3. Have you tried other compiler
> versions?
Tried 3.3 (Debian 3.3.6). Discover still gets the errors, opening port
with minicom didn't this time (maybe I did start minicom an power on the
switch in different order). But when closing minicom, I got the messages
again (after the AGP messages).
Linux version 2.6.15-rc6-gd5ea4e26 (mroos@rhn) (gcc version 3.3.6 (Debian 1:3.3.6-10)) #115 PREEMPT Thu Dec 22 17:30:04 EET 2005
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001ffc0000 (usable)
BIOS-e820: 000000001ffc0000 - 000000001fff8000 (ACPI data)
BIOS-e820: 000000001fff8000 - 0000000020000000 (ACPI NVS)
BIOS-e820: 00000000ffb80000 - 00000000ffc00000 (reserved)
BIOS-e820: 00000000fff00000 - 0000000100000000 (reserved)
511MB LOWMEM available.
On node 0 totalpages: 131008
DMA zone: 4096 pages, LIFO batch:0
DMA32 zone: 0 pages, LIFO batch:0
Normal zone: 126912 pages, LIFO batch:31
HighMem zone: 0 pages, LIFO batch:0
DMI 2.3 present.
ACPI: RSDP (v000 AMI ) @ 0x000ff980
ACPI: RSDT (v001 D815EA D815EEA2 0x20021106 MSFT 0x00001011) @ 0x1fff0000
ACPI: FADT (v001 D815EA EA81510A 0x20021106 MSFT 0x00001011) @ 0x1fff1000
ACPI: DSDT (v001 D815E2 EA81520A 0x00000023 MSFT 0x0100000b) @ 0x00000000
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 30000000 (gap: 20000000:dfb80000)
Built 1 zonelists
Kernel command line: root=/dev/hda3 ro nmi_watchdog=1 lapic
Found and enabled local APIC!
mapped APIC to ffffd000 (fee00000)
Initializing CPU#0
CPU 0 irqstacks, hard=c043e000 soft=c043d000
PID hash table entries: 2048 (order: 11, 32768 bytes)
Detected 897.205 MHz processor.
Using pmtmr for high-res timesource
Console: colour VGA+ 80x25
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 514968k/524032k available (2101k kernel code, 8592k reserved, 1026k data, 160k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1825.21 BogoMIPS (lpj=3650438)
Mount-cache hash table entries: 512
CPU: After generic identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: After vendor identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 128K
CPU: After all inits, caps: 0383fbff 00000000 00000000 00000040 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
mtrr: v2.0 (20020519)
CPU: Intel Celeron (Coppermine) stepping 0a
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0e00)
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: PCI BIOS revision 2.10 entry at 0xfda95, last bus=2
PCI: Using configuration type 1
ACPI: Subsystem revision 20050902
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI: Probing PCI hardware (bus 00)
PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO
PCI quirk: region 0500-053f claimed by ICH4 GPIO
Boot video device is 0000:02:00.0
PCI: Transparent bridge - 0000:00:1e.0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCI1._PRT]
ACPI: Power Resource [FDDP] (off)
ACPI: Power Resource [URP1] (off)
ACPI: Power Resource [URP2] (off)
ACPI: Power Resource [LPTP] (off)
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *9 10 11 12)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 *10 11 12)
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 12 devices
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report
TC classifier action (bugs to [email protected] cc [email protected])
PCI: Bridge: 0000:00:01.0
IO window: d000-dfff
MEM window: ff900000-ff9fffff
PREFETCH window: eea00000-f6afffff
PCI: Bridge: 0000:00:1e.0
IO window: c000-cfff
MEM window: ff800000-ff8fffff
PREFETCH window: ee900000-ee9fffff
PCI: Setting latency timer of device 0000:00:1e.0 to 64
Installing knfsd (copyright (C) 1996 [email protected]).
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
ACPI: Power Button (FF) [PWRF]
ACPI: Power Button (CM) [PBTN]
lp: driver loaded but no devices found
Real Time Clock Driver v1.12
Non-volatile memory driver v1.2
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: Detected an Intel i815 Chipset.
agpgart: AGP aperture is 64M @ 0xf8000000
[drm] Initialized drm 1.0.0 20040925
Hangcheck: starting hangcheck timer 0.9.0 (tick is 180 seconds, margin is 60 seconds).
Hangcheck: Using monotonic_clock().
PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
00:07: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:08: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
parport: PnPBIOS parport detected.
parport0: PC-style at 0x378 (0x778), irq 7, dma 3 [PCSPP,TRISTATE,COMPAT,ECP,DMA]
parport0: faking semi-colon
parport0: Printer, Hewlett-Packard HP LaserJet 1100
lp0: using parport0 (interrupt-driven).
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
pktcdvd: v0.2.0a 2004-07-14 Jens Axboe ([email protected]) and [email protected]
e100: Intel(R) PRO/100 Network Driver, 3.4.14-k4-NAPI
e100: Copyright(c) 1999-2005 Intel Corporation
ACPI: PCI Interrupt Link [LNKE] enabled at IRQ 11
PCI: setting IRQ 11 as level-triggered
ACPI: PCI Interrupt 0000:01:08.0[A] -> Link [LNKE] -> GSI 11 (level, low) -> IRQ 11
e100: eth0: e100_probe: addr 0xff8ff000, irq 11, MAC addr 00:03:47:A4:64:D5
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
ICH2: IDE controller at PCI slot 0000:00:1f.1
ICH2: chipset revision 2
ICH2: not 100% native mode: will probe irqs later
ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio
ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:DMA, hdd:pio
Probing IDE interface ide0...
hda: ST380011A, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: CDU5211, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
hda: max request size: 1024KiB
hda: 156301488 sectors (80026 MB) w/2048KiB Cache, CHS=16383/255/63, UDMA(100)
hda: cache flushes supported
hda: hda1 hda2 hda3 hda4
hdc: ATAPI 52X CD-ROM drive, 120kB Cache, UDMA(33)
Uniform CD-ROM driver Revision: 3.20
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
NET: Registered protocol family 2
input: AT Translated Set 2 keyboard as /class/input/input1
IP route cache hash table entries: 8192 (order: 3, 32768 bytes)
TCP established hash table entries: 32768 (order: 5, 131072 bytes)
TCP bind hash table entries: 32768 (order: 5, 131072 bytes)
TCP: Hash tables configured (established 32768 bind 32768)
TCP reno registered
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
Testing NMI watchdog ... OK.
Using IPI Shortcut mode
ACPI wakeup devices:
PBTN PCI1 UAR1 USB USB2 AC9 SMB
ACPI: (supports S0 S1 S4 S5)
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 160k freed
kjournald starting. Commit interval 5 seconds
logips2pp: Detected unknown logitech mouse model 99
input: ImExPS/2 Logitech Explorer Mouse as /class/input/input2
device-mapper: 4.4.0-ioctl (2005-01-12) initialised: [email protected]
usbcore: registered new driver usbfs
usbcore: registered new driver hub
USB Universal Host Controller Interface driver v2.3
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11
ACPI: PCI Interrupt 0000:00:1f.2[D] -> Link [LNKD] -> GSI 11 (level, low) -> IRQ 11
PCI: Setting latency timer of device 0000:00:1f.2 to 64
uhci_hcd 0000:00:1f.2: UHCI Host Controller
uhci_hcd 0000:00:1f.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:1f.2: irq 11, io base 0x0000ef40
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKH] enabled at IRQ 10
PCI: setting IRQ 10 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.4[C] -> Link [LNKH] -> GSI 10 (level, low) -> IRQ 10
PCI: Setting latency timer of device 0000:00:1f.4 to 64
uhci_hcd 0000:00:1f.4: UHCI Host Controller
uhci_hcd 0000:00:1f.4: new USB bus registered, assigned bus number 2
uhci_hcd 0000:00:1f.4: irq 10, io base 0x0000ef80
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 9
PCI: setting IRQ 9 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.5[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:1f.5 to 64
intel8x0_measure_ac97_clock: measured 133300 usecs
intel8x0: clocking to 41181
Adding 1004052k swap on /dev/hda2. Priority:-1 extents:1 across:1004052k
EXT3 FS on hda3, internal journal
NTFS driver 2.1.25 [Flags: R/W MODULE].
SCSI subsystem initialized
Initializing USB Mass Storage driver...
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
smsc47m1: Found SMSC LPC47M10x/LPC47M13x
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda4, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
lp0: ECP mode
serial8250: too much work for irq4
serial8250: port c047ccc0(0)
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
28: jif=fffef44c type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
29: jif=fffef44c type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00
30: jif=fffef48b type=00 num=00 iir=c1 lsr=00 => iir=c1 lsr=00
31: jif=fffef48b type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef48b type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef48b type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef48b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef48b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef48b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef48b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef48b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef48b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef48b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef48b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef48b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef48b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef48b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef48b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef48b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef48b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef48b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef48b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef48b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef48b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef48b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef48b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef48b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef48b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef48b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef48b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef48b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef48b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef48b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef48b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef48b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef48b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq4
serial8250: port c047ccc0(0)
0: jif=fffef48b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef48b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef48b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef48b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef48b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef48b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef48b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef48b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef48b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef48b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef48b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef48b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef48b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef48b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef48b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef48b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef48b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef48b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef48b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef48b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef48b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef48b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef48b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef48b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef48b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef48b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef48b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef48b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef48b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef48b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef48b type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef48b type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef48b type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef48b type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef48b type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef48b type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef48b type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef48b type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef48b type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef48b type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef48b type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef48b type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef48b type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef48b type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef48b type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef48b type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef48b type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef48b type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef48b type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef48b type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef48b type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef48b type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef48b type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef48b type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef48b type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef48b type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef48b type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef48b type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef48b type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef48b type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef48b type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef48b type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef48b type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef48b type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq4
serial8250: port c047ccc0(0)
0: jif=fffef48b type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef48b type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef48b type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef48b type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef48b type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef48b type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef48b type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef48b type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef48b type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef48b type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef48b type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef48b type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef48b type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef48b type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef48b type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef48b type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef48b type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef48b type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef48b type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef48b type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef48b type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef48b type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef48b type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef48b type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef48b type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef48b type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef48b type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef48b type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef48b type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef48b type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef48d type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef48d type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef48d type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef48d type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef48d type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef48d type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef48d type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef48d type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef48d type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef48d type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef48d type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef48d type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef48d type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef48d type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef48d type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef48d type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef48d type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef48d type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef48d type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef48d type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef48d type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef48d type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef48d type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef48d type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef48d type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef48d type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef48d type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef48d type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef48d type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef48d type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef48d type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef48d type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef48d type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef48d type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq3
serial8250: port c047d074(1)
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00
30: jif=fffef48e type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef48e type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef48e type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef48e type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef48e type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef48e type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef48e type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef48e type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef48e type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef48e type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef48e type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef48e type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef48e type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef48e type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef48e type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef48e type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef48e type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef48e type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef48e type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef48e type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef48e type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef48e type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef48e type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef48e type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef48e type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef48e type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef48e type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef48e type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef48e type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef48e type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef48e type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef48e type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef48e type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef48e type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c047d074(1)
0: jif=fffef48e type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef48e type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef48e type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef48e type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef48e type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef48e type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef48e type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef48e type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef48e type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef48e type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef48e type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef48e type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef48e type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef48e type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef48e type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef48e type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef48e type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef48e type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef48e type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef48e type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef48e type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef48e type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef48e type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef48e type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef48e type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef48e type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef48e type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef48e type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef48e type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef48e type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef48e type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00
31: jif=fffef48e type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef48e type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef48e type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef48e type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef48e type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef48e type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef48e type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef48e type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef48e type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef48e type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef48e type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef48e type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef48e type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef48e type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef48e type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef48e type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef48e type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef48e type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef48e type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef48e type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef48e type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef48e type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef48e type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef48e type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef48e type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef48e type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef48e type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef48e type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef48e type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef48e type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef48e type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef48e type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef48e type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c047d074(1)
0: jif=fffef48e type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef48e type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef48e type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef48e type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef48e type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef48e type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef48e type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef48e type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef48e type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef48e type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef48e type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef48e type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef48e type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef48e type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef48e type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef48e type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef48e type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef48e type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef48e type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef48e type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef48e type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef48e type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef48e type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef48e type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef48e type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef48e type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef48e type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef48e type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef4f6 type=00 num=00 iir=c2 lsr=60 => iir=c1 lsr=60
29: jif=fffef4f6 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef535 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef535 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef535 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef535 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef535 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef535 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef535 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef535 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef535 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef535 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef535 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef535 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef535 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef535 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef535 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef535 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef535 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef535 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef535 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef535 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef535 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef535 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef535 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef535 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef535 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef535 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef535 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef535 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef535 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef535 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef535 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef535 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef535 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef535 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
serial8250: too much work for irq3
serial8250: port c047d074(1)
0: jif=fffef535 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
1: jif=fffef535 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=fffef535 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
3: jif=fffef535 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=fffef535 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
5: jif=fffef535 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=fffef535 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
7: jif=fffef535 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=fffef535 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
9: jif=fffef535 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=fffef535 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
11: jif=fffef535 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=fffef535 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
13: jif=fffef535 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=fffef535 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
15: jif=fffef535 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=fffef535 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
17: jif=fffef535 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=fffef535 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
19: jif=fffef535 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=fffef535 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
21: jif=fffef535 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=fffef535 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
23: jif=fffef535 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=fffef535 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
25: jif=fffef535 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=fffef535 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
27: jif=fffef535 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=fffef535 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
29: jif=fffef535 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=fffef535 type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60
31: jif=fffef535 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60
32: jif=fffef535 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60
33: jif=fffef535 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60
34: jif=fffef535 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
35: jif=fffef535 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
36: jif=fffef535 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
37: jif=fffef535 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
38: jif=fffef535 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
39: jif=fffef535 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
40: jif=fffef535 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
41: jif=fffef535 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
42: jif=fffef535 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
43: jif=fffef535 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
44: jif=fffef535 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
45: jif=fffef535 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
46: jif=fffef535 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
47: jif=fffef535 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
48: jif=fffef535 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
49: jif=fffef535 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
50: jif=fffef535 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
51: jif=fffef535 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
52: jif=fffef535 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
53: jif=fffef535 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
54: jif=fffef535 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
55: jif=fffef535 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
56: jif=fffef535 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
57: jif=fffef535 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
58: jif=fffef535 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
59: jif=fffef535 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
60: jif=fffef535 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
61: jif=fffef535 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
62: jif=fffef535 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
63: jif=fffef536 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
serial8250: too much work for irq3
serial8250: port c047d074(1)
0: jif=fffef535 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60
1: jif=fffef535 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60
2: jif=fffef535 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60
3: jif=fffef535 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60
4: jif=fffef535 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60
5: jif=fffef535 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60
6: jif=fffef535 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60
7: jif=fffef535 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60
8: jif=fffef535 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60
9: jif=fffef535 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60
10: jif=fffef535 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60
11: jif=fffef535 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60
12: jif=fffef535 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60
13: jif=fffef535 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60
14: jif=fffef535 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60
15: jif=fffef535 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60
16: jif=fffef535 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60
17: jif=fffef535 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60
18: jif=fffef535 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60
19: jif=fffef535 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60
20: jif=fffef535 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60
21: jif=fffef535 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60
22: jif=fffef535 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60
23: jif=fffef535 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60
24: jif=fffef535 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60
25: jif=fffef535 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60
26: jif=fffef535 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60
27: jif=fffef535 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60
28: jif=fffef535 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60
29: jif=fffef536 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60
30: jif=fffef536 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60
31: jif=fffef536 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=fffef536 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=fffef536 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=fffef536 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=fffef536 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=fffef536 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=fffef536 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=fffef536 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=fffef536 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=fffef536 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=fffef536 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=fffef536 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=fffef536 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=fffef536 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=fffef536 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=fffef536 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=fffef536 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=fffef536 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=fffef536 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=fffef536 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=fffef536 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=fffef536 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=fffef536 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=fffef536 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=fffef536 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=fffef536 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=fffef536 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=fffef536 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=fffef536 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=fffef536 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=fffef536 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=fffef536 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=fffef536 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
e100: eth0: e100_watchdog: link up, 100Mbps, full-duplex
NET: Registered protocol family 10
lo: Disabled Privacy Extensions
IPv6 over IPv4 tunneling driver
lp0: ECP mode
lp0: ECP mode
lp0: ECP mode
NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
NFSD: recovery directory /var/lib/nfs/v4recovery doesn't exist
NFSD: starting 90-second grace period
eth0: no IPv6 routers present
ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 11
ACPI: PCI Interrupt 0000:02:00.0[A] -> Link [LNKA] -> GSI 11 (level, low) -> IRQ 11
[drm] Initialized r128 2.5.0 20030725 on minor 0:
agpgart: Found an AGP 2.0 compliant device at 0000:00:00.0.
agpgart: Putting AGP V2 device at 0000:00:00.0 into 2x mode
agpgart: Putting AGP V2 device at 0000:02:00.0 into 2x mode
serial8250: too much work for irq4
serial8250: port c047ccc0(0)
0: jif=ffff8251 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
1: jif=ffff8252 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
2: jif=ffff8254 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
3: jif=ffff8254 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
4: jif=ffff8256 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
5: jif=ffff8256 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
6: jif=ffff8258 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
7: jif=ffff8258 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
8: jif=ffff825a type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
9: jif=ffff825a type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
10: jif=ffff825c type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
11: jif=ffff825c type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
12: jif=ffff825e type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
13: jif=ffff825e type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
14: jif=ffff8260 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
15: jif=ffff8260 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
16: jif=ffff8262 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
17: jif=ffff8262 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
18: jif=ffff8264 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
19: jif=ffff8264 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
20: jif=ffff8266 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
21: jif=ffff8266 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
22: jif=ffff8268 type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
23: jif=ffff8268 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
24: jif=ffff826a type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
25: jif=ffff826a type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
26: jif=ffff826c type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
27: jif=ffff826c type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
28: jif=ffff826f type=00 num=00 iir=c4 lsr=61 => iir=c1 lsr=60
29: jif=ffff826f type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
30: jif=ffff9a19 type=00 num=00 iir=c1 lsr=61 => iir=c1 lsr=60
31: jif=ffff9a19 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60
32: jif=ffff9a19 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60
33: jif=ffff9a19 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60
34: jif=ffff9a19 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60
35: jif=ffff9a19 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60
36: jif=ffff9a19 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60
37: jif=ffff9a19 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60
38: jif=ffff9a19 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60
39: jif=ffff9a19 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60
40: jif=ffff9a19 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60
41: jif=ffff9a19 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60
42: jif=ffff9a19 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60
43: jif=ffff9a19 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60
44: jif=ffff9a19 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60
45: jif=ffff9a19 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60
46: jif=ffff9a19 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60
47: jif=ffff9a19 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60
48: jif=ffff9a19 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60
49: jif=ffff9a19 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60
50: jif=ffff9a19 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60
51: jif=ffff9a19 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60
52: jif=ffff9a19 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60
53: jif=ffff9a19 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60
54: jif=ffff9a19 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60
55: jif=ffff9a19 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60
56: jif=ffff9a19 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60
57: jif=ffff9a19 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60
58: jif=ffff9a19 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60
59: jif=ffff9a19 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60
60: jif=ffff9a19 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60
61: jif=ffff9a19 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60
62: jif=ffff9a19 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60
63: jif=ffff9a19 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60
--
Meelis Roos ([email protected])
On Fri, Dec 23, 2005 at 11:20:59AM +0200, Meelis Roos wrote:
> >I notice you're using gcc 4.0.3. Have you tried other compiler
> >versions?
>
> Tried 3.3 (Debian 3.3.6). Discover still gets the errors, opening port
> with minicom didn't this time (maybe I did start minicom an power on the
> switch in different order). But when closing minicom, I got the messages
> again (after the AGP messages).
So not much change.
Ok, please apply this patch on top of the previous and re-send the
kernel messages. This will let us see what's going on with 'l' and
'end'.
Thanks.
--- a/drivers/serial/8250.c 2005-12-23 09:26:45.273235110 +0000
+++ b/drivers/serial/8250.c 2005-12-23 09:32:37.347434791 +0000
@@ -146,6 +146,9 @@
unsigned char iir_b;
unsigned char lsr_e;
unsigned char iir_e;
+ void *l;
+ void *eb;
+ void *ee;
} log[64];
unsigned char log_idx;
};
@@ -1348,8 +1351,11 @@
up->log[up->log_idx].type = 0;
up->log[up->log_idx].num = pass_counter;
up->log[up->log_idx].iir_b = iir;
+ up->log[up->log_idx].l = l;
+ up->log[up->log_idx].eb = end;
if (!(iir & UART_IIR_NO_INT)) {
+ up->log[up->log_idx].type = 1;
spin_lock(&up->port.lock);
serial8250_handle_port(up, regs);
spin_unlock(&up->port.lock);
@@ -1361,6 +1367,7 @@
end = l;
up->log[up->log_idx].iir_e = serial_in(up, UART_IIR);
+ up->log[up->log_idx].ee = end;
up->log_idx = (up->log_idx + 1) & 63;
l = l->next;
@@ -1402,16 +1409,19 @@
struct uart_8250_port *up = list_entry(l, struct uart_8250_port, list);
int i;
- printk("serial8250: port %p(%d)\n", up, up->port.line);
+ printk("serial8250: port %p(%d) head=%p end=%p\n", up, up->port.line, i->head, end);
for (i = 0; i < 64; i++)
- printk("%d: jif=%08lx type=%02x num=%02x iir=%02x lsr=%02x => iir=%02x lsr=%02x\n", i,
+ printk("%d: jif=%08lx type=%02x num=%02x iir=%02x lsr=%02x => iir=%02x lsr=%02x l=%p eb=%p ee=%p\n", i,
up->log[(up->log_idx + i) & 63].jiffies,
up->log[(up->log_idx + i) & 63].type,
up->log[(up->log_idx + i) & 63].num,
up->log[(up->log_idx + i) & 63].iir_b,
up->log[(up->log_idx + i) & 63].lsr_b,
up->log[(up->log_idx + i) & 63].iir_e,
- up->log[(up->log_idx + i) & 63].lsr_e);
+ up->log[(up->log_idx + i) & 63].lsr_e,
+ up->log[(up->log_idx + i) & 63].l,
+ up->log[(up->log_idx + i) & 63].eb,
+ up->log[(up->log_idx + i) & 63].ee);
l = l->next;
} while (l != i->head);
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> Ok, please apply this patch on top of the previous and re-send the
> kernel messages. This will let us see what's going on with 'l' and
> 'end'.
> + printk("serial8250: port %p(%d) head=%p end=%p\n", up, up->port.line, i->head, end);
replaced i->heqad with l because i is shadowed by a local variable here,
now it compiles.
Linux version 2.6.15-rc6-gd5ea4e26 (mroos@rhn) (gcc version 3.3.6 (Debian 1:3.3.6-10)) #116 PREEMPT Fri Dec 23 11:55:40 EET 2005
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001ffc0000 (usable)
BIOS-e820: 000000001ffc0000 - 000000001fff8000 (ACPI data)
BIOS-e820: 000000001fff8000 - 0000000020000000 (ACPI NVS)
BIOS-e820: 00000000ffb80000 - 00000000ffc00000 (reserved)
BIOS-e820: 00000000fff00000 - 0000000100000000 (reserved)
511MB LOWMEM available.
On node 0 totalpages: 131008
DMA zone: 4096 pages, LIFO batch:0
DMA32 zone: 0 pages, LIFO batch:0
Normal zone: 126912 pages, LIFO batch:31
HighMem zone: 0 pages, LIFO batch:0
DMI 2.3 present.
ACPI: RSDP (v000 AMI ) @ 0x000ff980
ACPI: RSDT (v001 D815EA D815EEA2 0x20021106 MSFT 0x00001011) @ 0x1fff0000
ACPI: FADT (v001 D815EA EA81510A 0x20021106 MSFT 0x00001011) @ 0x1fff1000
ACPI: DSDT (v001 D815E2 EA81520A 0x00000023 MSFT 0x0100000b) @ 0x00000000
ACPI: PM-Timer IO Port: 0x408
Allocating PCI resources starting at 30000000 (gap: 20000000:dfb80000)
Built 1 zonelists
Kernel command line: root=/dev/hda3 ro nmi_watchdog=1 lapic
Found and enabled local APIC!
mapped APIC to ffffd000 (fee00000)
Initializing CPU#0
CPU 0 irqstacks, hard=c043e000 soft=c043d000
PID hash table entries: 2048 (order: 11, 32768 bytes)
Detected 897.193 MHz processor.
Using pmtmr for high-res timesource
Console: colour VGA+ 80x25
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 514964k/524032k available (2101k kernel code, 8596k reserved, 1026k data, 160k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay using timer specific routine.. 1814.67 BogoMIPS (lpj=3629359)
Mount-cache hash table entries: 512
CPU: After generic identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: After vendor identify, caps: 0383fbff 00000000 00000000 00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 128K
CPU: After all inits, caps: 0383fbff 00000000 00000000 00000040 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
mtrr: v2.0 (20020519)
CPU: Intel Celeron (Coppermine) stepping 0a
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0e00)
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: PCI BIOS revision 2.10 entry at 0xfda95, last bus=2
PCI: Using configuration type 1
ACPI: Subsystem revision 20050902
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI: Probing PCI hardware (bus 00)
PCI quirk: region 0400-047f claimed by ICH4 ACPI/GPIO/TCO
PCI quirk: region 0500-053f claimed by ICH4 GPIO
Boot video device is 0000:02:00.0
PCI: Transparent bridge - 0000:00:1e.0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCI1._PRT]
ACPI: Power Resource [FDDP] (off)
ACPI: Power Resource [URP1] (off)
ACPI: Power Resource [URP2] (off)
ACPI: Power Resource [LPTP] (off)
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *9 10 11 12)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11 12)
ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11 12) *0, disabled.
ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 *10 11 12)
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 12 devices
PCI: Using ACPI for IRQ routing
PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report
TC classifier action (bugs to [email protected] cc [email protected])
PCI: Bridge: 0000:00:01.0
IO window: d000-dfff
MEM window: ff900000-ff9fffff
PREFETCH window: eea00000-f6afffff
PCI: Bridge: 0000:00:1e.0
IO window: c000-cfff
MEM window: ff800000-ff8fffff
PREFETCH window: ee900000-ee9fffff
PCI: Setting latency timer of device 0000:00:1e.0 to 64
Installing knfsd (copyright (C) 1996 [email protected]).
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
ACPI: Power Button (FF) [PWRF]
ACPI: Power Button (CM) [PBTN]
lp: driver loaded but no devices found
Real Time Clock Driver v1.12
Non-volatile memory driver v1.2
Linux agpgart interface v0.101 (c) Dave Jones
agpgart: Detected an Intel i815 Chipset.
agpgart: AGP aperture is 64M @ 0xf8000000
[drm] Initialized drm 1.0.0 20040925
Hangcheck: starting hangcheck timer 0.9.0 (tick is 180 seconds, margin is 60 seconds).
Hangcheck: Using monotonic_clock().
PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
00:07: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:08: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
parport: PnPBIOS parport detected.
parport0: PC-style at 0x378 (0x778), irq 7, dma 3 [PCSPP,TRISTATE,COMPAT,ECP,DMA]
parport0: faking semi-colon
parport0: Printer, Hewlett-Packard HP LaserJet 1100
lp0: using parport0 (interrupt-driven).
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
pktcdvd: v0.2.0a 2004-07-14 Jens Axboe ([email protected]) and [email protected]
e100: Intel(R) PRO/100 Network Driver, 3.4.14-k4-NAPI
e100: Copyright(c) 1999-2005 Intel Corporation
ACPI: PCI Interrupt Link [LNKE] enabled at IRQ 11
PCI: setting IRQ 11 as level-triggered
ACPI: PCI Interrupt 0000:01:08.0[A] -> Link [LNKE] -> GSI 11 (level, low) -> IRQ 11
e100: eth0: e100_probe: addr 0xff8ff000, irq 11, MAC addr 00:03:47:A4:64:D5
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
ICH2: IDE controller at PCI slot 0000:00:1f.1
ICH2: chipset revision 2
ICH2: not 100% native mode: will probe irqs later
ide0: BM-DMA at 0xffa0-0xffa7, BIOS settings: hda:DMA, hdb:pio
ide1: BM-DMA at 0xffa8-0xffaf, BIOS settings: hdc:DMA, hdd:pio
Probing IDE interface ide0...
hda: ST380011A, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: CDU5211, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
hda: max request size: 1024KiB
hda: 156301488 sectors (80026 MB) w/2048KiB Cache, CHS=16383/255/63, UDMA(100)
hda: cache flushes supported
hda: hda1 hda2 hda3 hda4
hdc: ATAPI 52X CD-ROM drive, 120kB Cache, UDMA(33)
Uniform CD-ROM driver Revision: 3.20
mice: PS/2 mouse device common for all mice
input: PC Speaker as /class/input/input0
NET: Registered protocol family 2
input: AT Translated Set 2 keyboard as /class/input/input1
IP route cache hash table entries: 8192 (order: 3, 32768 bytes)
TCP established hash table entries: 32768 (order: 5, 131072 bytes)
TCP bind hash table entries: 32768 (order: 5, 131072 bytes)
TCP: Hash tables configured (established 32768 bind 32768)
TCP reno registered
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
Testing NMI watchdog ... OK.
Using IPI Shortcut mode
ACPI wakeup devices:
PBTN PCI1 UAR1 USB USB2 AC9 SMB
ACPI: (supports S0 S1 S4 S5)
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 160k freed
kjournald starting. Commit interval 5 seconds
logips2pp: Detected unknown logitech mouse model 99
input: ImExPS/2 Logitech Explorer Mouse as /class/input/input2
device-mapper: 4.4.0-ioctl (2005-01-12) initialised: [email protected]
usbcore: registered new driver usbfs
usbcore: registered new driver hub
USB Universal Host Controller Interface driver v2.3
ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11
ACPI: PCI Interrupt 0000:00:1f.2[D] -> Link [LNKD] -> GSI 11 (level, low) -> IRQ 11
PCI: Setting latency timer of device 0000:00:1f.2 to 64
uhci_hcd 0000:00:1f.2: UHCI Host Controller
uhci_hcd 0000:00:1f.2: new USB bus registered, assigned bus number 1
uhci_hcd 0000:00:1f.2: irq 11, io base 0x0000ef40
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKH] enabled at IRQ 10
PCI: setting IRQ 10 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.4[C] -> Link [LNKH] -> GSI 10 (level, low) -> IRQ 10
PCI: Setting latency timer of device 0000:00:1f.4 to 64
uhci_hcd 0000:00:1f.4: UHCI Host Controller
uhci_hcd 0000:00:1f.4: new USB bus registered, assigned bus number 2
uhci_hcd 0000:00:1f.4: irq 10, io base 0x0000ef80
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 9
PCI: setting IRQ 9 as level-triggered
ACPI: PCI Interrupt 0000:00:1f.5[B] -> Link [LNKB] -> GSI 9 (level, low) -> IRQ 9
PCI: Setting latency timer of device 0000:00:1f.5 to 64
intel8x0_measure_ac97_clock: measured 55619 usecs
intel8x0: clocking to 41151
Adding 1004052k swap on /dev/hda2. Priority:-1 extents:1 across:1004052k
EXT3 FS on hda3, internal journal
NTFS driver 2.1.25 [Flags: R/W MODULE].
SCSI subsystem initialized
Initializing USB Mass Storage driver...
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
smsc47m1: Found SMSC LPC47M10x/LPC47M13x
md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27
md: bitmap version 4.39
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda4, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
lp0: ECP mode
serial8250: too much work for irq4
serial8250: port c047ccc0(0) head=c047cd54 end=c047cd54
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
30: jif=fffef3ba type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00 l=c047cd54 eb=00000000 ee=c047cd54
31: jif=fffef3ba type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
32: jif=fffef3ba type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
33: jif=fffef3ba type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
34: jif=fffef3ba type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
35: jif=fffef3ba type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
36: jif=fffef3ba type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
37: jif=fffef3ba type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
38: jif=fffef3ba type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
39: jif=fffef3ba type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
40: jif=fffef3ba type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
41: jif=fffef3ba type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
42: jif=fffef3ba type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
43: jif=fffef3ba type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
44: jif=fffef3ba type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
45: jif=fffef3ba type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
46: jif=fffef3ba type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
47: jif=fffef3ba type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
48: jif=fffef3ba type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
49: jif=fffef3ba type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
50: jif=fffef3ba type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
51: jif=fffef3ba type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
52: jif=fffef3ba type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
53: jif=fffef3ba type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
54: jif=fffef3ba type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
55: jif=fffef3ba type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
56: jif=fffef3ba type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
57: jif=fffef3ba type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
58: jif=fffef3ba type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
59: jif=fffef3ba type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
60: jif=fffef3ba type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
61: jif=fffef3ba type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
62: jif=fffef3ba type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
63: jif=fffef3ba type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
serial8250: too much work for irq4
serial8250: port c047ccc0(0) head=c047cd54 end=c047cd54
0: jif=fffef3ba type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
1: jif=fffef3ba type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
2: jif=fffef3ba type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
3: jif=fffef3ba type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
4: jif=fffef3ba type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
5: jif=fffef3ba type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
6: jif=fffef3ba type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
7: jif=fffef3ba type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
8: jif=fffef3ba type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
9: jif=fffef3ba type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
10: jif=fffef3ba type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
11: jif=fffef3ba type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
12: jif=fffef3ba type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
13: jif=fffef3ba type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
14: jif=fffef3ba type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
15: jif=fffef3ba type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
16: jif=fffef3ba type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
17: jif=fffef3ba type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
18: jif=fffef3ba type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
19: jif=fffef3ba type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
20: jif=fffef3ba type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
21: jif=fffef3ba type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
22: jif=fffef3ba type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
23: jif=fffef3ba type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
24: jif=fffef3ba type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
25: jif=fffef3ba type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
26: jif=fffef3bd type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
27: jif=fffef3bd type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00 l=c047cd54 eb=00000000 ee=c047cd54
28: jif=fffef421 type=01 num=00 iir=c2 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
29: jif=fffef421 type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00 l=c047cd54 eb=00000000 ee=c047cd54
30: jif=fffef460 type=00 num=00 iir=c1 lsr=00 => iir=c1 lsr=00 l=c047cd54 eb=00000000 ee=c047cd54
31: jif=fffef460 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
32: jif=fffef460 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
33: jif=fffef460 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
34: jif=fffef460 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
35: jif=fffef460 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
36: jif=fffef460 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
37: jif=fffef460 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
38: jif=fffef460 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
39: jif=fffef460 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
40: jif=fffef460 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
41: jif=fffef460 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
42: jif=fffef460 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
43: jif=fffef460 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
44: jif=fffef460 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
45: jif=fffef460 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
46: jif=fffef460 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
47: jif=fffef460 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
48: jif=fffef460 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
49: jif=fffef460 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
50: jif=fffef460 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
51: jif=fffef460 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
52: jif=fffef460 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
53: jif=fffef460 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
54: jif=fffef460 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
55: jif=fffef460 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
56: jif=fffef460 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
57: jif=fffef460 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
58: jif=fffef460 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
59: jif=fffef460 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
60: jif=fffef460 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
61: jif=fffef460 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
62: jif=fffef460 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
63: jif=fffef460 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
serial8250: too much work for irq4
serial8250: port c047ccc0(0) head=c047cd54 end=c047cd54
0: jif=fffef460 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
1: jif=fffef460 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
2: jif=fffef460 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
3: jif=fffef460 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
4: jif=fffef460 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
5: jif=fffef460 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
6: jif=fffef460 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
7: jif=fffef460 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
8: jif=fffef460 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
9: jif=fffef460 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
10: jif=fffef460 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
11: jif=fffef460 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
12: jif=fffef460 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
13: jif=fffef460 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
14: jif=fffef460 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
15: jif=fffef460 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
16: jif=fffef460 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
17: jif=fffef460 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
18: jif=fffef460 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
19: jif=fffef460 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
20: jif=fffef460 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
21: jif=fffef460 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
22: jif=fffef460 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
23: jif=fffef460 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
24: jif=fffef460 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
25: jif=fffef460 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
26: jif=fffef460 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
27: jif=fffef460 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
28: jif=fffef460 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
29: jif=fffef460 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
30: jif=fffef461 type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
31: jif=fffef461 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
32: jif=fffef461 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
33: jif=fffef461 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
34: jif=fffef461 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
35: jif=fffef461 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
36: jif=fffef461 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
37: jif=fffef461 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
38: jif=fffef461 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
39: jif=fffef461 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
40: jif=fffef461 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
41: jif=fffef461 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
42: jif=fffef461 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
43: jif=fffef461 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
44: jif=fffef461 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
45: jif=fffef461 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
46: jif=fffef461 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
47: jif=fffef461 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
48: jif=fffef461 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
49: jif=fffef461 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
50: jif=fffef461 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
51: jif=fffef461 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
52: jif=fffef461 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
53: jif=fffef461 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
54: jif=fffef461 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
55: jif=fffef461 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
56: jif=fffef461 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
57: jif=fffef461 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
58: jif=fffef461 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
59: jif=fffef461 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
60: jif=fffef461 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
61: jif=fffef461 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
62: jif=fffef461 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
63: jif=fffef461 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
serial8250: too much work for irq3
serial8250: port c047d374(1) head=c047d408 end=c047d408
0: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
1: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
2: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
3: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
4: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
5: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
6: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
7: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
8: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
9: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
10: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
11: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
12: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
13: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
14: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
15: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
16: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
17: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
18: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
19: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
20: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
21: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
22: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
23: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
24: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
25: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
26: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
27: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
28: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
29: jif=00000000 type=00 num=00 iir=00 lsr=00 => iir=00 lsr=00 l=00000000 eb=00000000 ee=00000000
30: jif=fffef462 type=00 num=00 iir=01 lsr=00 => iir=01 lsr=00 l=c047d408 eb=00000000 ee=c047d408
31: jif=fffef462 type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
32: jif=fffef462 type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
33: jif=fffef462 type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
34: jif=fffef462 type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
35: jif=fffef462 type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
36: jif=fffef462 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
37: jif=fffef462 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
38: jif=fffef462 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
39: jif=fffef462 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
40: jif=fffef462 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
41: jif=fffef462 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
42: jif=fffef462 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
43: jif=fffef462 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
44: jif=fffef462 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
45: jif=fffef462 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
46: jif=fffef462 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
47: jif=fffef462 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
48: jif=fffef462 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
49: jif=fffef462 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
50: jif=fffef462 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
51: jif=fffef462 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
52: jif=fffef462 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
53: jif=fffef462 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
54: jif=fffef462 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
55: jif=fffef462 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
56: jif=fffef462 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
57: jif=fffef462 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
58: jif=fffef462 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
59: jif=fffef462 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
60: jif=fffef462 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
61: jif=fffef462 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
62: jif=fffef462 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
63: jif=fffef462 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
serial8250: too much work for irq3
serial8250: port c047d374(1) head=c047d408 end=c047d408
0: jif=fffef462 type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
1: jif=fffef462 type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
2: jif=fffef462 type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
3: jif=fffef462 type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
4: jif=fffef462 type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
5: jif=fffef462 type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
6: jif=fffef462 type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
7: jif=fffef462 type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
8: jif=fffef462 type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
9: jif=fffef462 type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
10: jif=fffef462 type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
11: jif=fffef462 type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
12: jif=fffef462 type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
13: jif=fffef462 type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
14: jif=fffef462 type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
15: jif=fffef462 type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
16: jif=fffef462 type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
17: jif=fffef462 type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
18: jif=fffef462 type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
19: jif=fffef462 type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
20: jif=fffef462 type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
21: jif=fffef462 type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
22: jif=fffef462 type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
23: jif=fffef462 type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
24: jif=fffef462 type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
25: jif=fffef462 type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
26: jif=fffef462 type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
27: jif=fffef462 type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
28: jif=fffef4ca type=01 num=00 iir=c2 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=00000000 ee=00000000
29: jif=fffef4ca type=00 num=01 iir=c1 lsr=00 => iir=c1 lsr=00 l=c047d408 eb=00000000 ee=c047d408
30: jif=fffef509 type=00 num=00 iir=c1 lsr=00 => iir=c1 lsr=00 l=c047d408 eb=00000000 ee=c047d408
31: jif=fffef509 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
32: jif=fffef509 type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
33: jif=fffef509 type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
34: jif=fffef509 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
35: jif=fffef509 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
36: jif=fffef509 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
37: jif=fffef509 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
38: jif=fffef509 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
39: jif=fffef509 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
40: jif=fffef509 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
41: jif=fffef509 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
42: jif=fffef509 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
43: jif=fffef509 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
44: jif=fffef509 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
45: jif=fffef509 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
46: jif=fffef509 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
47: jif=fffef509 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
48: jif=fffef509 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
49: jif=fffef509 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
50: jif=fffef509 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
51: jif=fffef509 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
52: jif=fffef509 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
53: jif=fffef509 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
54: jif=fffef509 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
55: jif=fffef509 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
56: jif=fffef509 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
57: jif=fffef509 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
58: jif=fffef509 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
59: jif=fffef509 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
60: jif=fffef509 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
61: jif=fffef509 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
62: jif=fffef509 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
63: jif=fffef509 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
serial8250: too much work for irq3
serial8250: port c047d374(1) head=c047d408 end=c047d408
0: jif=fffef509 type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
1: jif=fffef509 type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
2: jif=fffef509 type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
3: jif=fffef509 type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
4: jif=fffef509 type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
5: jif=fffef509 type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
6: jif=fffef509 type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
7: jif=fffef509 type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
8: jif=fffef509 type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
9: jif=fffef509 type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
10: jif=fffef509 type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
11: jif=fffef509 type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
12: jif=fffef509 type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
13: jif=fffef509 type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
14: jif=fffef509 type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
15: jif=fffef509 type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
16: jif=fffef509 type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
17: jif=fffef509 type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
18: jif=fffef509 type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
19: jif=fffef509 type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
20: jif=fffef509 type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
21: jif=fffef509 type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
22: jif=fffef509 type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
23: jif=fffef509 type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
24: jif=fffef509 type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
25: jif=fffef509 type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
26: jif=fffef509 type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
27: jif=fffef509 type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
28: jif=fffef509 type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
29: jif=fffef509 type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
30: jif=fffef50a type=00 num=00 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=00000000 ee=c047d408
31: jif=fffef50a type=00 num=01 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
32: jif=fffef50a type=00 num=02 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
33: jif=fffef50a type=00 num=03 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
34: jif=fffef50a type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
35: jif=fffef50a type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
36: jif=fffef50a type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
37: jif=fffef50a type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
38: jif=fffef50a type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
39: jif=fffef50a type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
40: jif=fffef50a type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
41: jif=fffef50a type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
42: jif=fffef50a type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
43: jif=fffef50a type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
44: jif=fffef50a type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
45: jif=fffef50a type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
46: jif=fffef50a type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
47: jif=fffef50a type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
48: jif=fffef50a type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
49: jif=fffef50a type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
50: jif=fffef50a type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
51: jif=fffef50a type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
52: jif=fffef50a type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
53: jif=fffef50a type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
54: jif=fffef50a type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
55: jif=fffef50a type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
56: jif=fffef50a type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
57: jif=fffef50a type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
58: jif=fffef50a type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
59: jif=fffef50a type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
60: jif=fffef50a type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
61: jif=fffef50a type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
62: jif=fffef50a type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
63: jif=fffef50a type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
serial8250: too much work for irq3
serial8250: port c047d374(1) head=c047d408 end=c047d408
0: jif=fffef50a type=00 num=04 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
1: jif=fffef50a type=00 num=05 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
2: jif=fffef50a type=00 num=06 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
3: jif=fffef50a type=00 num=07 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
4: jif=fffef50a type=00 num=08 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
5: jif=fffef50a type=00 num=09 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
6: jif=fffef50a type=00 num=0a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
7: jif=fffef50a type=00 num=0b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
8: jif=fffef50a type=00 num=0c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
9: jif=fffef50a type=00 num=0d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
10: jif=fffef50a type=00 num=0e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
11: jif=fffef50a type=00 num=0f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
12: jif=fffef50a type=00 num=10 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
13: jif=fffef50a type=00 num=11 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
14: jif=fffef50a type=00 num=12 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
15: jif=fffef50a type=00 num=13 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
16: jif=fffef50a type=00 num=14 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
17: jif=fffef50a type=00 num=15 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
18: jif=fffef50a type=00 num=16 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
19: jif=fffef50a type=00 num=17 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
20: jif=fffef50a type=00 num=18 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
21: jif=fffef50a type=00 num=19 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
22: jif=fffef50a type=00 num=1a iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
23: jif=fffef50a type=00 num=1b iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
24: jif=fffef50a type=00 num=1c iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
25: jif=fffef50a type=00 num=1d iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
26: jif=fffef50a type=00 num=1e iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
27: jif=fffef50a type=00 num=1f iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
28: jif=fffef50a type=00 num=20 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
29: jif=fffef50a type=00 num=21 iir=01 lsr=60 => iir=01 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
30: jif=fffef50b type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=00000000 ee=c047d408
31: jif=fffef50b type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
32: jif=fffef50b type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
33: jif=fffef50b type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
34: jif=fffef50b type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
35: jif=fffef50b type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
36: jif=fffef50b type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
37: jif=fffef50b type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
38: jif=fffef50b type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
39: jif=fffef50b type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
40: jif=fffef50b type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
41: jif=fffef50b type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
42: jif=fffef50b type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
43: jif=fffef50b type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
44: jif=fffef50b type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
45: jif=fffef50b type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
46: jif=fffef50b type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
47: jif=fffef50b type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
48: jif=fffef50b type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
49: jif=fffef50b type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
50: jif=fffef50b type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
51: jif=fffef50b type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
52: jif=fffef50b type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
53: jif=fffef50b type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
54: jif=fffef50b type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
55: jif=fffef50b type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
56: jif=fffef50b type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
57: jif=fffef50b type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
58: jif=fffef50b type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
59: jif=fffef50b type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
60: jif=fffef50b type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
61: jif=fffef50b type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
62: jif=fffef50b type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
63: jif=fffef50b type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047d408 eb=c047d408 ee=c047d408
e100: eth0: e100_watchdog: link up, 100Mbps, full-duplex
NET: Registered protocol family 10
lo: Disabled Privacy Extensions
IPv6 over IPv4 tunneling driver
lp0: ECP mode
lp0: ECP mode
lp0: ECP mode
NFSD: Using /var/lib/nfs/v4recovery as the NFSv4 state recovery directory
NFSD: recovery directory /var/lib/nfs/v4recovery doesn't exist
NFSD: starting 90-second grace period
eth0: no IPv6 routers present
ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 11
ACPI: PCI Interrupt 0000:02:00.0[A] -> Link [LNKA] -> GSI 11 (level, low) -> IRQ 11
[drm] Initialized r128 2.5.0 20030725 on minor 0:
agpgart: Found an AGP 2.0 compliant device at 0000:00:00.0.
agpgart: Putting AGP V2 device at 0000:00:00.0 into 2x mode
agpgart: Putting AGP V2 device at 0000:02:00.0 into 2x mode
serial8250: too much work for irq4
serial8250: port c047ccc0(0) head=c047cd54 end=c047cd54
0: jif=ffff63d3 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
1: jif=ffff63d3 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
2: jif=ffff63d5 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
3: jif=ffff63d5 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
4: jif=ffff63d7 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
5: jif=ffff63d7 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
6: jif=ffff63d9 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
7: jif=ffff63d9 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
8: jif=ffff63db type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
9: jif=ffff63db type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
10: jif=ffff63dd type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
11: jif=ffff63dd type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
12: jif=ffff63df type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
13: jif=ffff63df type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
14: jif=ffff63e2 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
15: jif=ffff63e2 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
16: jif=ffff63e4 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
17: jif=ffff63e4 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
18: jif=ffff63e6 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
19: jif=ffff63e6 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
20: jif=ffff63e8 type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
21: jif=ffff63e8 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
22: jif=ffff63ea type=01 num=00 iir=c4 lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
23: jif=ffff63ea type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
24: jif=ffff63ec type=01 num=00 iir=cc lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
25: jif=ffff63ec type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
26: jif=ffff6445 type=01 num=00 iir=c2 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
27: jif=ffff6445 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
28: jif=ffff6447 type=01 num=00 iir=cc lsr=61 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=00000000
29: jif=ffff6447 type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
30: jif=ffff694e type=00 num=00 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=00000000 ee=c047cd54
31: jif=ffff694e type=00 num=01 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
32: jif=ffff694e type=00 num=02 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
33: jif=ffff694e type=00 num=03 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
34: jif=ffff694e type=00 num=04 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
35: jif=ffff694e type=00 num=05 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
36: jif=ffff694e type=00 num=06 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
37: jif=ffff694e type=00 num=07 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
38: jif=ffff694e type=00 num=08 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
39: jif=ffff694e type=00 num=09 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
40: jif=ffff694e type=00 num=0a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
41: jif=ffff694e type=00 num=0b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
42: jif=ffff694e type=00 num=0c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
43: jif=ffff694e type=00 num=0d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
44: jif=ffff694e type=00 num=0e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
45: jif=ffff694e type=00 num=0f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
46: jif=ffff694e type=00 num=10 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
47: jif=ffff694e type=00 num=11 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
48: jif=ffff694e type=00 num=12 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
49: jif=ffff694e type=00 num=13 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
50: jif=ffff694e type=00 num=14 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
51: jif=ffff694e type=00 num=15 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
52: jif=ffff694e type=00 num=16 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
53: jif=ffff694e type=00 num=17 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
54: jif=ffff694e type=00 num=18 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
55: jif=ffff694e type=00 num=19 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
56: jif=ffff694e type=00 num=1a iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
57: jif=ffff694e type=00 num=1b iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
58: jif=ffff694e type=00 num=1c iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
59: jif=ffff694e type=00 num=1d iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
60: jif=ffff694e type=00 num=1e iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
61: jif=ffff694e type=00 num=1f iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
62: jif=ffff694e type=00 num=20 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
63: jif=ffff694e type=00 num=21 iir=c1 lsr=60 => iir=c1 lsr=60 l=c047cd54 eb=c047cd54 ee=c047cd54
--
Meelis Roos ([email protected])
On Fri, Dec 23, 2005 at 12:05:35PM +0200, Meelis Roos wrote:
> >Ok, please apply this patch on top of the previous and re-send the
> >kernel messages. This will let us see what's going on with 'l' and
> >'end'.
>
> >+ printk("serial8250: port %p(%d) head=%p end=%p\n", up,
> >up->port.line, i->head, end);
>
> replaced i->heqad with l because i is shadowed by a local variable here,
> now it compiles.
Argh, fek fek fek. The original debug patch contained some extra code
to try to combat a problem I've been seeing here, which is causing more
complaints from your machine.
Right, discard all the patches I sent previously and use this one.
Thanks.
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -69,7 +69,8 @@ static unsigned int share_irqs = SERIAL8
#define DEBUG_INTR(fmt...) do { } while (0)
#endif
-#define PASS_LIMIT 256
+//#define PASS_LIMIT 256
+#define PASS_LIMIT 32
/*
* We default to IRQ0 for the "no irq" hack. Some
@@ -135,6 +136,18 @@ struct uart_8250_port {
*/
void (*pm)(struct uart_port *port,
unsigned int state, unsigned int old);
+
+ struct log {
+ unsigned long jiffies;
+ unsigned char type;
+ unsigned char num;
+ unsigned char unused[2];
+ unsigned char lsr_b;
+ unsigned char iir_b;
+ unsigned char lsr_e;
+ unsigned char iir_e;
+ } log[64];
+ unsigned char log_idx;
};
struct irq_info {
@@ -1284,6 +1297,8 @@ serial8250_handle_port(struct uart_8250_
{
unsigned int status = serial_inp(up, UART_LSR);
+ up->log[up->log_idx].lsr_b = status;
+
DEBUG_INTR("status = %x...", status);
if (status & UART_LSR_DR)
@@ -1291,6 +1306,8 @@ serial8250_handle_port(struct uart_8250_
check_modem_status(up);
if (status & UART_LSR_THRE)
transmit_chars(up);
+
+ up->log[up->log_idx].lsr_e = status;
}
/*
@@ -1325,6 +1342,12 @@ static irqreturn_t serial8250_interrupt(
up = list_entry(l, struct uart_8250_port, list);
iir = serial_in(up, UART_IIR);
+
+ up->log[up->log_idx].jiffies = jiffies;
+ up->log[up->log_idx].type = 0;
+ up->log[up->log_idx].num = pass_counter;
+ up->log[up->log_idx].iir_b = iir;
+
if (!(iir & UART_IIR_NO_INT)) {
spin_lock(&up->port.lock);
serial8250_handle_port(up, regs);
@@ -1336,21 +1359,45 @@ static irqreturn_t serial8250_interrupt(
} else if (end == NULL)
end = l;
+ up->log[up->log_idx].iir_e = serial_in(up, UART_IIR);
+ up->log_idx = (up->log_idx + 1) & 63;
+
l = l->next;
if (l == i->head && pass_counter++ > PASS_LIMIT) {
/* If we hit this, we're dead. */
printk(KERN_ERR "serial8250: too much work for "
"irq%d\n", irq);
- break;
+ goto debug;
}
} while (l != end);
+ out:
spin_unlock(&i->lock);
DEBUG_INTR("end.\n");
return IRQ_RETVAL(handled);
+
+ debug:
+ l = i->head;
+ do {
+ struct uart_8250_port *up = list_entry(l, struct uart_8250_port, list);
+ int j;
+
+ printk("serial8250: port %p(%d)\n", up, up->port.line);
+ for (j = 0; j < 64; j++)
+ printk("%d: jif=%08lx type=%02x num=%02x iir=%02x lsr=%02x => iir=%02x lsr=%02x\n", j,
+ up->log[(up->log_idx + j) & 63].jiffies,
+ up->log[(up->log_idx + j) & 63].type,
+ up->log[(up->log_idx + j) & 63].num,
+ up->log[(up->log_idx + j) & 63].iir_b,
+ up->log[(up->log_idx + j) & 63].lsr_b,
+ up->log[(up->log_idx + j) & 63].iir_e,
+ up->log[(up->log_idx + j) & 63].lsr_e);
+ l = l->next;
+ } while (l != i->head);
+ goto out;
}
/*
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> Right, discard all the patches I sent previously and use this one.
No messages at all so far, with several serial sessions.
--
Meelis Roos ([email protected])
On Tue, Dec 27, 2005 at 03:54:29PM +0200, Meelis Roos wrote:
> >Right, discard all the patches I sent previously and use this one.
>
> No messages at all so far, with several serial sessions.
Can I assume that the bug has disappeared? Does the patch make it
disappear?
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
> Can I assume that the bug has disappeared? Does the patch make it
> disappear?
Yes, seems so.
--
Meelis Roos ([email protected])
On 12/29/05, Meelis Roos <[email protected]> wrote:
> > Can I assume that the bug has disappeared? Does the patch make it
> > disappear?
>
> Yes, seems so.
>
> --
> Meelis Roos ([email protected])
Please notice official linus 2.6.15 tree doesn't have this fix... I've
just installed a virtual machine (qemu-system-i386 with linus 2.6.15 +
plain debian 3r0, console output to xterm via emulated serial console)
and trying to use any curses program (top for example) produces
exactly this type of error.
QEMU_AUDIO_DRV=none \
nice /home/qemu/bin/qemu \
-nographic \
-hda debian-30r0-i386-rootfs.ext2 \
-kernel bzImage-2.6.15 \
-append "console=ttyS0,9600n8 lpj=10000 noapic root=/dev/hda"
I'm now recompiling with this lower limit to test...
--
Greetz, Antonio Vargas aka winden of network
http://wind.codepixel.com/
[email protected]
[email protected]
Every day, every year
you have to work
you have to study
you have to scene.
On Mon, Jan 09, 2006 at 12:24:52AM +0100, Antonio Vargas wrote:
> On 12/29/05, Meelis Roos <[email protected]> wrote:
> > > Can I assume that the bug has disappeared? Does the patch make it
> > > disappear?
> >
> > Yes, seems so.
> >
> > --
> > Meelis Roos ([email protected])
>
> Please notice official linus 2.6.15 tree doesn't have this fix... I've
> just installed a virtual machine (qemu-system-i386 with linus 2.6.15 +
> plain debian 3r0, console output to xterm via emulated serial console)
> and trying to use any curses program (top for example) produces
> exactly this type of error.
That's because the patch just adds debugging seems to be sufficient to
cause the bug to disappear. It isn't a fix.
The only explaination I have at the moment is that it changes the timing
- maybe there's a bug in these UARTs... I don't know at the moment.
What I do know is that Alan's original premise seems wrong.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core