LinuxLists.cc - [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

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Subject: [Patch net-next v2 5/9] net: dsa: microchip: lan937x: add support for configuing xMII register

This patch add the common ksz_set_xmii function for ksz series switch
and update the lan937x code phylink mac config. The register address for
the ksz8795 is Port 5 Interface control 6 and for all other switch is
xMII Control 1.
The bit value for selecting the interface is same for
KSZ8795 and KSZ9893 are same. The bit values for KSZ9477 and lan973x are
same. So, this patch add the bit value for each switches in
ksz_chip_data and configure the registers based on the chip id.

Signed-off-by: Arun Ramadoss <[email protected]>
---
drivers/net/dsa/microchip/ksz_common.c | 44 ++++++++++++++++++++++++
drivers/net/dsa/microchip/ksz_common.h | 8 +++++
drivers/net/dsa/microchip/lan937x_main.c | 32 +----------------
drivers/net/dsa/microchip/lan937x_reg.h | 9 -----
4 files changed, 53 insertions(+), 40 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index bcf61f815e11..39b83b4d02ed 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -292,6 +292,10 @@ static const u8 ksz8795_xmii_ctrl0[] = {
};

static const u8 ksz8795_xmii_ctrl1[] = {
+ [P_RGMII_SEL] = 3,
+ [P_GMII_SEL] = 2,
+ [P_RMII_SEL] = 1,
+ [P_MII_SEL] = 0,
[P_GMII_1GBIT] = 1,
[P_GMII_NOT_1GBIT] = 0,
};
@@ -389,6 +393,10 @@ static const u8 ksz9477_xmii_ctrl0[] = {
};

static const u8 ksz9477_xmii_ctrl1[] = {
+ [P_RGMII_SEL] = 0,
+ [P_RMII_SEL] = 1,
+ [P_GMII_SEL] = 2,
+ [P_MII_SEL] = 3,
[P_GMII_1GBIT] = 0,
[P_GMII_NOT_1GBIT] = 1,
};
@@ -1400,6 +1408,42 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
return dev->dev_ops->max_mtu(dev, port);
}

+void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
+{
+ const u8 *bitval = dev->info->xmii_ctrl1;
+ const u16 *regs = dev->info->regs;
+ u8 data8;
+
+ ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
+
+ data8 &= ~P_MII_SEL_M;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_MII:
+ data8 |= bitval[P_MII_SEL];
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ data8 |= bitval[P_RMII_SEL];
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ data8 |= bitval[P_GMII_SEL];
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ data8 |= bitval[P_RGMII_SEL];
+ break;
+ default:
+ dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
+ phy_modes(interface), port);
+ return;
+ }
+
+ /* Write the updated value */
+ ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
+}
+
static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
unsigned int mode,
const struct phylink_link_state *state)
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 71a344afbf1f..24044fc873fd 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -222,6 +222,10 @@ enum ksz_xmii_ctrl0 {
};

enum ksz_xmii_ctrl1 {
+ P_RGMII_SEL,
+ P_RMII_SEL,
+ P_GMII_SEL,
+ P_MII_SEL,
P_GMII_1GBIT,
P_GMII_NOT_1GBIT,
};
@@ -313,6 +317,7 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
bool ksz_get_gbit(struct ksz_device *dev, int port);
void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
+void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
extern const struct ksz_chip_data ksz_switch_chips[];

/* Common register access functions */
@@ -489,6 +494,9 @@ static inline int is_lan937x(struct ksz_device *dev)
#define P_MII_100MBIT_M BIT(4)

#define P_GMII_1GBIT_M BIT(6)
+#define P_RGMII_ID_IG_ENABLE BIT(4)
+#define P_RGMII_ID_EG_ENABLE BIT(3)
+#define P_MII_SEL_M 0x3

/* Regmap tables generation */
#define KSZ_SPI_OP_RD 3
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index a2e648eacd19..d86ffdf976b0 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -315,36 +315,6 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
return 0;
}

-static void lan937x_mac_config(struct ksz_device *dev, int port,
- phy_interface_t interface)
-{
- u8 data8;
-
- ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
-
- /* clear MII selection & set it based on interface later */
- data8 &= ~PORT_MII_SEL_M;
-
- /* configure MAC based on interface */
- switch (interface) {
- case PHY_INTERFACE_MODE_MII:
- ksz_set_gbit(dev, port, false);
- data8 |= PORT_MII_SEL;
- break;
- case PHY_INTERFACE_MODE_RMII:
- ksz_set_gbit(dev, port, false);
- data8 |= PORT_RMII_SEL;
- break;
- default:
- dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
- phy_modes(interface), port);
- return;
- }
-
- /* Write the updated value */
- ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
-}
-
void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config)
{
@@ -370,7 +340,7 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
return;
}

- lan937x_mac_config(dev, port, state->interface);
+ ksz_set_xmii(dev, port, state->interface);
}

int lan937x_setup(struct dsa_switch *ds)
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index d5eb6dc3a739..a6cb3ca22dc3 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -131,19 +131,10 @@
#define REG_PORT_T1_PHY_CTRL_BASE 0x0100

/* 3 - xMII */
-#define REG_PORT_XMII_CTRL_0 0x0300
#define PORT_SGMII_SEL BIT(7)
#define PORT_GRXC_ENABLE BIT(0)

-#define REG_PORT_XMII_CTRL_1 0x0301
#define PORT_MII_SEL_EDGE BIT(5)
-#define PORT_RGMII_ID_IG_ENABLE BIT(4)
-#define PORT_RGMII_ID_EG_ENABLE BIT(3)
-#define PORT_MII_MAC_MODE BIT(2)
-#define PORT_MII_SEL_M 0x3
-#define PORT_RGMII_SEL 0x0
-#define PORT_RMII_SEL 0x1
-#define PORT_MII_SEL 0x2

/* 4 - MAC */
#define REG_PORT_MAC_CTRL_0 0x0400
--
2.36.1

2022-07-24 09:58:51

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Subject: [Patch net-next v2 4/9] net: dsa: microchip: add support for common phylink mac link up

This patch add the support for common phylink mac link up for the ksz
series switch. The register address, bit position and values are
configured based on the chip id to the dev->info structure.

Signed-off-by: Arun Ramadoss <[email protected]>
---
drivers/net/dsa/microchip/ksz_common.c | 20 ++++++++++++++++----
drivers/net/dsa/microchip/ksz_common.h | 3 ---
drivers/net/dsa/microchip/lan937x.h | 4 ----
drivers/net/dsa/microchip/lan937x_main.c | 22 ----------------------
4 files changed, 16 insertions(+), 33 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 28c21f5a285f..bcf61f815e11 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -223,7 +223,6 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.mirror_del = ksz9477_port_mirror_del,
.get_caps = lan937x_phylink_get_caps,
.phylink_mac_config = lan937x_phylink_mac_config,
- .phylink_mac_link_up = lan937x_phylink_mac_link_up,
.fdb_dump = ksz9477_fdb_dump,
.fdb_add = ksz9477_fdb_add,
.fdb_del = ksz9477_fdb_del,
@@ -1467,7 +1466,7 @@ static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
}

-void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
+static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
{
if (speed == SPEED_1000)
ksz_set_gbit(dev, port, true);
@@ -1478,8 +1477,8 @@ void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
ksz_set_100_10mbit(dev, port, speed);
}

-void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
- bool tx_pause, bool rx_pause)
+static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
+ bool tx_pause, bool rx_pause)
{
const u8 *bitval = dev->info->xmii_ctrl0;
const u32 *masks = dev->info->masks;
@@ -1511,6 +1510,19 @@ static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
int duplex, bool tx_pause, bool rx_pause)
{
struct ksz_device *dev = ds->priv;
+ struct ksz_port *p;
+
+ p = &dev->ports[port];
+
+ /* Internal PHYs */
+ if (dev->info->internal_phy[port])
+ return;
+
+ p->phydev.speed = speed;
+
+ ksz_port_set_xmii_speed(dev, port, speed);
+
+ ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);

if (dev->dev_ops->phylink_mac_link_up)
dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 3577fa2c5eab..71a344afbf1f 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -313,9 +313,6 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
bool ksz_get_gbit(struct ksz_device *dev, int port);
void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
-void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed);
-void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
- bool tx_pause, bool rx_pause);
extern const struct ksz_chip_data ksz_switch_chips[];

/* Common register access functions */
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 72ba9cb2fbc6..0ae553a9b9af 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -17,10 +17,6 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu);
void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config);
-void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
- unsigned int mode, phy_interface_t interface,
- struct phy_device *phydev, int speed,
- int duplex, bool tx_pause, bool rx_pause);
void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
unsigned int mode,
const struct phylink_link_state *state);
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 450ad059d93c..a2e648eacd19 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -345,15 +345,6 @@ static void lan937x_mac_config(struct ksz_device *dev, int port,
ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
}

-static void lan937x_config_interface(struct ksz_device *dev, int port,
- int speed, int duplex,
- bool tx_pause, bool rx_pause)
-{
- ksz_port_set_xmii_speed(dev, port, speed);
-
- ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
-}
-
void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config)
{
@@ -366,19 +357,6 @@ void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
}
}

-void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
- unsigned int mode, phy_interface_t interface,
- struct phy_device *phydev, int speed,
- int duplex, bool tx_pause, bool rx_pause)
-{
- /* Internal PHYs */
- if (dev->info->internal_phy[port])
- return;
-
- lan937x_config_interface(dev, port, speed, duplex,
- tx_pause, rx_pause);
-}
-
void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
unsigned int mode,
const struct phylink_link_state *state)
--
2.36.1

2022-07-24 09:59:39

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Subject: [Patch net-next v2 9/9] net: dsa: microchip: add support for phylink mac config

This patch add support for phylink mac config for ksz series of
switches. All the files ksz8795, ksz9477 and lan937x uses the ksz common
xmii function. Instead of calling from the individual files, it is moved
to the ksz common phylink mac config function.

Signed-off-by: Arun Ramadoss <[email protected]>
---
drivers/net/dsa/microchip/ksz8795.c | 7 -------
drivers/net/dsa/microchip/ksz9477.c | 4 ----
drivers/net/dsa/microchip/ksz_common.c | 18 ++++++++++++++++--
drivers/net/dsa/microchip/ksz_common.h | 6 +++++-
drivers/net/dsa/microchip/lan937x.h | 3 ---
drivers/net/dsa/microchip/lan937x_main.c | 16 ----------------
6 files changed, 21 insertions(+), 33 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
index 8f807d8eace5..c79a5128235f 100644
--- a/drivers/net/dsa/microchip/ksz8795.c
+++ b/drivers/net/dsa/microchip/ksz8795.c
@@ -26,11 +26,6 @@
#include "ksz8795_reg.h"
#include "ksz8.h"

-static bool ksz_is_ksz88x3(struct ksz_device *dev)
-{
- return dev->chip_id == 0x8830;
-}
-
static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
{
regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
@@ -1124,8 +1119,6 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
port);
p->interface = dev->compat_interface;
}
-
- ksz_set_xmii(dev, port, p->interface);
}

void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index 301283d1ba82..4b14d80d27ed 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -944,7 +944,6 @@ void ksz9477_get_caps(struct ksz_device *dev, int port,

void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
{
- struct ksz_port *p = &dev->ports[port];
struct dsa_switch *ds = dev->ds;
u16 data16;
u8 member;
@@ -987,9 +986,6 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
true);
-
- /* configure MAC to 1G & RGMII mode */
- ksz_set_xmii(dev, port, p->interface);
}

if (cpu_port)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 86a2a40cacb4..ed7d137cba99 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -222,7 +222,6 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.mirror_add = ksz9477_port_mirror_add,
.mirror_del = ksz9477_port_mirror_del,
.get_caps = lan937x_phylink_get_caps,
- .phylink_mac_config = lan937x_phylink_mac_config,
.setup_rgmii_delay = lan937x_setup_rgmii_delay,
.fdb_dump = ksz9477_fdb_dump,
.fdb_add = ksz9477_fdb_add,
@@ -1409,7 +1408,8 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
return dev->dev_ops->max_mtu(dev, port);
}

-void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
+static void ksz_set_xmii(struct ksz_device *dev, int port,
+ phy_interface_t interface)
{
const u8 *bitval = dev->info->xmii_ctrl1;
struct ksz_port *p = &dev->ports[port];
@@ -1495,6 +1495,20 @@ static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
{
struct ksz_device *dev = ds->priv;

+ if (ksz_is_ksz88x3(dev))
+ return;
+
+ /* Internal PHYs */
+ if (dev->info->internal_phy[port])
+ return;
+
+ if (phylink_autoneg_inband(mode)) {
+ dev_err(dev->dev, "In-band AN not supported!\n");
+ return;
+ }
+
+ ksz_set_xmii(dev, port, state->interface);
+
if (dev->dev_ops->phylink_mac_config)
dev->dev_ops->phylink_mac_config(dev, port, mode, state);

diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 0b5c565d1ff4..764ada3a0f42 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -319,7 +319,6 @@ void ksz_init_mib_timer(struct ksz_device *dev);
void ksz_r_mib_stats64(struct ksz_device *dev, int port);
void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
bool ksz_get_gbit(struct ksz_device *dev, int port);
-void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
extern const struct ksz_chip_data ksz_switch_chips[];

@@ -447,6 +446,11 @@ static inline void ksz_regmap_unlock(void *__mtx)
mutex_unlock(mtx);
}

+static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
+{
+ return dev->chip_id == KSZ8830_CHIP_ID;
+}
+
static inline int is_lan937x(struct ksz_device *dev)
{
return dev->chip_id == LAN9370_CHIP_ID ||
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 423521a13c9e..4e0b1dccec27 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -17,8 +17,5 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu);
void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config);
-void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
- unsigned int mode,
- const struct phylink_link_state *state);
void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port);
#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 797fe7f62394..daedd2bf20c1 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -383,22 +383,6 @@ void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port)
}
}

-void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
- unsigned int mode,
- const struct phylink_link_state *state)
-{
- /* Internal PHYs */
- if (dev->info->internal_phy[port])
- return;
-
- if (phylink_autoneg_inband(mode)) {
- dev_err(dev->dev, "In-band AN not supported!\n");
- return;
- }
-
- ksz_set_xmii(dev, port, state->interface);
-}
-
int lan937x_setup(struct dsa_switch *ds)
{
struct ksz_device *dev = ds->priv;
--
2.36.1

2022-07-24 10:00:13

[permalink] [raw]

Subject: [Patch net-next v2 8/9] net: dsa: microchip: ksz8795: use common xmii function

This patch updates the ksz8795 cpu configuration to use the ksz common
xmii set functions.

Signed-off-by: Arun Ramadoss <[email protected]>
---
drivers/net/dsa/microchip/ksz8795.c | 35 +------------------------
drivers/net/dsa/microchip/ksz8795_reg.h | 8 ------
2 files changed, 1 insertion(+), 42 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
index 911aace42284..8f807d8eace5 100644
--- a/drivers/net/dsa/microchip/ksz8795.c
+++ b/drivers/net/dsa/microchip/ksz8795.c
@@ -1116,7 +1116,6 @@ void ksz8_port_mirror_del(struct ksz_device *dev, int port,
static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
{
struct ksz_port *p = &dev->ports[port];
- u8 data8;

if (!p->interface && dev->compat_interface) {
dev_warn(dev->dev,
@@ -1126,39 +1125,7 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
p->interface = dev->compat_interface;
}

- /* Configure MII interface for proper network communication. */
- ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
- data8 &= ~PORT_INTERFACE_TYPE;
- data8 &= ~PORT_GMII_1GPS_MODE;
- switch (p->interface) {
- case PHY_INTERFACE_MODE_MII:
- p->phydev.speed = SPEED_100;
- break;
- case PHY_INTERFACE_MODE_RMII:
- data8 |= PORT_INTERFACE_RMII;
- p->phydev.speed = SPEED_100;
- break;
- case PHY_INTERFACE_MODE_GMII:
- data8 |= PORT_GMII_1GPS_MODE;
- data8 |= PORT_INTERFACE_GMII;
- p->phydev.speed = SPEED_1000;
- break;
- default:
- data8 &= ~PORT_RGMII_ID_IN_ENABLE;
- data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
- if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
- p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
- data8 |= PORT_RGMII_ID_IN_ENABLE;
- if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
- p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
- data8 |= PORT_RGMII_ID_OUT_ENABLE;
- data8 |= PORT_GMII_1GPS_MODE;
- data8 |= PORT_INTERFACE_RGMII;
- p->phydev.speed = SPEED_1000;
- break;
- }
- ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
- p->phydev.duplex = 1;
+ ksz_set_xmii(dev, port, p->interface);
}

void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
diff --git a/drivers/net/dsa/microchip/ksz8795_reg.h b/drivers/net/dsa/microchip/ksz8795_reg.h
index a848eb4c54cb..77487d611824 100644
--- a/drivers/net/dsa/microchip/ksz8795_reg.h
+++ b/drivers/net/dsa/microchip/ksz8795_reg.h
@@ -170,15 +170,7 @@
#define REG_PORT_5_CTRL_6 0x56

#define PORT_MII_INTERNAL_CLOCK BIT(7)
-#define PORT_GMII_1GPS_MODE BIT(6)
-#define PORT_RGMII_ID_IN_ENABLE BIT(4)
-#define PORT_RGMII_ID_OUT_ENABLE BIT(3)
#define PORT_GMII_MAC_MODE BIT(2)
-#define PORT_INTERFACE_TYPE 0x3
-#define PORT_INTERFACE_MII 0
-#define PORT_INTERFACE_RMII 1
-#define PORT_INTERFACE_GMII 2
-#define PORT_INTERFACE_RGMII 3

#define REG_PORT_1_CTRL_7 0x17
#define REG_PORT_2_CTRL_7 0x27
--
2.36.1

2022-07-24 21:56:21

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Sun, Jul 24, 2022 at 02:58:14PM +0530, Arun Ramadoss wrote:
> This patch series add support common phylink mac config and link up for the ksz
> series switches. At present, ksz8795 and ksz9477 doesn't implement the phylink
> mac config and link up. It configures the mac interface in the port setup hook.
> ksz8830 series switch does not mac link configuration. For lan937x switches, in
> the part support patch series has support only for MII and RMII configuration.
> Some group of switches have some register address and bit fields common and
> others are different. So, this patch aims to have common phylink implementation
> which configures the register based on the chip id.

I don't see something problematic with this patch set.

Reviewed-by: Vladimir Oltean <[email protected]>

>
> Changes in v2
> - combined the modification of duplex, tx_pause and rx_pause into single
> function.
>
> Changes in v1
> - Squash the reading rgmii value from dt to patch which apply the rgmii value
> - Created the new function ksz_port_set_xmii_speed
> - Seperated the namespace values for xmii_ctrl_0 and xmii_ctrl_1 register
> - Applied the rgmii delay value based on the rx/tx-internal-delay-ps
>
> Arun Ramadoss (9):
> net: dsa: microchip: add common gigabit set and get function
> net: dsa: microchip: add common ksz port xmii speed selection function
> net: dsa: microchip: add common duplex and flow control function
> net: dsa: microchip: add support for common phylink mac link up
> net: dsa: microchip: lan937x: add support for configuing xMII register
> net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config
> net: dsa: microchip: ksz9477: use common xmii function
> net: dsa: microchip: ksz8795: use common xmii function
> net: dsa: microchip: add support for phylink mac config
>
> drivers/net/dsa/microchip/ksz8795.c | 40 ---
> drivers/net/dsa/microchip/ksz8795_reg.h | 8 -
> drivers/net/dsa/microchip/ksz9477.c | 183 +------------
> drivers/net/dsa/microchip/ksz9477_reg.h | 24 --
> drivers/net/dsa/microchip/ksz_common.c | 312 ++++++++++++++++++++++-
> drivers/net/dsa/microchip/ksz_common.h | 54 ++++
> drivers/net/dsa/microchip/lan937x.h | 8 +-
> drivers/net/dsa/microchip/lan937x_main.c | 125 +++------
> drivers/net/dsa/microchip/lan937x_reg.h | 32 ++-
> 9 files changed, 431 insertions(+), 355 deletions(-)
>
>
> base-commit: 502c6f8cedcce7889ccdefeb88ce36b39acd522f
> --
> 2.36.1
>

2022-07-27 08:53:18

by patchwork-bot+netdevbpf

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

Hello:

This series was applied to netdev/net-next.git (master)
by David S. Miller <[email protected]>:

On Sun, 24 Jul 2022 14:58:14 +0530 you wrote:
> This patch series add support common phylink mac config and link up for the ksz
> series switches. At present, ksz8795 and ksz9477 doesn't implement the phylink
> mac config and link up. It configures the mac interface in the port setup hook.
> ksz8830 series switch does not mac link configuration. For lan937x switches, in
> the part support patch series has support only for MII and RMII configuration.
> Some group of switches have some register address and bit fields common and
> others are different. So, this patch aims to have common phylink implementation
> which configures the register based on the chip id.
>
> [...]

Here is the summary with links:
- [net-next,v2,1/9] net: dsa: microchip: add common gigabit set and get function
https://git.kernel.org/netdev/net-next/c/46f80fa8981b
- [net-next,v2,2/9] net: dsa: microchip: add common ksz port xmii speed selection function
https://git.kernel.org/netdev/net-next/c/aa5b8b73d4bd
- [net-next,v2,3/9] net: dsa: microchip: add common duplex and flow control function
https://git.kernel.org/netdev/net-next/c/8560664fd32a
- [net-next,v2,4/9] net: dsa: microchip: add support for common phylink mac link up
https://git.kernel.org/netdev/net-next/c/da8cd08520f3
- [net-next,v2,5/9] net: dsa: microchip: lan937x: add support for configuing xMII register
https://git.kernel.org/netdev/net-next/c/dc1c596edba5
- [net-next,v2,6/9] net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config
https://git.kernel.org/netdev/net-next/c/b19ac41faa3f
- [net-next,v2,7/9] net: dsa: microchip: ksz9477: use common xmii function
https://git.kernel.org/netdev/net-next/c/0ab7f6bf1675
- [net-next,v2,8/9] net: dsa: microchip: ksz8795: use common xmii function
https://git.kernel.org/netdev/net-next/c/c476bede4b0f
- [net-next,v2,9/9] net: dsa: microchip: add support for phylink mac config
https://git.kernel.org/netdev/net-next/c/f3d890f5f90e

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

2022-08-30 07:05:00

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

Hi Arun,

starting with this patch set I have following regression on ksz8873
switch. Can you please take a look at it:
8<--- cut here ---
Unable to handle kernel NULL pointer dereference at virtual address 00000005
ksz8863-switch gpio-0:00: nonfatal error -34 setting MTU to 1500 on port 0
...
Modules linked in:
CPU: 0 PID: 16 Comm: kworker/0:1 Not tainted 6.0.0-rc2-00436-g3da285df1324 #74
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
Workqueue: events_power_efficient phylink_resolve
PC is at ksz_set_gbit+0x5c/0xa4
LR is at arch_atomic_cmpxchg_relaxed+0x1c/0x38
....
Backtrace:
ksz_set_gbit from ksz_phylink_mac_link_up+0x15c/0x1c8
ksz_phylink_mac_link_up from dsa_port_phylink_mac_link_up+0x7c/0x80
dsa_port_phylink_mac_link_up from phylink_resolve+0x304/0x3d0
phylink_resolve from process_one_work+0x214/0x31c
process_one_work from worker_thread+0x254/0x2d4
worker_thread from kthread+0xfc/0x108
kthread from ret_from_fork+0x14/0x2c
...
ksz8863-switch gpio-0:00 lan2 (uninitialized): PHY [dsa-0.0:01] driver [Micrel KSZ8851 Ethernet MAC or KSZ886X Switch] (irq=POLL)
ksz8863-switch gpio-0:00: nonfatal error -34 setting MTU to 1500 on port 1
device eth0 entered promiscuous mode
DSA: tree 0 setup
---[ end trace 0000000000000000 ]---

Regards,
Oleksij

On Sun, Jul 24, 2022 at 02:58:14PM +0530, Arun Ramadoss wrote:
> This patch series add support common phylink mac config and link up for the ksz
> series switches. At present, ksz8795 and ksz9477 doesn't implement the phylink
> mac config and link up. It configures the mac interface in the port setup hook.
> ksz8830 series switch does not mac link configuration. For lan937x switches, in
> the part support patch series has support only for MII and RMII configuration.
> Some group of switches have some register address and bit fields common and
> others are different. So, this patch aims to have common phylink implementation
> which configures the register based on the chip id.

> Changes in v2
> - combined the modification of duplex, tx_pause and rx_pause into single
> function.
>
> Changes in v1
> - Squash the reading rgmii value from dt to patch which apply the rgmii value
> - Created the new function ksz_port_set_xmii_speed
> - Seperated the namespace values for xmii_ctrl_0 and xmii_ctrl_1 register
> - Applied the rgmii delay value based on the rx/tx-internal-delay-ps
>
> Arun Ramadoss (9):
> net: dsa: microchip: add common gigabit set and get function
> net: dsa: microchip: add common ksz port xmii speed selection function
> net: dsa: microchip: add common duplex and flow control function
> net: dsa: microchip: add support for common phylink mac link up
> net: dsa: microchip: lan937x: add support for configuing xMII register
> net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config
> net: dsa: microchip: ksz9477: use common xmii function
> net: dsa: microchip: ksz8795: use common xmii function
> net: dsa: microchip: add support for phylink mac config
>
> drivers/net/dsa/microchip/ksz8795.c | 40 ---
> drivers/net/dsa/microchip/ksz8795_reg.h | 8 -
> drivers/net/dsa/microchip/ksz9477.c | 183 +------------
> drivers/net/dsa/microchip/ksz9477_reg.h | 24 --
> drivers/net/dsa/microchip/ksz_common.c | 312 ++++++++++++++++++++++-
> drivers/net/dsa/microchip/ksz_common.h | 54 ++++
> drivers/net/dsa/microchip/lan937x.h | 8 +-
> drivers/net/dsa/microchip/lan937x_main.c | 125 +++------
> drivers/net/dsa/microchip/lan937x_reg.h | 32 ++-
> 9 files changed, 431 insertions(+), 355 deletions(-)
>
>
> base-commit: 502c6f8cedcce7889ccdefeb88ce36b39acd522f
> --
> 2.36.1
>

--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2022-08-30 09:36:49

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

Hi Oleksij,
Is this Bug related to fix in
https://lore.kernel.org/lkml/[email protected]/
.
It is observed in ksz8794 switch. I think after applying this bug fix
patch it should work. I don't have ksz8 series to test. I ran the
regression only for ksz9 series switches.

On Tue, 2022-08-30 at 08:55 +0200, Oleksij Rempel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hi Arun,
>
> starting with this patch set I have following regression on ksz8873
> switch. Can you please take a look at it:
> 8<--- cut here ---
> Unable to handle kernel NULL pointer dereference at virtual address
> 00000005
> ksz8863-switch gpio-0:00: nonfatal error -34 setting MTU to 1500 on
> port 0
> ...
> Modules linked in:
> CPU: 0 PID: 16 Comm: kworker/0:1 Not tainted 6.0.0-rc2-00436-
> g3da285df1324 #74
> Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> Workqueue: events_power_efficient phylink_resolve
> PC is at ksz_set_gbit+0x5c/0xa4
> LR is at arch_atomic_cmpxchg_relaxed+0x1c/0x38
> ....
> Backtrace:
> ksz_set_gbit from ksz_phylink_mac_link_up+0x15c/0x1c8
> ksz_phylink_mac_link_up from dsa_port_phylink_mac_link_up+0x7c/0x80
> dsa_port_phylink_mac_link_up from phylink_resolve+0x304/0x3d0
> phylink_resolve from process_one_work+0x214/0x31c
> process_one_work from worker_thread+0x254/0x2d4
> worker_thread from kthread+0xfc/0x108
> kthread from ret_from_fork+0x14/0x2c
> ...
> ksz8863-switch gpio-0:00 lan2 (uninitialized): PHY [dsa-0.0:01]
> driver [Micrel KSZ8851 Ethernet MAC or KSZ886X Switch] (irq=POLL)
> ksz8863-switch gpio-0:00: nonfatal error -34 setting MTU to 1500 on
> port 1
> device eth0 entered promiscuous mode
> DSA: tree 0 setup
> ---[ end trace 0000000000000000 ]---
>
> Regards,
> Oleksij
>
> On Sun, Jul 24, 2022 at 02:58:14PM +0530, Arun Ramadoss wrote:
> > This patch series add support common phylink mac config and link up
> > for the ksz
> > series switches. At present, ksz8795 and ksz9477 doesn't implement
> > the phylink
> > mac config and link up. It configures the mac interface in the port
> > setup hook.
> > ksz8830 series switch does not mac link configuration. For lan937x
> > switches, in
> > the part support patch series has support only for MII and RMII
> > configuration.
> > Some group of switches have some register address and bit fields
> > common and
> > others are different. So, this patch aims to have common phylink
> > implementation
> > which configures the register based on the chip id.
> > Changes in v2
> > - combined the modification of duplex, tx_pause and rx_pause into
> > single
> > function.
> >
> > Changes in v1
> > - Squash the reading rgmii value from dt to patch which apply the
> > rgmii value
> > - Created the new function ksz_port_set_xmii_speed
> > - Seperated the namespace values for xmii_ctrl_0 and xmii_ctrl_1
> > register
> > - Applied the rgmii delay value based on the rx/tx-internal-delay-
> > ps
> >
> > Arun Ramadoss (9):
> > net: dsa: microchip: add common gigabit set and get function
> > net: dsa: microchip: add common ksz port xmii speed selection
> > function
> > net: dsa: microchip: add common duplex and flow control function
> > net: dsa: microchip: add support for common phylink mac link up
> > net: dsa: microchip: lan937x: add support for configuing xMII
> > register
> > net: dsa: microchip: apply rgmii tx and rx delay in phylink mac
> > config
> > net: dsa: microchip: ksz9477: use common xmii function
> > net: dsa: microchip: ksz8795: use common xmii function
> > net: dsa: microchip: add support for phylink mac config
> >
> > drivers/net/dsa/microchip/ksz8795.c | 40 ---
> > drivers/net/dsa/microchip/ksz8795_reg.h | 8 -
> > drivers/net/dsa/microchip/ksz9477.c | 183 +------------
> > drivers/net/dsa/microchip/ksz9477_reg.h | 24 --
> > drivers/net/dsa/microchip/ksz_common.c | 312
> > ++++++++++++++++++++++-
> > drivers/net/dsa/microchip/ksz_common.h | 54 ++++
> > drivers/net/dsa/microchip/lan937x.h | 8 +-
> > drivers/net/dsa/microchip/lan937x_main.c | 125 +++------
> > drivers/net/dsa/microchip/lan937x_reg.h | 32 ++-
> > 9 files changed, 431 insertions(+), 355 deletions(-)
> >
> >
> > base-commit: 502c6f8cedcce7889ccdefeb88ce36b39acd522f
> > --
> > 2.36.1
> >
>
> --
> Pengutronix
> e.K. | |
> Steuerwalder Str. 21 |
> http://www.pengutronix.de/e/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-
> 0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-
> 5555 |

2022-08-30 10:03:27

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

Hello,

On Tue, Aug 30, 2022 at 08:15:59AM +0000, [email protected] wrote:
> On Tue, 2022-08-30 at 08:55 +0200, Oleksij Rempel wrote:
> > Hi Arun,
> >
> > starting with this patch set I have following regression on ksz8873
> > switch. Can you please take a look at it:
> > 8<--- cut here ---
> > Unable to handle kernel NULL pointer dereference at virtual address 00000005
> > ksz8863-switch gpio-0:00: nonfatal error -34 setting MTU to 1500 on port 0
> > ...
> > Modules linked in:
> > CPU: 0 PID: 16 Comm: kworker/0:1 Not tainted 6.0.0-rc2-00436-
> > g3da285df1324 #74
> > Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> > Workqueue: events_power_efficient phylink_resolve
> > PC is at ksz_set_gbit+0x5c/0xa4
> > LR is at arch_atomic_cmpxchg_relaxed+0x1c/0x38
> > ....
> > Backtrace:
> > ksz_set_gbit from ksz_phylink_mac_link_up+0x15c/0x1c8
> > ksz_phylink_mac_link_up from dsa_port_phylink_mac_link_up+0x7c/0x80
> > dsa_port_phylink_mac_link_up from phylink_resolve+0x304/0x3d0
> > phylink_resolve from process_one_work+0x214/0x31c
> > process_one_work from worker_thread+0x254/0x2d4
> > worker_thread from kthread+0xfc/0x108
> > kthread from ret_from_fork+0x14/0x2c
> > ...
> > ksz8863-switch gpio-0:00 lan2 (uninitialized): PHY [dsa-0.0:01] driver [Micrel KSZ8851 Ethernet MAC or KSZ886X Switch] (irq=POLL)
> > ksz8863-switch gpio-0:00: nonfatal error -34 setting MTU to 1500 on port 1
> > device eth0 entered promiscuous mode
> > DSA: tree 0 setup
> > ---[ end trace 0000000000000000 ]---
>
> Hi Oleksij,
> Is this Bug related to fix in
> https://lore.kernel.org/lkml/[email protected]/
> .
> It is observed in ksz8794 switch. I think after applying this bug fix
> patch it should work. I don't have ksz8 series to test. I ran the
> regression only for ksz9 series switches.

I find it unlikely that the cited patch will fix a NULL pointer
dereference in ksz_get_gbit(). But rather, some pointer to a structure
is NULL, and we then dereference a member located at its offset 0x5, no?

My eyes are on this:

const u8 *bitval = dev->info->xmii_ctrl1;

data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
~~~~~~~~~~~~~~~~
this is coincidentally
also 5

See, looking at the struct ksz_chip_data[] array element for KSZ8873
that Oleksij mentions as broken, I do not see xmii_ctrl1 and xmii_ctrl2
as being pointers to anything.

[KSZ8830] = {
.chip_id = KSZ8830_CHIP_ID,
.dev_name = "KSZ8863/KSZ8873",
.num_vlans = 16,
.num_alus = 0,
.num_statics = 8,
.cpu_ports = 0x4, /* can be configured as cpu port */
.port_cnt = 3,
.ops = &ksz8_dev_ops,
.mib_names = ksz88xx_mib_names,
.mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz8863_regs,
.masks = ksz8863_masks,
.shifts = ksz8863_shifts,
.supports_mii = {false, false, true},
.supports_rmii = {false, false, true},
.internal_phy = {true, true, false},
},

Should we point them to ksz8795_xmii_ctrl0 and ksz8795_xmii_ctrl1? I don't know.
Could you find out what these should be set to?

2022-08-30 16:21:24

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Tue, Aug 30, 2022 at 12:58:30PM +0300, Vladimir Oltean wrote:
> Hello,
>
> On Tue, Aug 30, 2022 at 08:15:59AM +0000, [email protected] wrote:
...
> > Hi Oleksij,
> > Is this Bug related to fix in
> > https://lore.kernel.org/lkml/[email protected]/
> > .
> > It is observed in ksz8794 switch. I think after applying this bug fix
> > patch it should work. I don't have ksz8 series to test. I ran the
> > regression only for ksz9 series switches.
>
> I find it unlikely that the cited patch will fix a NULL pointer
> dereference in ksz_get_gbit(). But rather, some pointer to a structure
> is NULL, and we then dereference a member located at its offset 0x5, no?
>
> My eyes are on this:
>
> const u8 *bitval = dev->info->xmii_ctrl1;
>
> data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
> ~~~~~~~~~~~~~~~~
> this is coincidentally
> also 5

ack.

> See, looking at the struct ksz_chip_data[] array element for KSZ8873
> that Oleksij mentions as broken, I do not see xmii_ctrl1 and xmii_ctrl2
> as being pointers to anything.
>
> [KSZ8830] = {
> .chip_id = KSZ8830_CHIP_ID,
> .dev_name = "KSZ8863/KSZ8873",
> .num_vlans = 16,
> .num_alus = 0,
> .num_statics = 8,
> .cpu_ports = 0x4, /* can be configured as cpu port */
> .port_cnt = 3,
> .ops = &ksz8_dev_ops,
> .mib_names = ksz88xx_mib_names,
> .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
> .reg_mib_cnt = MIB_COUNTER_NUM,
> .regs = ksz8863_regs,
> .masks = ksz8863_masks,
> .shifts = ksz8863_shifts,
> .supports_mii = {false, false, true},
> .supports_rmii = {false, false, true},
> .internal_phy = {true, true, false},
> },
>
> Should we point them to ksz8795_xmii_ctrl0 and ksz8795_xmii_ctrl1? I don't know.
> Could you find out what these should be set to?

xmii_ctrl0/1 are missing and it make no sense to add it.
KSZ8873 switch is controlling CPU port MII configuration over global,
not port based register.

I'll better define separate ops for this chip.

Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2022-08-31 07:50:35

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Tue, Aug 30, 2022 at 06:05:46PM +0200, Oleksij Rempel wrote:
> On Tue, Aug 30, 2022 at 12:58:30PM +0300, Vladimir Oltean wrote:
> > Hello,
> >
> > On Tue, Aug 30, 2022 at 08:15:59AM +0000, [email protected] wrote:
> ...
> > > Hi Oleksij,
> > > Is this Bug related to fix in
> > > https://lore.kernel.org/lkml/[email protected]/
> > > .
> > > It is observed in ksz8794 switch. I think after applying this bug fix
> > > patch it should work. I don't have ksz8 series to test. I ran the
> > > regression only for ksz9 series switches.
> >
> > I find it unlikely that the cited patch will fix a NULL pointer
> > dereference in ksz_get_gbit(). But rather, some pointer to a structure
> > is NULL, and we then dereference a member located at its offset 0x5, no?
> >
> > My eyes are on this:
> >
> > const u8 *bitval = dev->info->xmii_ctrl1;
> >
> > data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
> > ~~~~~~~~~~~~~~~~
> > this is coincidentally
> > also 5
>
> ack.
>
> > See, looking at the struct ksz_chip_data[] array element for KSZ8873
> > that Oleksij mentions as broken, I do not see xmii_ctrl1 and xmii_ctrl2
> > as being pointers to anything.
> >
> > [KSZ8830] = {
> > .chip_id = KSZ8830_CHIP_ID,
> > .dev_name = "KSZ8863/KSZ8873",
> > .num_vlans = 16,
> > .num_alus = 0,
> > .num_statics = 8,
> > .cpu_ports = 0x4, /* can be configured as cpu port */
> > .port_cnt = 3,
> > .ops = &ksz8_dev_ops,
> > .mib_names = ksz88xx_mib_names,
> > .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
> > .reg_mib_cnt = MIB_COUNTER_NUM,
> > .regs = ksz8863_regs,
> > .masks = ksz8863_masks,
> > .shifts = ksz8863_shifts,
> > .supports_mii = {false, false, true},
> > .supports_rmii = {false, false, true},
> > .internal_phy = {true, true, false},
> > },
> >
> > Should we point them to ksz8795_xmii_ctrl0 and ksz8795_xmii_ctrl1? I don't know.
> > Could you find out what these should be set to?
>
> xmii_ctrl0/1 are missing and it make no sense to add it.
> KSZ8873 switch is controlling CPU port MII configuration over global,
> not port based register.
>
> I'll better define separate ops for this chip.

Hm, not only KSZ8830/KSZ8863/KSZ8873 are affected. ksz8795 compatible
series with defined .xmii_ctrl0/.xmii_ctrl1 are broken too. Because it
is writing to the global config register over ksz_pwrite8 function. It
means, we are writing to 0xa6 instead of 0x06. And to 0xf6 instead of
0x56.

--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2022-08-31 15:42:44

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Wed, Aug 31, 2022 at 09:43:24AM +0200, Oleksij Rempel wrote:
> > > Should we point them to ksz8795_xmii_ctrl0 and ksz8795_xmii_ctrl1? I don't know.
> > > Could you find out what these should be set to?
> >
> > xmii_ctrl0/1 are missing and it make no sense to add it.
> > KSZ8873 switch is controlling CPU port MII configuration over global,
> > not port based register.
> >
> > I'll better define separate ops for this chip.
>
> Hm, not only KSZ8830/KSZ8863/KSZ8873 are affected. ksz8795 compatible
> series with defined .xmii_ctrl0/.xmii_ctrl1 are broken too. Because it
> is writing to the global config register over ksz_pwrite8 function. It
> means, we are writing to 0xa6 instead of 0x06. And to 0xf6 instead of
> 0x56.

What do you mean by "global config register"? The Is_1Gbps bit is still
part of a port register, it's just that this particular register is only
defined for the 5th port (port #4, the only xMII port on KSZ7895 AFAIU).
That doesn't necessarily make it a "global" register.

Datasheet says:

Register 22 (0x16): Reserved
Register 38 (0x26): Reserved
Register 54 (0x36): Reserved
Register 70 (0x46): Reserved
Register 86 (0x56): Port 5 Interface Control 6

I wonder if it's ok to modify the regs table like this, because we
should then only touch P_XMII_CTRL_1 using port 4:

static const u16 ksz8795_regs[] = {
[REG_IND_CTRL_0] = 0x6E,
[REG_IND_DATA_8] = 0x70,
[REG_IND_DATA_CHECK] = 0x72,
[REG_IND_DATA_HI] = 0x71,
[REG_IND_DATA_LO] = 0x75,
[REG_IND_MIB_CHECK] = 0x74,
[REG_IND_BYTE] = 0xA0,
[P_FORCE_CTRL] = 0x0C,
[P_LINK_STATUS] = 0x0E,
[P_LOCAL_CTRL] = 0x07,
[P_NEG_RESTART_CTRL] = 0x0D,
[P_REMOTE_STATUS] = 0x08,
[P_SPEED_STATUS] = 0x09,
[S_TAIL_TAG_CTRL] = 0x0C,
[P_STP_CTRL] = 0x02,
[S_START_CTRL] = 0x01,
[S_BROADCAST_CTRL] = 0x06,
[S_MULTICAST_CTRL] = 0x04,
[P_XMII_CTRL_0] = 0x06,
- [P_XMII_CTRL_1] = 0x56,
+ [P_XMII_CTRL_1] = 0x06,
};

Arun, what is your proposed solution?

2022-08-31 16:18:55

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Wed, Aug 31, 2022 at 06:18:59PM +0300, Vladimir Oltean wrote:
> On Wed, Aug 31, 2022 at 09:43:24AM +0200, Oleksij Rempel wrote:
> > > > Should we point them to ksz8795_xmii_ctrl0 and ksz8795_xmii_ctrl1? I don't know.
> > > > Could you find out what these should be set to?
> > >
> > > xmii_ctrl0/1 are missing and it make no sense to add it.
> > > KSZ8873 switch is controlling CPU port MII configuration over global,
> > > not port based register.
> > >
> > > I'll better define separate ops for this chip.
> >
> > Hm, not only KSZ8830/KSZ8863/KSZ8873 are affected. ksz8795 compatible
> > series with defined .xmii_ctrl0/.xmii_ctrl1 are broken too. Because it
> > is writing to the global config register over ksz_pwrite8 function. It
> > means, we are writing to 0xa6 instead of 0x06. And to 0xf6 instead of
> > 0x56.
>
> What do you mean by "global config register"? The Is_1Gbps bit is still
> part of a port register, it's just that this particular register is only
> defined for the 5th port (port #4, the only xMII port on KSZ7895 AFAIU).
> That doesn't necessarily make it a "global" register.
>
> Datasheet says:
>
> Register 22 (0x16): Reserved
> Register 38 (0x26): Reserved
> Register 54 (0x36): Reserved
> Register 70 (0x46): Reserved
> Register 86 (0x56): Port 5 Interface Control 6
>
> I wonder if it's ok to modify the regs table like this, because we
> should then only touch P_XMII_CTRL_1 using port 4:
>
> static const u16 ksz8795_regs[] = {
> [REG_IND_CTRL_0] = 0x6E,
> [REG_IND_DATA_8] = 0x70,
> [REG_IND_DATA_CHECK] = 0x72,
> [REG_IND_DATA_HI] = 0x71,
> [REG_IND_DATA_LO] = 0x75,
> [REG_IND_MIB_CHECK] = 0x74,
> [REG_IND_BYTE] = 0xA0,
> [P_FORCE_CTRL] = 0x0C,
> [P_LINK_STATUS] = 0x0E,
> [P_LOCAL_CTRL] = 0x07,
> [P_NEG_RESTART_CTRL] = 0x0D,
> [P_REMOTE_STATUS] = 0x08,
> [P_SPEED_STATUS] = 0x09,
> [S_TAIL_TAG_CTRL] = 0x0C,
> [P_STP_CTRL] = 0x02,
> [S_START_CTRL] = 0x01,
> [S_BROADCAST_CTRL] = 0x06,
> [S_MULTICAST_CTRL] = 0x04,
> [P_XMII_CTRL_0] = 0x06,
> - [P_XMII_CTRL_1] = 0x56,
> + [P_XMII_CTRL_1] = 0x06,
> };
>

Speed configuration on ksz8795 is done over two registers:
Register 86 (0x56): Port 5 Interface Control 6: Is_1Gbps - BIT(6)
and
Register 6 (0x06): Global Control 4: Switch SW5-MII/RMII Speed -BIT(4)

both are accessed on wrong offsets.

I would prefer to do following steps:
- remove everything from ksz_phylink_mac_link_up() except of
dev->dev_ops->phylink_mac_link_up
- move ksz_duplex_flowctrl(), ksz_port_set_xmii_speed()... to ksz9477.c
and rename them. Assign ksz9477_phylink_mac_link_up()
dev->dev_ops->phylink_mac_link_up
- create separate function ksz8795_phylink_mac_link_up()
- use documented, not generic register names.

--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2022-09-01 09:35:59

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Wed, 2022-08-31 at 18:10 +0200, Oleksij Rempel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Wed, Aug 31, 2022 at 06:18:59PM +0300, Vladimir Oltean wrote:
> > On Wed, Aug 31, 2022 at 09:43:24AM +0200, Oleksij Rempel wrote:
> > > > > Should we point them to ksz8795_xmii_ctrl0 and
> > > > > ksz8795_xmii_ctrl1? I don't know.
> > > > > Could you find out what these should be set to?
> > > >
> > > > xmii_ctrl0/1 are missing and it make no sense to add it.
> > > > KSZ8873 switch is controlling CPU port MII configuration over
> > > > global,
> > > > not port based register.
> > > >
> > > > I'll better define separate ops for this chip.
> > >
> > > Hm, not only KSZ8830/KSZ8863/KSZ8873 are affected. ksz8795
> > > compatible
> > > series with defined .xmii_ctrl0/.xmii_ctrl1 are broken too.
> > > Because it
> > > is writing to the global config register over ksz_pwrite8
> > > function. It
> > > means, we are writing to 0xa6 instead of 0x06. And to 0xf6
> > > instead of
> > > 0x56.
> > What do you mean by "global config register"? The Is_1Gbps bit is
> > still
> > part of a port register, it's just that this particular register is
> > only
> > defined for the 5th port (port #4, the only xMII port on KSZ7895
> > AFAIU).
> > That doesn't necessarily make it a "global" register.
> >
> > Datasheet says:
> >
> > Register 22 (0x16): Reserved
> > Register 38 (0x26): Reserved
> > Register 54 (0x36): Reserved
> > Register 70 (0x46): Reserved
> > Register 86 (0x56): Port 5 Interface Control 6
> >
> > I wonder if it's ok to modify the regs table like this, because we
> > should then only touch P_XMII_CTRL_1 using port 4:
> >
> > static const u16 ksz8795_regs[] = {
> > [REG_IND_CTRL_0] = 0x6E,
> > [REG_IND_DATA_8] = 0x70,
> > [REG_IND_DATA_CHECK] = 0x72,
> > [REG_IND_DATA_HI] = 0x71,
> > [REG_IND_DATA_LO] = 0x75,
> > [REG_IND_MIB_CHECK] = 0x74,
> > [REG_IND_BYTE] = 0xA0,
> > [P_FORCE_CTRL] = 0x0C,
> > [P_LINK_STATUS] = 0x0E,
> > [P_LOCAL_CTRL] = 0x07,
> > [P_NEG_RESTART_CTRL] = 0x0D,
> > [P_REMOTE_STATUS] = 0x08,
> > [P_SPEED_STATUS] = 0x09,
> > [S_TAIL_TAG_CTRL] = 0x0C,
> > [P_STP_CTRL] = 0x02,
> > [S_START_CTRL] = 0x01,
> > [S_BROADCAST_CTRL] = 0x06,
> > [S_MULTICAST_CTRL] = 0x04,
> > [P_XMII_CTRL_0] = 0x06,
> > - [P_XMII_CTRL_1] = 0x56,
> > + [P_XMII_CTRL_1] = 0x06,
> > };
> >
>
> Speed configuration on ksz8795 is done over two registers:
> Register 86 (0x56): Port 5 Interface Control 6: Is_1Gbps - BIT(6)
> and
> Register 6 (0x06): Global Control 4: Switch SW5-MII/RMII Speed
> -BIT(4)
>
> both are accessed on wrong offsets.
>
> I would prefer to do following steps:
> - remove everything from ksz_phylink_mac_link_up() except of
> dev->dev_ops->phylink_mac_link_up
> - move ksz_duplex_flowctrl(), ksz_port_set_xmii_speed()... to
> ksz9477.c
> and rename them. Assign ksz9477_phylink_mac_link_up()
> dev->dev_ops->phylink_mac_link_up
> - create separate function ksz8795_phylink_mac_link_up()
> - use documented, not generic register names.
>

In the original code, the ksz8795_cpu_interface_select (which does the
xmii and speed configuration) is called only ksz87xx switch not for the
ksz88x3.
During refactoring, I intentionally did not add the P_XMII_CTRL0/1 for
the ksz88xx in the chip_data structure.
I added check that if switch belong to ksz88x3 then return in the
phylink_mac_config function but I missed to add in the
phylink_mac_link_up. Thats the mistake I have done. So, for the ksz88xx
switch code breakage, it could be fixed by adding the check in the
phylink_mac_link_up as well.

For the code breakage in ksz8795/ksz8794, the original code has only
provision for configuring xmii mode and choosing the 100/1000Mbps speed
selection which could be selected using is_1Gbps bit of
port5_interface_control6 register (0x56). But it didn't have provision
to select speed between 10/100Mbps, flow control and duplex.

As per vladimir suggestion, P_XMII_CTRL1 can be changed from 0x56 to
0x06. It fixes the problem for ksz_set_xmii, ksz_set_gbit since this is
the port based register not the global register.

The global register 0x06 responsibilities are bit 4 for 10/100mbps
speed selection, bit 5 for flow control and bit 6 for duplex
operation. Since these three are new features added during refactoring
I overlooked it.
To fix this, either I need to return from the ksz_set_100_10mbit &
ksz_duplex_flowctrl function if the chip_id is ksz87xx or add dev-
>dev_ops for this alone.
Kindly suggest on how to proceed.

> --
> Pengutronix
> e.K. | |
> Steuerwalder Str. 21 |
> http://www.pengutronix.de/e/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-
> 0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-
> 5555 |

2022-09-01 11:39:34

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Thu, Sep 01, 2022 at 08:51:44AM +0000, [email protected] wrote:
> On Wed, 2022-08-31 at 18:10 +0200, Oleksij Rempel wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On Wed, Aug 31, 2022 at 06:18:59PM +0300, Vladimir Oltean wrote:
> > > On Wed, Aug 31, 2022 at 09:43:24AM +0200, Oleksij Rempel wrote:
> > > > > > Should we point them to ksz8795_xmii_ctrl0 and
> > > > > > ksz8795_xmii_ctrl1? I don't know.
> > > > > > Could you find out what these should be set to?
> > > > >
> > > > > xmii_ctrl0/1 are missing and it make no sense to add it.
> > > > > KSZ8873 switch is controlling CPU port MII configuration over
> > > > > global,
> > > > > not port based register.
> > > > >
> > > > > I'll better define separate ops for this chip.
> > > >
> > > > Hm, not only KSZ8830/KSZ8863/KSZ8873 are affected. ksz8795
> > > > compatible
> > > > series with defined .xmii_ctrl0/.xmii_ctrl1 are broken too.
> > > > Because it
> > > > is writing to the global config register over ksz_pwrite8
> > > > function. It
> > > > means, we are writing to 0xa6 instead of 0x06. And to 0xf6
> > > > instead of
> > > > 0x56.
> > > What do you mean by "global config register"? The Is_1Gbps bit is
> > > still
> > > part of a port register, it's just that this particular register is
> > > only
> > > defined for the 5th port (port #4, the only xMII port on KSZ7895
> > > AFAIU).
> > > That doesn't necessarily make it a "global" register.
> > >
> > > Datasheet says:
> > >
> > > Register 22 (0x16): Reserved
> > > Register 38 (0x26): Reserved
> > > Register 54 (0x36): Reserved
> > > Register 70 (0x46): Reserved
> > > Register 86 (0x56): Port 5 Interface Control 6
> > >
> > > I wonder if it's ok to modify the regs table like this, because we
> > > should then only touch P_XMII_CTRL_1 using port 4:
> > >
> > > static const u16 ksz8795_regs[] = {
> > > [REG_IND_CTRL_0] = 0x6E,
> > > [REG_IND_DATA_8] = 0x70,
> > > [REG_IND_DATA_CHECK] = 0x72,
> > > [REG_IND_DATA_HI] = 0x71,
> > > [REG_IND_DATA_LO] = 0x75,
> > > [REG_IND_MIB_CHECK] = 0x74,
> > > [REG_IND_BYTE] = 0xA0,
> > > [P_FORCE_CTRL] = 0x0C,
> > > [P_LINK_STATUS] = 0x0E,
> > > [P_LOCAL_CTRL] = 0x07,
> > > [P_NEG_RESTART_CTRL] = 0x0D,
> > > [P_REMOTE_STATUS] = 0x08,
> > > [P_SPEED_STATUS] = 0x09,
> > > [S_TAIL_TAG_CTRL] = 0x0C,
> > > [P_STP_CTRL] = 0x02,
> > > [S_START_CTRL] = 0x01,
> > > [S_BROADCAST_CTRL] = 0x06,
> > > [S_MULTICAST_CTRL] = 0x04,
> > > [P_XMII_CTRL_0] = 0x06,
> > > - [P_XMII_CTRL_1] = 0x56,
> > > + [P_XMII_CTRL_1] = 0x06,
> > > };
> > >
> >
> > Speed configuration on ksz8795 is done over two registers:
> > Register 86 (0x56): Port 5 Interface Control 6: Is_1Gbps - BIT(6)
> > and
> > Register 6 (0x06): Global Control 4: Switch SW5-MII/RMII Speed
> > -BIT(4)
> >
> > both are accessed on wrong offsets.
> >
> > I would prefer to do following steps:
> > - remove everything from ksz_phylink_mac_link_up() except of
> > dev->dev_ops->phylink_mac_link_up
> > - move ksz_duplex_flowctrl(), ksz_port_set_xmii_speed()... to
> > ksz9477.c
> > and rename them. Assign ksz9477_phylink_mac_link_up()
> > dev->dev_ops->phylink_mac_link_up
> > - create separate function ksz8795_phylink_mac_link_up()
> > - use documented, not generic register names.
> >
>
> In the original code, the ksz8795_cpu_interface_select (which does the
> xmii and speed configuration) is called only ksz87xx switch not for the
> ksz88x3.
> During refactoring, I intentionally did not add the P_XMII_CTRL0/1 for
> the ksz88xx in the chip_data structure.
> I added check that if switch belong to ksz88x3 then return in the
> phylink_mac_config function but I missed to add in the
> phylink_mac_link_up. Thats the mistake I have done. So, for the ksz88xx
> switch code breakage, it could be fixed by adding the check in the
> phylink_mac_link_up as well.
>
> For the code breakage in ksz8795/ksz8794, the original code has only
> provision for configuring xmii mode and choosing the 100/1000Mbps speed
> selection which could be selected using is_1Gbps bit of
> port5_interface_control6 register (0x56). But it didn't have provision
> to select speed between 10/100Mbps, flow control and duplex.
>
> As per vladimir suggestion, P_XMII_CTRL1 can be changed from 0x56 to
> 0x06. It fixes the problem for ksz_set_xmii, ksz_set_gbit since this is
> the port based register not the global register.
>
> The global register 0x06 responsibilities are bit 4 for 10/100mbps
> speed selection, bit 5 for flow control and bit 6 for duplex
> operation. Since these three are new features added during refactoring
> I overlooked it.
> To fix this, either I need to return from the ksz_set_100_10mbit &
> ksz_duplex_flowctrl function if the chip_id is ksz87xx or add dev-
> >dev_ops for this alone.
> Kindly suggest on how to proceed.

Do not worry, every one makes mistakes ;)

I just scared how easy it is to make them in this driver. I assume, that
initially the good idea to make things more generic in this driver is
working against us. The register- and bit-mapping functionally is
already biting us:
- it is hard to review, due to different register naming schema for
different switch families. Especially the old ones.
- we are using naming from one documentation to map to other
documentation.
- some times we need to map some registers multiple times with different
names: P_REMOTE_STATUS and P_LINK_STATUS

I would prefer to got ops way, to clean things up.

Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

2022-09-01 12:55:16

[permalink] [raw]

Subject: Re: [Patch net-next v2 0/9] net: dsa: microchip: add support for phylink mac config and link up

On Thu, Sep 01, 2022 at 01:27:21PM +0200, Oleksij Rempel wrote:
> > The global register 0x06 responsibilities are bit 4 for 10/100mbps
> > speed selection, bit 5 for flow control and bit 6 for duplex
> > operation. Since these three are new features added during refactoring
> > I overlooked it.
> > To fix this, either I need to return from the ksz_set_100_10mbit &
> > ksz_duplex_flowctrl function if the chip_id is ksz87xx or add
> > dev->dev_ops for this alone. Kindly suggest on how to proceed.
>
> I would prefer to got ops way, to clean things up.

I can't say that that one approach is better or worse than the other.
Indirect function calls are going to be more expensive than conditionals
on dev->chip_id, but we aren't in a fast path here, so it doesn't matter
too much.

Having indirect function calls will in theory help simplify the logic of
the main function, but will require good forethought for what constitutes
an atom of functionality, in a high enough level such as to abstract
switch differences. Whereas conditionals don't require thinking that far,
you put them where you need them.

Also, indirect function calls will move the bloat somewhere else. I have
seen complaints in the past about the mv88e6xxx driver's layered structure,
making it difficult to see exactly what gets done for a certain chip.

It is probable that we don't want to mix these styles too much within a
single driver, so if work has already started towards dev_ops for
everything, then dev_ops be it, I guess.

Oleksij, are you going to submit patches with your proposal?

2022-09-02 10:09:35