The Rockchip rk3288 SoC has 4-built-in PWM channels.
Configurable to operate in capture mode.
Measures the high/low polarity effective cycles of this input waveform
Generates a single interrupt at the transition of input waveform polarity
Configurable to operate in continuous mode or one-shot mode.
One-shot operation will produce N + 1 periods of the waveform,
where N is the repeat counter value, and generates a single interrupt at
the end of operation.
Continuous mode generates the waveform continuously and
do not generates any interrupts.
Add interrupts property to rk3288 PWM nodes.
Signed-off-by: Caesar Wang <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
---
Original patch location:
ARM: dts: rk3288: add the interrupts property for PWM
https://github.com/rockchip-linux/kernel/commit/16b7b284618d1652e694f6286f575ce82f5f03e5
---
"rockchip,rk3288-pwm" is in use as fall back string for Rockchip SoCs with combined
PWM interrupt.
---
arch/arm/boot/dts/rk3288.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 487b0e03d..1223aa369 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -675,6 +675,7 @@
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -685,6 +686,7 @@
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
@@ -695,6 +697,7 @@
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
@@ -705,6 +708,7 @@
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
--
2.20.1
On 2022-09-29 15:04, Johan Jonker wrote:
> The Rockchip rk3288 SoC has 4-built-in PWM channels.
>
> Configurable to operate in capture mode.
> Measures the high/low polarity effective cycles of this input waveform
> Generates a single interrupt at the transition of input waveform polarity
>
> Configurable to operate in continuous mode or one-shot mode.
> One-shot operation will produce N + 1 periods of the waveform,
> where N is the repeat counter value, and generates a single interrupt at
> the end of operation.
> Continuous mode generates the waveform continuously and
> do not generates any interrupts.
>
> Add interrupts property to rk3288 PWM nodes.
As far as I can make out from the TRM, these are only valid when
GRF_SOC_CON2[0] = 0, otherwise it's in "new" RK_PWM mode using SPI 78
for all channels. Which apparently will be the case for anyone using
upstream U-Boot:
https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-rockchip/rk3288/rk3288.c#L83
Thanks,
Robin.
> Signed-off-by: Caesar Wang <[email protected]>
> Signed-off-by: Johan Jonker <[email protected]>
>
> ---
>
> Original patch location:
> ARM: dts: rk3288: add the interrupts property for PWM
> https://github.com/rockchip-linux/kernel/commit/16b7b284618d1652e694f6286f575ce82f5f03e5
>
> ---
>
> "rockchip,rk3288-pwm" is in use as fall back string for Rockchip SoCs with combined
> PWM interrupt.
> ---
> arch/arm/boot/dts/rk3288.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 487b0e03d..1223aa369 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -675,6 +675,7 @@
> pwm0: pwm@ff680000 {
> compatible = "rockchip,rk3288-pwm";
> reg = <0x0 0xff680000 0x0 0x10>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm0_pin>;
> @@ -685,6 +686,7 @@
> pwm1: pwm@ff680010 {
> compatible = "rockchip,rk3288-pwm";
> reg = <0x0 0xff680010 0x0 0x10>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm1_pin>;
> @@ -695,6 +697,7 @@
> pwm2: pwm@ff680020 {
> compatible = "rockchip,rk3288-pwm";
> reg = <0x0 0xff680020 0x0 0x10>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm2_pin>;
> @@ -705,6 +708,7 @@
> pwm3: pwm@ff680030 {
> compatible = "rockchip,rk3288-pwm";
> reg = <0x0 0xff680030 0x0 0x10>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <&pwm3_pin>;
On Thu, Sep 29, 2022 at 04:04:06PM +0200, Johan Jonker wrote:
> The Rockchip rk3288 SoC has 4-built-in PWM channels.
>
> Configurable to operate in capture mode.
> Measures the high/low polarity effective cycles of this input waveform
> Generates a single interrupt at the transition of input waveform polarity
>
> Configurable to operate in continuous mode or one-shot mode.
> One-shot operation will produce N + 1 periods of the waveform,
> where N is the repeat counter value, and generates a single interrupt at
> the end of operation.
> Continuous mode generates the waveform continuously and
> do not generates any interrupts.
>
> Add interrupts property to rk3288 PWM nodes.
>
> Signed-off-by: Caesar Wang <[email protected]>
> Signed-off-by: Johan Jonker <[email protected]>
>
> ---
Please thread your series properly. That's replies to the cover letter
or patch 1 if there isn't a cover letter. git-send-email does this by
default.
Rob
On Thu, Sep 29, 2022 at 04:50:43PM +0100, Robin Murphy wrote:
> On 2022-09-29 15:04, Johan Jonker wrote:
> > The Rockchip rk3288 SoC has 4-built-in PWM channels.
> >
> > Configurable to operate in capture mode.
> > Measures the high/low polarity effective cycles of this input waveform
> > Generates a single interrupt at the transition of input waveform polarity
> >
> > Configurable to operate in continuous mode or one-shot mode.
> > One-shot operation will produce N + 1 periods of the waveform,
> > where N is the repeat counter value, and generates a single interrupt at
> > the end of operation.
> > Continuous mode generates the waveform continuously and
> > do not generates any interrupts.
> >
> > Add interrupts property to rk3288 PWM nodes.
>
> As far as I can make out from the TRM, these are only valid when
> GRF_SOC_CON2[0] = 0, otherwise it's in "new" RK_PWM mode using SPI 78 for
> all channels. Which apparently will be the case for anyone using upstream
> U-Boot:
>
> https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-rockchip/rk3288/rk3288.c#L83
Huh, so it depends on a (software) setting which irqs are in use? So the
patch isn't correct as is, but I have no idea how to make it right.
Should we rely on the bootloader to fixup the dtb correctly?
Anyhow, I'm marking the patch as 'changes-requested' in our patchwork
instance.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
Am Mittwoch, 19. Oktober 2022, 09:26:21 CEST schrieb Uwe Kleine-K?nig:
> On Thu, Sep 29, 2022 at 04:50:43PM +0100, Robin Murphy wrote:
> > On 2022-09-29 15:04, Johan Jonker wrote:
> > > The Rockchip rk3288 SoC has 4-built-in PWM channels.
> > >
> > > Configurable to operate in capture mode.
> > > Measures the high/low polarity effective cycles of this input waveform
> > > Generates a single interrupt at the transition of input waveform polarity
> > >
> > > Configurable to operate in continuous mode or one-shot mode.
> > > One-shot operation will produce N + 1 periods of the waveform,
> > > where N is the repeat counter value, and generates a single interrupt at
> > > the end of operation.
> > > Continuous mode generates the waveform continuously and
> > > do not generates any interrupts.
> > >
> > > Add interrupts property to rk3288 PWM nodes.
> >
> > As far as I can make out from the TRM, these are only valid when
> > GRF_SOC_CON2[0] = 0, otherwise it's in "new" RK_PWM mode using SPI 78 for
> > all channels. Which apparently will be the case for anyone using upstream
> > U-Boot:
> >
> > https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-rockchip/rk3288/rk3288.c#L83
>
> Huh, so it depends on a (software) setting which irqs are in use?
In the past when Rockchip swapped one IP block for another they often
had both in a soc for one generation (as a safeguard probably)
So the rk3288 has two different pwm implementations and the GRF
register selects which one is active.
Heiko
> So the
> patch isn't correct as is, but I have no idea how to make it right.
> Should we rely on the bootloader to fixup the dtb correctly?
>
> Anyhow, I'm marking the patch as 'changes-requested' in our patchwork
> instance.
>
> Best regards
> Uwe
>
>