IPQ9574 SoC uses the PMIC MP5496 and SMPA1 regulator for APSS voltage scaling.
This patch series adds support for the same and also enables the RPM
communication over the RPMSG framework.
DTS patch depends on the below series
https://lore.kernel.org/linux-arm-msm/[email protected]/
[V3]:
- Dropped PATCH [1/6] dt-bindings: soc: qcom: smd-rpm: Add IPQ9574 compatible
as it is available in linux-next/master
- Dropped PATCH [4/6] regulator: qcom_smd: Add support to define the bootup voltage
and updated the nominal voltage in the Board DT as discussed
- Splitted the board DT changes to a separate patch as suggested
- Detailed change logs are added to the respective patches
[V2]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Reordered the patches to have the bindings and driver changes
in place before the device tree support
- Dropped the 'soc: qcom: smd-rpm: Add IPQ9574 compatible' since
it is already part of the linux-next/master
- Detailed change log is added to the respective patches
[V1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/
Devi Priya (5):
regulator: qcom_smd: Add s1 sub-node to mp5496 regulator
regulator: qcom_smd: Add MP5496 S1 regulator
arm64: dts: qcom: ipq9574: Add RPM related nodes
arm64: dts: qcom: ipq9574: Add SMPA1 regulator node
arm64: dts: qcom: ipq9574: Add cpufreq support
.../regulator/qcom,smd-rpm-regulator.yaml | 2 +-
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 75 +++++++++++++++++++
drivers/regulator/qcom_smd-regulator.c | 10 +++
4 files changed, 105 insertions(+), 1 deletion(-)
base-commit: 8417c8f5007bf4567ccffda850a3157c7d905f67
--
2.17.1
Adding support for MP5496 S1 regulator on IPQ9574 SoC.
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- No change
drivers/regulator/qcom_smd-regulator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c
index 6f722b2d682e..cb77b3bd1723 100644
--- a/drivers/regulator/qcom_smd-regulator.c
+++ b/drivers/regulator/qcom_smd-regulator.c
@@ -749,6 +749,15 @@ static const struct regulator_desc pms405_pldo600 = {
.ops = &rpm_smps_ldo_ops,
};
+static const struct regulator_desc mp5496_smpa1 = {
+ .linear_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
+ },
+ .n_linear_ranges = 1,
+ .n_voltages = 128,
+ .ops = &rpm_mp5496_ops,
+};
+
static const struct regulator_desc mp5496_smpa2 = {
.linear_ranges = (struct linear_range[]) {
REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
@@ -794,6 +803,7 @@ struct rpm_regulator_data {
};
static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
+ { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smpa1, "s1" },
{ "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
{ "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
{}
--
2.17.1
Adding s1 sub-node entry to mp5496 regulator node.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- Picked up the R-b tag
.../devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
index 8c45f53212b1..a8ca8e0b27f8 100644
--- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
@@ -22,7 +22,7 @@ description:
Each sub-node is identified using the node's name, with valid values listed
for each of the pmics below.
- For mp5496, s2
+ For mp5496, s1, s2
For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22
--
2.17.1
Add support for SMPA1 regulator node in IPQ9574.
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- Updated the regulator-min-microvolt with the SVS voltage 725000uV
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 3ae38cf327ea..06f579b1c590 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -44,6 +44,25 @@
};
};
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq9574_s1: s1 {
+ /*
+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
+ * During regulator registration, kernel not knowing the initial voltage,
+ * considers it as zero and brings up the regulators with minimum supported voltage.
+ * Updating the regulator-min-microvolt with SVS voltage of 725000uV so that
+ * the regulators are brought up with 725000uV which is sufficient for all the
+ * corner parts to operate at 800MHz
+ */
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1075000>;
+ };
+ };
+};
+
&pcie1_phy {
status = "okay";
};
--
2.17.1
Add RPM Glink & RPM message RAM nodes to support frequency scaling
on IPQ9574.
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- Moved rpm_msg_ram node under /soc and updated the node name to sram@
- Moved rpm-glink node such that the nodes are sorted alphabetically
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7c820463a79d..1f9b7529e7ed 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -110,12 +110,29 @@
};
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-ipq9574";
+ qcom,glink-channels = "rpm_requests";
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ rpm_msg_ram: sram@60000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x00060000 0x6000>;
+ };
+
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1000>;
--
2.17.1
Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
Co-developed-by: Praveenkumar I <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
---
Changes in V3:
- No change
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 1f9b7529e7ed..cfef87b5fd22 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -6,6 +6,7 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
@@ -37,6 +38,10 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
CPU1: cpu@1 {
@@ -45,6 +50,10 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
CPU2: cpu@2 {
@@ -53,6 +62,10 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
CPU3: cpu@3 {
@@ -61,6 +74,10 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq9574_s1>;
};
L2_0: l2-cache {
@@ -75,6 +92,47 @@
reg = <0x0 0x40000000 0x0 0x0>;
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-936000000 {
+ opp-hz = /bits/ 64 <936000000>;
+ opp-microvolt = <725000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <787500>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <862500>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1488000000 {
+ opp-hz = /bits/ 64 <1488000000>;
+ opp-microvolt = <925000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <987500>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq9574", "qcom,scm";
--
2.17.1
On 6.04.2023 09:00, Devi Priya wrote:
> Adding support for MP5496 S1 regulator on IPQ9574 SoC.
>
> Co-developed-by: Praveenkumar I <[email protected]>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> Changes in V3:
> - No change
>
> drivers/regulator/qcom_smd-regulator.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c
> index 6f722b2d682e..cb77b3bd1723 100644
> --- a/drivers/regulator/qcom_smd-regulator.c
> +++ b/drivers/regulator/qcom_smd-regulator.c
> @@ -749,6 +749,15 @@ static const struct regulator_desc pms405_pldo600 = {
> .ops = &rpm_smps_ldo_ops,
> };
>
> +static const struct regulator_desc mp5496_smpa1 = {
> + .linear_ranges = (struct linear_range[]) {
> + REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
> + },
> + .n_linear_ranges = 1,
> + .n_voltages = 128,
> + .ops = &rpm_mp5496_ops,
> +};
> +
As far as I can tell, this is identical to struct mp5496_smpa2, so
this patch could come down to:
- static const struct regulator_desc mp5496_smpa1 = {
+ static const struct regulator_desc mp5496_smps = {
+ { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smps, "s1" },
- { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
+ { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smps, "s2" },
Konrad
> static const struct regulator_desc mp5496_smpa2 = {
> .linear_ranges = (struct linear_range[]) {
> REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
> @@ -794,6 +803,7 @@ struct rpm_regulator_data {
> };
>
> static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
> + { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smpa1, "s1" },
> { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
> { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
> {}
On 6.04.2023 09:00, Devi Priya wrote:
> Add RPM Glink & RPM message RAM nodes to support frequency scaling
> on IPQ9574.
>
> Co-developed-by: Praveenkumar I <[email protected]>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> Changes in V3:
> - Moved rpm_msg_ram node under /soc and updated the node name to sram@
> - Moved rpm-glink node such that the nodes are sorted alphabetically
>
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 7c820463a79d..1f9b7529e7ed 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -110,12 +110,29 @@
> };
> };
>
> + rpm-glink {
> + compatible = "qcom,glink-rpm";
> + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> + qcom,rpm-msg-ram = <&rpm_msg_ram>;
> + mboxes = <&apcs_glb 0>;
> +
> + rpm_requests: rpm-requests {
> + compatible = "qcom,rpm-ipq9574";
> + qcom,glink-channels = "rpm_requests";
> + };
> + };
> +
> soc: soc@0 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + rpm_msg_ram: sram@60000 {
> + compatible = "qcom,rpm-msg-ram";
> + reg = <0x00060000 0x6000>;
> + };
> +
> pcie0_phy: phy@84000 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1000>;
On 6.04.2023 09:00, Devi Priya wrote:
> Add support for SMPA1 regulator node in IPQ9574.
>
> Co-developed-by: Praveenkumar I <[email protected]>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> Changes in V3:
> - Updated the regulator-min-microvolt with the SVS voltage 725000uV
>
> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> index 3ae38cf327ea..06f579b1c590 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> @@ -44,6 +44,25 @@
> };
> };
>
> +&rpm_requests {
> + regulators {
> + compatible = "qcom,rpm-mp5496-regulators";
> +
> + ipq9574_s1: s1 {
> + /*
> + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
> + * During regulator registration, kernel not knowing the initial voltage,
> + * considers it as zero and brings up the regulators with minimum supported voltage.
> + * Updating the regulator-min-microvolt with SVS voltage of 725000uV so that
s/Updating/Update
s/725000uV/725mV here and below (for consistency with the first mention
of 800mV)
Konrad
> + * the regulators are brought up with 725000uV which is sufficient for all the
> + * corner parts to operate at 800MHz
> + */
> + regulator-min-microvolt = <725000>;
> + regulator-max-microvolt = <1075000>;
> + };
> + };
> +};
> +
> &pcie1_phy {
> status = "okay";
> };
On 6.04.2023 09:00, Devi Priya wrote:
> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>
> Co-developed-by: Praveenkumar I <[email protected]>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Devi Priya <[email protected]>
> ---
> Changes in V3:
> - No change
>
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 1f9b7529e7ed..cfef87b5fd22 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -6,6 +6,7 @@
> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> @@ -37,6 +38,10 @@
> reg = <0x0>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> + clock-names = "cpu";
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq9574_s1>;
> };
>
> CPU1: cpu@1 {
> @@ -45,6 +50,10 @@
> reg = <0x1>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> + clock-names = "cpu";
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq9574_s1>;
> };
>
> CPU2: cpu@2 {
> @@ -53,6 +62,10 @@
> reg = <0x2>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> + clock-names = "cpu";
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq9574_s1>;
> };
>
> CPU3: cpu@3 {
> @@ -61,6 +74,10 @@
> reg = <0x3>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> + clock-names = "cpu";
> + operating-points-v2 = <&cpu_opp_table>;
> + cpu-supply = <&ipq9574_s1>;
> };
>
> L2_0: l2-cache {
> @@ -75,6 +92,47 @@
> reg = <0x0 0x40000000 0x0 0x0>;
> };
>
> + cpu_opp_table: opp-table-cpu {
This is not sorted properly. It should probably come
after memory alphabetically ('o' > 'm')
Konrad
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-936000000 {
> + opp-hz = /bits/ 64 <936000000>;
> + opp-microvolt = <725000>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1104000000 {
> + opp-hz = /bits/ 64 <1104000000>;
> + opp-microvolt = <787500>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1416000000 {
> + opp-hz = /bits/ 64 <1416000000>;
> + opp-microvolt = <862500>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1488000000 {
> + opp-hz = /bits/ 64 <1488000000>;
> + opp-microvolt = <925000>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <987500>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-2208000000 {
> + opp-hz = /bits/ 64 <2208000000>;
> + opp-microvolt = <1062500>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> firmware {
> scm {
> compatible = "qcom,scm-ipq9574", "qcom,scm";
On 4/7/2023 1:17 AM, Konrad Dybcio wrote:
>
>
> On 6.04.2023 09:00, Devi Priya wrote:
>> Add support for SMPA1 regulator node in IPQ9574.
>>
>> Co-developed-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> Changes in V3:
>> - Updated the regulator-min-microvolt with the SVS voltage 725000uV
>>
>> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> index 3ae38cf327ea..06f579b1c590 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> @@ -44,6 +44,25 @@
>> };
>> };
>>
>> +&rpm_requests {
>> + regulators {
>> + compatible = "qcom,rpm-mp5496-regulators";
>> +
>> + ipq9574_s1: s1 {
>> + /*
>> + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> + * During regulator registration, kernel not knowing the initial voltage,
>> + * considers it as zero and brings up the regulators with minimum supported voltage.
>
>> + * Updating the regulator-min-microvolt with SVS voltage of 725000uV so that
> s/Updating/Update
> s/725000uV/725mV here and below (for consistency with the first mention
> of 800mV)
>
Sure, will update!
> Konrad
>> + * the regulators are brought up with 725000uV which is sufficient for all the
>> + * corner parts to operate at 800MHz
>> + */
>> + regulator-min-microvolt = <725000>;
>> + regulator-max-microvolt = <1075000>;
>> + };
>> + };
>> +};
>> +
>> &pcie1_phy {
>> status = "okay";
>> };
On 4/7/2023 1:21 AM, Konrad Dybcio wrote:
>
>
> On 6.04.2023 09:00, Devi Priya wrote:
>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>>
>> Co-developed-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> Changes in V3:
>> - No change
>>
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>> 1 file changed, 58 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 1f9b7529e7ed..cfef87b5fd22 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -6,6 +6,7 @@
>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> @@ -37,6 +38,10 @@
>> reg = <0x0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> + clock-names = "cpu";
>> + operating-points-v2 = <&cpu_opp_table>;
>> + cpu-supply = <&ipq9574_s1>;
>> };
>>
>> CPU1: cpu@1 {
>> @@ -45,6 +50,10 @@
>> reg = <0x1>;
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> + clock-names = "cpu";
>> + operating-points-v2 = <&cpu_opp_table>;
>> + cpu-supply = <&ipq9574_s1>;
>> };
>>
>> CPU2: cpu@2 {
>> @@ -53,6 +62,10 @@
>> reg = <0x2>;
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> + clock-names = "cpu";
>> + operating-points-v2 = <&cpu_opp_table>;
>> + cpu-supply = <&ipq9574_s1>;
>> };
>>
>> CPU3: cpu@3 {
>> @@ -61,6 +74,10 @@
>> reg = <0x3>;
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> + clock-names = "cpu";
>> + operating-points-v2 = <&cpu_opp_table>;
>> + cpu-supply = <&ipq9574_s1>;
>> };
>>
>> L2_0: l2-cache {
>> @@ -75,6 +92,47 @@
>> reg = <0x0 0x40000000 0x0 0x0>;
>> };
>>
>> + cpu_opp_table: opp-table-cpu {
> This is not sorted properly. It should probably come
> after memory alphabetically ('o' > 'm')
>
Yes, But I see that opp-table-cpu node is already placed after
memory@40000000
> Konrad
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp-936000000 {
>> + opp-hz = /bits/ 64 <936000000>;
>> + opp-microvolt = <725000>;
>> + clock-latency-ns = <200000>;
>> + };
>> +
>> + opp-1104000000 {
>> + opp-hz = /bits/ 64 <1104000000>;
>> + opp-microvolt = <787500>;
>> + clock-latency-ns = <200000>;
>> + };
>> +
>> + opp-1416000000 {
>> + opp-hz = /bits/ 64 <1416000000>;
>> + opp-microvolt = <862500>;
>> + clock-latency-ns = <200000>;
>> + };
>> +
>> + opp-1488000000 {
>> + opp-hz = /bits/ 64 <1488000000>;
>> + opp-microvolt = <925000>;
>> + clock-latency-ns = <200000>;
>> + };
>> +
>> + opp-1800000000 {
>> + opp-hz = /bits/ 64 <1800000000>;
>> + opp-microvolt = <987500>;
>> + clock-latency-ns = <200000>;
>> + };
>> +
>> + opp-2208000000 {
>> + opp-hz = /bits/ 64 <2208000000>;
>> + opp-microvolt = <1062500>;
>> + clock-latency-ns = <200000>;
>> + };
>> + };
>> +
>> firmware {
>> scm {
>> compatible = "qcom,scm-ipq9574", "qcom,scm";
Best Regards,
Devi Priya
On 7.04.2023 06:53, Devi Priya wrote:
>
>
> On 4/7/2023 1:21 AM, Konrad Dybcio wrote:
>>
>>
>> On 6.04.2023 09:00, Devi Priya wrote:
>>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>>>
>>> Co-developed-by: Praveenkumar I <[email protected]>
>>> Signed-off-by: Praveenkumar I <[email protected]>
>>> Signed-off-by: Devi Priya <[email protected]>
>>> ---
>>> Changes in V3:
>>> - No change
>>>
>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>>> 1 file changed, 58 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> index 1f9b7529e7ed..cfef87b5fd22 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> @@ -6,6 +6,7 @@
>>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>> */
>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>>> @@ -37,6 +38,10 @@
>>> reg = <0x0>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2_0>;
>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> + clock-names = "cpu";
>>> + operating-points-v2 = <&cpu_opp_table>;
>>> + cpu-supply = <&ipq9574_s1>;
>>> };
>>> CPU1: cpu@1 {
>>> @@ -45,6 +50,10 @@
>>> reg = <0x1>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2_0>;
>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> + clock-names = "cpu";
>>> + operating-points-v2 = <&cpu_opp_table>;
>>> + cpu-supply = <&ipq9574_s1>;
>>> };
>>> CPU2: cpu@2 {
>>> @@ -53,6 +62,10 @@
>>> reg = <0x2>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2_0>;
>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> + clock-names = "cpu";
>>> + operating-points-v2 = <&cpu_opp_table>;
>>> + cpu-supply = <&ipq9574_s1>;
>>> };
>>> CPU3: cpu@3 {
>>> @@ -61,6 +74,10 @@
>>> reg = <0x3>;
>>> enable-method = "psci";
>>> next-level-cache = <&L2_0>;
>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> + clock-names = "cpu";
>>> + operating-points-v2 = <&cpu_opp_table>;
>>> + cpu-supply = <&ipq9574_s1>;
>>> };
>>> L2_0: l2-cache {
>>> @@ -75,6 +92,47 @@
>>> reg = <0x0 0x40000000 0x0 0x0>;
>>> };
>>> + cpu_opp_table: opp-table-cpu {
>> This is not sorted properly. It should probably come
>> after memory alphabetically ('o' > 'm')
>>
> Yes, But I see that opp-table-cpu node is already placed after
> memory@40000000
Oh you're right, the diff doesn't really show that very
well and I didn't notice..
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
>> Konrad
>>> + compatible = "operating-points-v2";
>>> + opp-shared;
>>> +
>>> + opp-936000000 {
>>> + opp-hz = /bits/ 64 <936000000>;
>>> + opp-microvolt = <725000>;
>>> + clock-latency-ns = <200000>;
>>> + };
>>> +
>>> + opp-1104000000 {
>>> + opp-hz = /bits/ 64 <1104000000>;
>>> + opp-microvolt = <787500>;
>>> + clock-latency-ns = <200000>;
>>> + };
>>> +
>>> + opp-1416000000 {
>>> + opp-hz = /bits/ 64 <1416000000>;
>>> + opp-microvolt = <862500>;
>>> + clock-latency-ns = <200000>;
>>> + };
>>> +
>>> + opp-1488000000 {
>>> + opp-hz = /bits/ 64 <1488000000>;
>>> + opp-microvolt = <925000>;
>>> + clock-latency-ns = <200000>;
>>> + };
>>> +
>>> + opp-1800000000 {
>>> + opp-hz = /bits/ 64 <1800000000>;
>>> + opp-microvolt = <987500>;
>>> + clock-latency-ns = <200000>;
>>> + };
>>> +
>>> + opp-2208000000 {
>>> + opp-hz = /bits/ 64 <2208000000>;
>>> + opp-microvolt = <1062500>;
>>> + clock-latency-ns = <200000>;
>>> + };
>>> + };
>>> +
>>> firmware {
>>> scm {
>>> compatible = "qcom,scm-ipq9574", "qcom,scm";
> Best Regards,
> Devi Priya
On 4/7/2023 5:29 PM, Konrad Dybcio wrote:
>
>
> On 7.04.2023 06:53, Devi Priya wrote:
>>
>>
>> On 4/7/2023 1:21 AM, Konrad Dybcio wrote:
>>>
>>>
>>> On 6.04.2023 09:00, Devi Priya wrote:
>>>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>>>>
>>>> Co-developed-by: Praveenkumar I <[email protected]>
>>>> Signed-off-by: Praveenkumar I <[email protected]>
>>>> Signed-off-by: Devi Priya <[email protected]>
>>>> ---
>>>> Changes in V3:
>>>> - No change
>>>>
>>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>>>> 1 file changed, 58 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> index 1f9b7529e7ed..cfef87b5fd22 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> @@ -6,6 +6,7 @@
>>>> * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>>> */
>>>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>>>> @@ -37,6 +38,10 @@
>>>> reg = <0x0>;
>>>> enable-method = "psci";
>>>> next-level-cache = <&L2_0>;
>>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> + clock-names = "cpu";
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + cpu-supply = <&ipq9574_s1>;
>>>> };
>>>> CPU1: cpu@1 {
>>>> @@ -45,6 +50,10 @@
>>>> reg = <0x1>;
>>>> enable-method = "psci";
>>>> next-level-cache = <&L2_0>;
>>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> + clock-names = "cpu";
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + cpu-supply = <&ipq9574_s1>;
>>>> };
>>>> CPU2: cpu@2 {
>>>> @@ -53,6 +62,10 @@
>>>> reg = <0x2>;
>>>> enable-method = "psci";
>>>> next-level-cache = <&L2_0>;
>>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> + clock-names = "cpu";
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + cpu-supply = <&ipq9574_s1>;
>>>> };
>>>> CPU3: cpu@3 {
>>>> @@ -61,6 +74,10 @@
>>>> reg = <0x3>;
>>>> enable-method = "psci";
>>>> next-level-cache = <&L2_0>;
>>>> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> + clock-names = "cpu";
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + cpu-supply = <&ipq9574_s1>;
>>>> };
>>>> L2_0: l2-cache {
>>>> @@ -75,6 +92,47 @@
>>>> reg = <0x0 0x40000000 0x0 0x0>;
>>>> };
>>>> + cpu_opp_table: opp-table-cpu {
>>> This is not sorted properly. It should probably come
>>> after memory alphabetically ('o' > 'm')
>>>
>> Yes, But I see that opp-table-cpu node is already placed after
>> memory@40000000
>
> Oh you're right, the diff doesn't really show that very
> well and I didn't notice..
>
>
> Reviewed-by: Konrad Dybcio <[email protected]>
Sure, thank you!
>
> Konrad
>>> Konrad
>>>> + compatible = "operating-points-v2";
>>>> + opp-shared;
>>>> +
>>>> + opp-936000000 {
>>>> + opp-hz = /bits/ 64 <936000000>;
>>>> + opp-microvolt = <725000>;
>>>> + clock-latency-ns = <200000>;
>>>> + };
>>>> +
>>>> + opp-1104000000 {
>>>> + opp-hz = /bits/ 64 <1104000000>;
>>>> + opp-microvolt = <787500>;
>>>> + clock-latency-ns = <200000>;
>>>> + };
>>>> +
>>>> + opp-1416000000 {
>>>> + opp-hz = /bits/ 64 <1416000000>;
>>>> + opp-microvolt = <862500>;
>>>> + clock-latency-ns = <200000>;
>>>> + };
>>>> +
>>>> + opp-1488000000 {
>>>> + opp-hz = /bits/ 64 <1488000000>;
>>>> + opp-microvolt = <925000>;
>>>> + clock-latency-ns = <200000>;
>>>> + };
>>>> +
>>>> + opp-1800000000 {
>>>> + opp-hz = /bits/ 64 <1800000000>;
>>>> + opp-microvolt = <987500>;
>>>> + clock-latency-ns = <200000>;
>>>> + };
>>>> +
>>>> + opp-2208000000 {
>>>> + opp-hz = /bits/ 64 <2208000000>;
>>>> + opp-microvolt = <1062500>;
>>>> + clock-latency-ns = <200000>;
>>>> + };
>>>> + };
>>>> +
>>>> firmware {
>>>> scm {
>>>> compatible = "qcom,scm-ipq9574", "qcom,scm";
>> Best Regards,
>> Devi Priya
On 4/7/2023 1:07 AM, Konrad Dybcio wrote:
>
>
> On 6.04.2023 09:00, Devi Priya wrote:
>> Adding support for MP5496 S1 regulator on IPQ9574 SoC.
>>
>> Co-developed-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Devi Priya <[email protected]>
>> ---
>> Changes in V3:
>> - No change
>>
>> drivers/regulator/qcom_smd-regulator.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c
>> index 6f722b2d682e..cb77b3bd1723 100644
>> --- a/drivers/regulator/qcom_smd-regulator.c
>> +++ b/drivers/regulator/qcom_smd-regulator.c
>> @@ -749,6 +749,15 @@ static const struct regulator_desc pms405_pldo600 = {
>> .ops = &rpm_smps_ldo_ops,
>> };
>>
>> +static const struct regulator_desc mp5496_smpa1 = {
>> + .linear_ranges = (struct linear_range[]) {
>> + REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
>> + },
>> + .n_linear_ranges = 1,
>> + .n_voltages = 128,
>> + .ops = &rpm_mp5496_ops,
>> +};
>> +
> As far as I can tell, this is identical to struct mp5496_smpa2, so
> this patch could come down to:
>
> - static const struct regulator_desc mp5496_smpa1 = {
> + static const struct regulator_desc mp5496_smps = {
>
>
>
> + { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smps, "s1" },
> - { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
> + { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smps, "s2" },
>
Yes, right. Will update it
> Konrad
>> static const struct regulator_desc mp5496_smpa2 = {
>> .linear_ranges = (struct linear_range[]) {
>> REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
>> @@ -794,6 +803,7 @@ struct rpm_regulator_data {
>> };
>>
>> static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
>> + { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smpa1, "s1" },
>> { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
>> { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
>> {}
Best Regards,
Devi Priya