Implement ARM errata 814220 for Cortex A7.
This patch has been wroten by Jason Liu years ago but never send upstream.
I have tried to contact the author on multiple email addresses but I haven't
found any valid one...
I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
Benjamin Gaignard (2):
ARM: errata 814220-B-Cache maintenance by set/way operations can
execute out of order.
ARM: stm32: select ARM errata 814220
arch/arm/Kconfig | 10 ++++++++++
arch/arm/mach-stm32/Kconfig | 1 +
arch/arm/mm/cache-v7.S | 3 +++
3 files changed, 14 insertions(+)
--
2.15.0
Make sure that ARM errata 814220 is selected by STM32MP157 SoC
Signed-off-by: Benjamin Gaignard <[email protected]>
---
arch/arm/mach-stm32/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 713c068b953f..be2403fa3deb 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -46,6 +46,7 @@ if ARCH_MULTI_V7
config MACH_STM32MP157
bool "STMicroelectronics STM32MP157"
+ select ARM_ERRATA_814220
default y
endif # ARMv7-A
--
2.15.0
Description:
The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.
This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
Signed-off-by: Jason Liu <[email protected]>
Signed-off-by: Benjamin Gaignard <[email protected]>
---
arch/arm/Kconfig | 10 ++++++++++
arch/arm/mm/cache-v7.S | 3 +++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918e2624..6f608558e22a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1227,6 +1227,16 @@ config PCI_HOST_ITE8152
default y
select DMABOUNCE
+config ARM_ERRATA_814220
+ bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+ depends on CPU_V7
+ help
+ The v7 ARM states that all cache and branch predictor maintenance operations
+ that do not specify an address execute, relative to each other, in program order.
+ However, because of this erratum, an L2 set/way cache maintenance operation can
+ overtake an L1 set/way cache maintenance operation. This ERRATA only affected the
+ Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
+
endmenu
menu "Kernel Features"
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 2149b47a0c5a..7ff7b4c197cc 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -163,6 +163,9 @@ loop2:
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
+#ifdef CONFIG_ARM_ERRATA_814220
+ dsb
+#endif
bgt flush_levels
finished:
mov r10, #0 @ switch back to cache level 0
--
2.15.0
On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard
<[email protected]> wrote:
>
> Implement ARM errata 814220 for Cortex A7.
>
> This patch has been wroten by Jason Liu years ago but never send upstream.
> I have tried to contact the author on multiple email addresses but I haven't
> found any valid one...
> I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
>
> Benjamin Gaignard (2):
> ARM: errata 814220-B-Cache maintenance by set/way operations can
> execute out of order.
> ARM: stm32: select ARM errata 814220
>
> arch/arm/Kconfig | 10 ++++++++++
> arch/arm/mach-stm32/Kconfig | 1 +
> arch/arm/mm/cache-v7.S | 3 +++
> 3 files changed, 14 insertions(+)
Looks good to me,
Acked-by: Arnd Bergmann <[email protected]>
It probably makes most sense to keep them as a series, either
through the soc tree or Russell's patch tracker, so feel free to add
it there, and have them both in the stm32 soc branch for arm-soc
if Russell prefers.
As we have a number of Cortex-A7 based platforms with all
kinds of revisions, I wonder if we should also select the workaround
for the others. I can probably figure out which SoC platforms
are based on Cortex-A7, but I have no idea about the revisions,
so that might mean we'd have to do it for all of them. According
to the latest TRM I found, only revisions r0p0 through r0p5
exist, and the erraturm text lists r0p2 through r0p5, which may
mean all products ever shipped in practice (the oldest public
TRM from 2012 already describe r0p3).
Arnd
On Wed, Feb 13, 2019 at 10:56:12AM +0100, Benjamin Gaignard wrote:
> Description:
> The v7 ARM states that all cache and branch predictor maintenance operations
> that do not specify an address execute, relative to each other, in program
> order. However, because of this erratum, an L2 set/way cache maintenance
> operation can overtake an L1 set/way cache maintenance operation, this would
> cause the data corruption.
>
> This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
>
> This patch is the SW workaround by adding a DSB before changing cache levels as
> the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
>
> Signed-off-by: Jason Liu <[email protected]>
> Signed-off-by: Benjamin Gaignard <[email protected]>
> ---
> arch/arm/Kconfig | 10 ++++++++++
> arch/arm/mm/cache-v7.S | 3 +++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 664e918e2624..6f608558e22a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1227,6 +1227,16 @@ config PCI_HOST_ITE8152
> default y
> select DMABOUNCE
>
> +config ARM_ERRATA_814220
> + bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
> + depends on CPU_V7
> + help
> + The v7 ARM states that all cache and branch predictor maintenance operations
> + that do not specify an address execute, relative to each other, in program order.
> + However, because of this erratum, an L2 set/way cache maintenance operation can
> + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the
> + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
We generally try to keep help lines so that when edited on an 80 column
display, they do not wrap. Please can you reformat the above to satisfy
that please? (means breaking the lines after "maintenance" on the first
line.)
Thanks.
> +
> endmenu
>
> menu "Kernel Features"
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index 2149b47a0c5a..7ff7b4c197cc 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -163,6 +163,9 @@ loop2:
> skip:
> add r10, r10, #2 @ increment cache number
> cmp r3, r10
> +#ifdef CONFIG_ARM_ERRATA_814220
> + dsb
> +#endif
> bgt flush_levels
> finished:
> mov r10, #0 @ switch back to cache level 0
> --
> 2.15.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
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On 2/13/19 3:52 PM, Arnd Bergmann wrote:
> On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard
> <[email protected]> wrote:
>>
>> Implement ARM errata 814220 for Cortex A7.
>>
>> This patch has been wroten by Jason Liu years ago but never send upstream.
>> I have tried to contact the author on multiple email addresses but I haven't
>> found any valid one...
>> I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
>>
>> Benjamin Gaignard (2):
>> ARM: errata 814220-B-Cache maintenance by set/way operations can
>> execute out of order.
>> ARM: stm32: select ARM errata 814220
>>
>> arch/arm/Kconfig | 10 ++++++++++
>> arch/arm/mach-stm32/Kconfig | 1 +
>> arch/arm/mm/cache-v7.S | 3 +++
>> 3 files changed, 14 insertions(+)
>
> Looks good to me,
>
> Acked-by: Arnd Bergmann <[email protected]>
>
> It probably makes most sense to keep them as a series, either
> through the soc tree or Russell's patch tracker, so feel free to add
> it there, and have them both in the stm32 soc branch for arm-soc
> if Russell prefers.
Russel, what do you think about Arnd proposition? I could take both
patches in my stm32 tree. It'll make part of future v5.2 pull request.
Alex
>
> As we have a number of Cortex-A7 based platforms with all
> kinds of revisions, I wonder if we should also select the workaround
> for the others. I can probably figure out which SoC platforms
> are based on Cortex-A7, but I have no idea about the revisions,
> so that might mean we'd have to do it for all of them. According
> to the latest TRM I found, only revisions r0p0 through r0p5
> exist, and the erraturm text lists r0p2 through r0p5, which may
> mean all products ever shipped in practice (the oldest public
> TRM from 2012 already describe r0p3).
>
>
>
>
> Arnd
>