Hi all,
This patch series adds support for
the imx8q video encoder and decoder
via the VPU block present in imx8q platforms.
Currently, support for IMX8QXP and IMX8QM is included.
It features decoding for the following formats:
- H.264
- HEVC
- MPEG4
- MPEG2
- MJPEG
- VC1
- VP8
- AVS
It features encoding for the following formats:
- H.264
The driver creates a separate device node for
the encoder and decoder.
Changelog:
v4:
- redefine the memory-region in devicetree bindings documentation
- use v4l2's mechanism to implement synchronize queuing ioctl
- remove the unnecessary mutex ioctl_sync
- don't notify source change event if the parameters are same as previously established
- add flag V4L2_FMT_FLAG_DYN_RESOLUTION to decoder's capture format
v3:
- don't make vpu device node a simple-bus
- trigger probing vpu core in the driver
- remove unnecessary vpu core index property
v2:
- fix dt bindings build error
- split driver patch into several parts to avoid exceeding bytes limit
Compliance
==========
# v4l2-compliance -d /dev/video0
v4l2-compliance SHA: not available
, 64 bits, 64-bit time_t
Compliance test for vpu B0 device /dev/video0:
Driver Info:
Driver name : vpu B0
Card type : imx vpu decoder
Bus info : platform: imx8q-vpu
Driver version : 5.10.35
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video0 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
test invalid ioctls: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 3 Private Controls: 2
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for vpu b0 device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 0
# v4l2-compliance -d /dev/video1
v4l2-compliance SHA: not available
, 64 bits, 64-bit time_t
Compliance test for imx vpu encoder device /dev/video1:
Driver Info:
Driver name : imx vpu encoder
Card type : imx vpu encoder
Bus info : platform: imx8q-vpu
Driver version : 5.10.35
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected Stateful Encoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video1 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
test invalid ioctls: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 20 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for imx vpu encoder device /dev/video1: 45, Succeeded: 45, Failed: 0, Warnings: 0
Ming Qian (13):
dt-bindings: media: imx8q: add imx video codec bindings
media: v4l: add some definition of v4l2
colorspace/xfer_func/ycbcr_encoding
media: imx: imx8q: add imx8q vpu device driver
media: imx: imx8q: add vpu core driver
media: imx: imx8q: implement vpu core communication based on mailbox
media: imx: imx8q: add vpu v4l2 m2m support
media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver
media: imx: imx8q: add v4l2 m2m vpu decoder stateful driver
media: imx: imx8q: implement windsor encoder rpc interface
media: imx: imx8q: implement malone decoder rpc interface
ARM64: dts: freescale: imx8q: add imx vpu codec entries
firmware: imx: scu-pd: imx8q: add vpu mu resources
MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
.../bindings/media/nxp,imx8q-vpu.yaml | 178 ++
MAINTAINERS | 10 +
.../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 +
drivers/firmware/imx/scu-pd.c | 4 +
drivers/media/platform/Kconfig | 2 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/imx/Kconfig | 19 +
drivers/media/platform/imx/Makefile | 1 +
drivers/media/platform/imx/vpu-8q/Makefile | 23 +
drivers/media/platform/imx/vpu-8q/vdec.c | 1817 +++++++++++++++++
drivers/media/platform/imx/vpu-8q/venc.c | 1395 +++++++++++++
drivers/media/platform/imx/vpu-8q/vpu.h | 343 ++++
drivers/media/platform/imx/vpu-8q/vpu_cmds.c | 446 ++++
drivers/media/platform/imx/vpu-8q/vpu_cmds.h | 34 +
drivers/media/platform/imx/vpu-8q/vpu_codec.h | 77 +
drivers/media/platform/imx/vpu-8q/vpu_color.c | 201 ++
drivers/media/platform/imx/vpu-8q/vpu_core.c | 919 +++++++++
drivers/media/platform/imx/vpu-8q/vpu_core.h | 25 +
drivers/media/platform/imx/vpu-8q/vpu_dbg.c | 505 +++++
drivers/media/platform/imx/vpu-8q/vpu_defs.h | 194 ++
.../media/platform/imx/vpu-8q/vpu_dev_imx8q.c | 82 +
drivers/media/platform/imx/vpu-8q/vpu_drv.c | 225 ++
.../media/platform/imx/vpu-8q/vpu_helpers.c | 405 ++++
.../media/platform/imx/vpu-8q/vpu_helpers.h | 80 +
drivers/media/platform/imx/vpu-8q/vpu_imx8q.c | 227 ++
drivers/media/platform/imx/vpu-8q/vpu_imx8q.h | 125 ++
drivers/media/platform/imx/vpu-8q/vpu_log.h | 53 +
.../media/platform/imx/vpu-8q/vpu_malone.c | 1744 ++++++++++++++++
.../media/platform/imx/vpu-8q/vpu_malone.h | 51 +
drivers/media/platform/imx/vpu-8q/vpu_mbox.c | 135 ++
drivers/media/platform/imx/vpu-8q/vpu_mbox.h | 25 +
drivers/media/platform/imx/vpu-8q/vpu_msgs.c | 420 ++++
drivers/media/platform/imx/vpu-8q/vpu_msgs.h | 23 +
drivers/media/platform/imx/vpu-8q/vpu_rpc.c | 266 +++
drivers/media/platform/imx/vpu-8q/vpu_rpc.h | 472 +++++
drivers/media/platform/imx/vpu-8q/vpu_v4l2.c | 662 ++++++
drivers/media/platform/imx/vpu-8q/vpu_v4l2.h | 53 +
.../media/platform/imx/vpu-8q/vpu_windsor.c | 1253 ++++++++++++
.../media/platform/imx/vpu-8q/vpu_windsor.h | 48 +
include/linux/imx_vpu.h | 19 +
include/uapi/linux/imx_vpu.h | 120 ++
include/uapi/linux/videodev2.h | 30 +
44 files changed, 12828 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
create mode 100644 drivers/media/platform/imx/Kconfig
create mode 100644 drivers/media/platform/imx/Makefile
create mode 100644 drivers/media/platform/imx/vpu-8q/Makefile
create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c
create mode 100644 drivers/media/platform/imx/vpu-8q/venc.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_codec.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_color.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dbg.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_defs.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_drv.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_log.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.h
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.h
create mode 100644 include/linux/imx_vpu.h
create mode 100644 include/uapi/linux/imx_vpu.h
--
2.32.0
This consists of video decoder implementation plus decoder controls.
Signed-off-by: Ming Qian <[email protected]>
Signed-off-by: Shijie Qin <[email protected]>
Signed-off-by: Zhou Peng <[email protected]>
---
drivers/media/platform/imx/vpu-8q/vdec.c | 1817 ++++++++++++++++++++++
1 file changed, 1817 insertions(+)
create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c
diff --git a/drivers/media/platform/imx/vpu-8q/vdec.c b/drivers/media/platform/imx/vpu-8q/vdec.c
new file mode 100644
index 000000000000..3bae2c0de7c1
--- /dev/null
+++ b/drivers/media/platform/imx/vpu-8q/vdec.c
@@ -0,0 +1,1817 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020-2021 NXP
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define TAG "DEC"
+#include <linux/init.h>
+#include <linux/interconnect.h>
+#include <linux/ioctl.h>
+#include <linux/list.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/videobuf2-vmalloc.h>
+#include <linux/imx_vpu.h>
+#include "vpu.h"
+#include "vpu_defs.h"
+#include "vpu_core.h"
+#include "vpu_helpers.h"
+#include "vpu_v4l2.h"
+#include "vpu_cmds.h"
+#include "vpu_rpc.h"
+#include "vpu_log.h"
+
+#define VDEC_FRAME_DEPTH 256
+
+struct vdec_fs_info {
+ char name[8];
+ u32 type;
+ u32 max_count;
+ u32 req_count;
+ u32 count;
+ u32 index;
+ u32 size;
+ struct vpu_buffer buffer[32];
+ u32 tag;
+};
+
+struct vdec_t {
+ u32 seq_hdr_found;
+ struct vpu_buffer udata;
+ struct vpu_decode_params params;
+ struct vpu_dec_codec_info codec_info;
+ enum vpu_codec_state state;
+
+ struct vpu_vb2_buffer *slots[VB2_MAX_FRAME];
+ u32 req_frame_count;
+ struct vdec_fs_info mbi;
+ struct vdec_fs_info dcp;
+ u32 seq_tag;
+
+ u32 decoded_frame_count;
+ u32 display_frame_count;
+ u32 eos_received;
+ u32 eos_subscribed;
+ bool is_source_changed;
+ u32 source_change;
+ u32 drain;
+ u32 ts_pre_count;
+ u32 frame_depth;
+ s64 ts_start;
+ s64 ts_input;
+ s64 timestamp;
+};
+
+static const struct vpu_format vdec_formats[] = {
+ {
+ .pixfmt = V4L2_PIX_FMT_NV12,
+ .num_planes = 2,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+ },
+ {
+ .name = "NXP Tiled NV12 Format",
+ .pixfmt = V4L2_PIX_FMT_NT8,
+ .num_planes = 2,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+ },
+ {
+ .name = "NXP Tiled 10bit Format",
+ .pixfmt = V4L2_PIX_FMT_NT10,
+ .num_planes = 2,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_H264,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_H264_MVC,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_HEVC,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_G,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_VC1_ANNEX_L,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_MPEG2,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_MPEG4,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .name = "AVS",
+ .pixfmt = V4L2_PIX_FMT_AVS,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_XVID,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_JPEG,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .name = "VP6",
+ .pixfmt = V4L2_PIX_FMT_VP6,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_VP8,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .name = "SPK",
+ .pixfmt = V4L2_PIX_FMT_SPK,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {
+ .pixfmt = V4L2_PIX_FMT_H263,
+ .num_planes = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ .flags = V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_DYN_RESOLUTION
+ },
+ {0, 0, 0, 0},
+};
+
+static int vdec_op_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct vpu_inst *inst = ctrl_to_inst(ctrl);
+ struct vdec_t *vdec = inst->priv;
+
+ switch (ctrl->id) {
+ case V4L2_CID_DIS_REORDER:
+ vdec->params.b_dis_reorder = ctrl->val;
+ break;
+ case V4L2_CID_NON_FRAME:
+ vdec->params.b_non_frame = ctrl->val;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct v4l2_ctrl_ops vdec_ctrl_ops = {
+ .s_ctrl = vdec_op_s_ctrl,
+ .g_volatile_ctrl = vpu_helper_g_volatile_ctrl,
+};
+
+static struct v4l2_ctrl_config vdec_custom_cfg[] = {
+ {
+ .id = V4L2_CID_DIS_REORDER,
+ .name = "frame disable reoder ctrl",
+ .ops = &vdec_ctrl_ops,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .min = 0,
+ .max = 1,
+ .step = 1,
+ .def = 0,
+ },
+ {
+ .id = V4L2_CID_NON_FRAME,
+ .name = "stream input mode, is non frame or not",
+ .ops = &vdec_ctrl_ops,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .min = 0,
+ .max = 1,
+ .step = 1,
+ .def = 0,
+ },
+ {0, 0, 0, 0},
+};
+
+static int vdec_ctrl_init(struct vpu_inst *inst)
+{
+ struct v4l2_ctrl *ctrl;
+ int i;
+ int ret;
+
+ ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 20);
+ if (ret)
+ return ret;
+
+ ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
+ V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 2);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
+
+ ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
+ V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 2);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
+
+ for (i = 0; i < ARRAY_SIZE(vdec_custom_cfg); i++)
+ ctrl = v4l2_ctrl_new_custom(&inst->ctrl_handler, &vdec_custom_cfg[i], NULL);
+
+ ret = v4l2_ctrl_handler_setup(&inst->ctrl_handler);
+ if (ret) {
+ inst_err(inst, "setup ctrls fail, ret = %d\n", ret);
+ v4l2_ctrl_handler_free(&inst->ctrl_handler);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int vdec_handle_eos(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vb2_queue *dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
+
+ if (!vdec->eos_received)
+ return 0;
+
+ if (!vdec->eos_subscribed)
+ return 0;
+
+ if (!list_empty(&dst_q->done_list))
+ return 0;
+
+ dst_q->last_buffer_dequeued = true;
+ vpu_notify_eos(inst);
+ vdec->eos_received--;
+
+ return 0;
+}
+
+static void vdec_handle_resolution_change(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vb2_queue *q;
+
+ if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ return;
+ if (!vdec->source_change)
+ return;
+
+ q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
+ if (!list_empty(&q->done_list))
+ return;
+
+ vdec->source_change--;
+ vpu_notify_source_change(inst);
+}
+
+static int vdec_update_state(struct vpu_inst *inst,
+ enum vpu_codec_state state, u32 force)
+{
+ struct vdec_t *vdec = inst->priv;
+ enum vpu_codec_state pre_state = inst->state;
+
+ if (state == VPU_CODEC_STATE_SEEK) {
+ if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ vdec->state = inst->state;
+ else
+ vdec->state = VPU_CODEC_STATE_ACTIVE;
+ }
+ if (inst->state != VPU_CODEC_STATE_SEEK || force)
+ inst->state = state;
+ else if (state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ vdec->state = VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE;
+
+ inst_dbg(inst, LVL_FLOW, "state : %d -> %d\n", pre_state, inst->state);
+
+ if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ vdec_handle_resolution_change(inst);
+
+ return 0;
+}
+
+static int vdec_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
+{
+ strscpy(cap->driver, "vpu B0", sizeof(cap->driver));
+ strscpy(cap->card, "imx vpu decoder", sizeof(cap->card));
+ strscpy(cap->bus_info, "platform: imx8q-vpu", sizeof(cap->bus_info));
+
+ return 0;
+}
+
+static int vdec_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f)
+{
+ struct vpu_inst *inst = to_inst(file);
+ struct vdec_t *vdec = inst->priv;
+ const struct vpu_format *fmt;
+ const char *descr = NULL;
+ int ret = -EINVAL;
+
+ vpu_inst_lock(inst);
+ if (!V4L2_TYPE_IS_OUTPUT(f->type) && vdec->seq_hdr_found) {
+ if (f->index == 0) {
+ f->pixelformat = inst->cap_format.pixfmt;
+ f->flags = inst->cap_format.flags;
+ descr = inst->cap_format.name;
+ ret = 0;
+ }
+ } else {
+ fmt = vpu_helper_enum_format(inst, f->type, f->index);
+ memset(f->reserved, 0, sizeof(f->reserved));
+ if (!fmt)
+ goto exit;
+
+ f->pixelformat = fmt->pixfmt;
+ f->flags = fmt->flags;
+ descr = fmt->name;
+ ret = 0;
+ }
+ if (descr && strlen(descr))
+ strscpy(f->description, descr, sizeof(f->description));
+
+exit:
+ vpu_inst_unlock(inst);
+ return ret;
+}
+
+static int vdec_g_fmt(struct file *file, void *fh, struct v4l2_format *f)
+{
+ struct vpu_inst *inst = to_inst(file);
+ struct vdec_t *vdec = inst->priv;
+ struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
+ struct vpu_format *cur_fmt;
+ int i;
+
+ cur_fmt = vpu_get_format(inst, f->type);
+
+ pixmp->pixelformat = cur_fmt->pixfmt;
+ pixmp->num_planes = cur_fmt->num_planes;
+ pixmp->width = cur_fmt->width;
+ pixmp->height = cur_fmt->height;
+ pixmp->field = cur_fmt->field;
+ pixmp->flags = cur_fmt->flags;
+ for (i = 0; i < pixmp->num_planes; i++) {
+ pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i];
+ pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i];
+ }
+
+ f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries;
+ f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars;
+ f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs;
+ f->fmt.pix_mp.quantization = vdec->codec_info.full_range;
+
+ inst_dbg(inst, LVL_DEBUG, "%s g_fmt: %c%c%c%c %dx%d %d,%d, %d,%d\n",
+ vpu_type_name(f->type),
+ f->fmt.pix_mp.pixelformat,
+ f->fmt.pix_mp.pixelformat >> 8,
+ f->fmt.pix_mp.pixelformat >> 16,
+ f->fmt.pix_mp.pixelformat >> 24,
+ f->fmt.pix_mp.width,
+ f->fmt.pix_mp.height,
+ pixmp->plane_fmt[0].sizeimage,
+ pixmp->plane_fmt[1].sizeimage,
+ pixmp->plane_fmt[0].bytesperline,
+ pixmp->plane_fmt[1].bytesperline);
+
+ return 0;
+}
+
+static int vdec_try_fmt(struct file *file, void *fh, struct v4l2_format *f)
+{
+ struct vpu_inst *inst = to_inst(file);
+ struct vdec_t *vdec = inst->priv;
+
+ vpu_try_fmt_common(inst, f);
+
+ vpu_inst_lock(inst);
+ if (vdec->seq_hdr_found) {
+ f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries;
+ f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars;
+ f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs;
+ f->fmt.pix_mp.quantization = vdec->codec_info.full_range;
+ } else {
+ f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_DEFAULT;
+ f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
+ f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+ }
+ vpu_inst_unlock(inst);
+
+ return 0;
+}
+
+static int vdec_s_fmt(struct file *file, void *fh, struct v4l2_format *f)
+{
+ struct vpu_inst *inst = to_inst(file);
+ struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp;
+ const struct vpu_format *fmt;
+ struct vpu_format *cur_fmt;
+ struct vb2_queue *q;
+ struct vdec_t *vdec;
+ int i;
+
+ vdec = inst->priv;
+ q = v4l2_m2m_get_vq(inst->m2m_ctx, f->type);
+ if (!q)
+ return -EINVAL;
+ if (vb2_is_streaming(q))
+ return -EBUSY;
+
+ fmt = vpu_try_fmt_common(inst, f);
+ if (!fmt)
+ return -EINVAL;
+
+ cur_fmt = vpu_get_format(inst, f->type);
+
+ vpu_inst_lock(inst);
+ cur_fmt->pixfmt = fmt->pixfmt;
+ cur_fmt->type = fmt->type;
+ if (V4L2_TYPE_IS_OUTPUT(f->type) || vdec->seq_hdr_found <= 0) {
+ cur_fmt->num_planes = fmt->num_planes;
+ cur_fmt->flags = fmt->flags;
+ cur_fmt->width = pixmp->width;
+ cur_fmt->height = pixmp->height;
+ for (i = 0; i < fmt->num_planes; i++) {
+ cur_fmt->sizeimage[i] = pixmp->plane_fmt[i].sizeimage;
+ cur_fmt->bytesperline[i] = pixmp->plane_fmt[i].bytesperline;
+ }
+ if (pixmp->field != V4L2_FIELD_ANY)
+ cur_fmt->field = pixmp->field;
+ } else {
+ pixmp->num_planes = cur_fmt->num_planes;
+ pixmp->width = cur_fmt->width;
+ pixmp->height = cur_fmt->height;
+ for (i = 0; i < pixmp->num_planes; i++) {
+ pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i];
+ pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i];
+ }
+ pixmp->field = cur_fmt->field;
+ }
+ if (V4L2_TYPE_IS_OUTPUT(f->type))
+ vdec->params.codec_format = cur_fmt->pixfmt;
+ else
+ vdec->params.output_format = cur_fmt->pixfmt;
+
+ if (!vdec->seq_hdr_found) {
+ vdec->codec_info.color_primaries = f->fmt.pix_mp.colorspace;
+ vdec->codec_info.transfer_chars = f->fmt.pix_mp.xfer_func;
+ vdec->codec_info.matrix_coeffs = f->fmt.pix_mp.ycbcr_enc;
+ vdec->codec_info.full_range = f->fmt.pix_mp.quantization;
+
+ inst->crop.left = 0;
+ inst->crop.top = 0;
+ inst->crop.width = cur_fmt->width;
+ inst->crop.height = cur_fmt->height;
+ } else {
+ f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries;
+ f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars;
+ f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs;
+ f->fmt.pix_mp.quantization = vdec->codec_info.full_range;
+ }
+
+ vpu_inst_unlock(inst);
+
+ inst_dbg(inst, LVL_FLOW, "%s s_fmt: %c%c%c%c %dx%d %u,%u, %u,%u\n",
+ vpu_type_name(f->type),
+ f->fmt.pix_mp.pixelformat,
+ f->fmt.pix_mp.pixelformat >> 8,
+ f->fmt.pix_mp.pixelformat >> 16,
+ f->fmt.pix_mp.pixelformat >> 24,
+ f->fmt.pix_mp.width,
+ f->fmt.pix_mp.height,
+ pixmp->plane_fmt[0].sizeimage,
+ pixmp->plane_fmt[1].sizeimage,
+ pixmp->plane_fmt[0].bytesperline,
+ pixmp->plane_fmt[1].bytesperline);
+
+ return 0;
+}
+
+static int vdec_g_selection(struct file *file, void *fh,
+ struct v4l2_selection *s)
+{
+ struct vpu_inst *inst = to_inst(file);
+
+ if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
+ s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+ s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
+ s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+ return -EINVAL;
+
+ switch (s->target) {
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ if (!V4L2_TYPE_IS_OUTPUT(s->type))
+ return -EINVAL;
+ s->r.left = 0;
+ s->r.top = 0;
+ s->r.width = inst->out_format.width;
+ s->r.height = inst->out_format.height;
+ break;
+ case V4L2_SEL_TGT_CROP:
+ case V4L2_SEL_TGT_CROP_DEFAULT:
+ if (!V4L2_TYPE_IS_OUTPUT(s->type))
+ return -EINVAL;
+ s->r = inst->crop;
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ case V4L2_SEL_TGT_COMPOSE_DEFAULT:
+ case V4L2_SEL_TGT_COMPOSE_PADDED:
+ if (V4L2_TYPE_IS_OUTPUT(s->type))
+ return -EINVAL;
+ s->r = inst->crop;
+ break;
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ if (V4L2_TYPE_IS_OUTPUT(s->type))
+ return -EINVAL;
+ s->r.left = 0;
+ s->r.top = 0;
+ s->r.width = inst->cap_format.width;
+ s->r.height = inst->cap_format.height;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+
+ return 0;
+}
+
+static int vdec_drain(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ if (!vdec->drain)
+ return 0;
+
+ if (v4l2_m2m_num_src_bufs_ready(inst->m2m_ctx))
+ return 0;
+
+ if (!vdec->params.frame_count) {
+ vpu_notify_eos(inst);
+ return 0;
+ }
+
+ vpu_iface_add_scode(inst, SCODE_PADDING_EOS);
+ vdec->params.end_flag = 1;
+ vpu_iface_set_decode_params(inst, &vdec->params, 1);
+ vdec->drain = 0;
+ inst_dbg(inst, LVL_FLOW, "append eos\n");
+
+ return 0;
+}
+
+static int vdec_cmd_stop(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ inst_dbg(inst, LVL_FLOW, "stop cmd\n");
+
+ if (inst->state == VPU_CODEC_STATE_DEINIT) {
+ vpu_notify_eos(inst);
+ } else {
+ vdec->drain = 1;
+ vdec_drain(inst);
+ }
+
+ return 0;
+}
+
+static int vdec_cmd_reset(struct vpu_inst *inst)
+{
+ inst_dbg(inst, LVL_FLOW, "reset cmd\n");
+
+ if (inst->state == VPU_CODEC_STATE_DEINIT)
+ return 0;
+
+ if (vb2_is_streaming(v4l2_m2m_get_src_vq(inst->m2m_ctx)))
+ return -EINVAL;
+ if (vb2_is_streaming(v4l2_m2m_get_dst_vq(inst->m2m_ctx)))
+ return -EINVAL;
+ vpu_session_stop(inst);
+
+ return 0;
+}
+
+static int vdec_decoder_cmd(struct file *file,
+ void *fh,
+ struct v4l2_decoder_cmd *cmd)
+{
+ struct vpu_inst *inst = to_inst(file);
+ int ret;
+
+ ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, cmd);
+ if (ret)
+ return ret;
+
+ vpu_inst_lock(inst);
+ switch (cmd->cmd) {
+ case V4L2_DEC_CMD_STOP:
+ vdec_cmd_stop(inst);
+ break;
+ case V4L2_DEC_CMD_RESET:
+ vdec_cmd_reset(inst);
+ break;
+ default:
+ break;
+ }
+ vpu_inst_unlock(inst);
+
+ return 0;
+}
+
+static int vdec_subscribe_event(struct v4l2_fh *fh,
+ const struct v4l2_event_subscription *sub)
+{
+ struct vpu_inst *inst = container_of(fh, struct vpu_inst, fh);
+ struct vdec_t *vdec = inst->priv;
+
+ switch (sub->type) {
+ case V4L2_EVENT_EOS:
+ vdec->eos_subscribed = true;
+ return v4l2_event_subscribe(fh, sub, 0, NULL);
+ case V4L2_EVENT_SOURCE_CHANGE:
+ return v4l2_src_change_event_subscribe(fh, sub);
+ case V4L2_EVENT_CTRL:
+ return v4l2_ctrl_subscribe_event(fh, sub);
+ case V4L2_EVENT_SKIP:
+ case V4L2_EVENT_CODEC_ERROR:
+ return v4l2_event_subscribe(fh, sub, 0, NULL);
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int vdec_unsubscribe_event(struct v4l2_fh *fh,
+ const struct v4l2_event_subscription *sub)
+{
+ struct vpu_inst *inst = container_of(fh, struct vpu_inst, fh);
+ struct vdec_t *vdec = inst->priv;
+ int ret;
+
+ ret = v4l2_event_unsubscribe(fh, sub);
+ if (ret)
+ return ret;
+
+ if (sub->type == V4L2_EVENT_EOS)
+ vdec->eos_subscribed = false;
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops vdec_ioctl_ops = {
+ .vidioc_querycap = vdec_querycap,
+ .vidioc_enum_fmt_vid_cap = vdec_enum_fmt,
+ .vidioc_enum_fmt_vid_out = vdec_enum_fmt,
+ .vidioc_g_fmt_vid_cap_mplane = vdec_g_fmt,
+ .vidioc_g_fmt_vid_out_mplane = vdec_g_fmt,
+ .vidioc_try_fmt_vid_cap_mplane = vdec_try_fmt,
+ .vidioc_try_fmt_vid_out_mplane = vdec_try_fmt,
+ .vidioc_s_fmt_vid_cap_mplane = vdec_s_fmt,
+ .vidioc_s_fmt_vid_out_mplane = vdec_s_fmt,
+ .vidioc_g_selection = vdec_g_selection,
+ .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,
+ .vidioc_decoder_cmd = vdec_decoder_cmd,
+ .vidioc_subscribe_event = vdec_subscribe_event,
+ .vidioc_unsubscribe_event = vdec_unsubscribe_event,
+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
+ .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
+};
+
+static bool vdec_check_ready(struct vpu_inst *inst, unsigned int type)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ if (V4L2_TYPE_IS_OUTPUT(type)) {
+ if (vdec->ts_pre_count >= vdec->frame_depth)
+ return false;
+ return true;
+ }
+
+ if (vdec->req_frame_count || vdec->eos_received)
+ return true;
+
+ return false;
+}
+
+static int vdec_frame_decoded(struct vpu_inst *inst, void *arg)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_dec_pic_info *info = arg;
+ struct vpu_vb2_buffer *vpu_buf;
+ int ret = 0;
+
+ if (!info || info->id >= ARRAY_SIZE(vdec->slots))
+ return -EINVAL;
+
+ vpu_inst_lock(inst);
+ vpu_buf = vdec->slots[info->id];
+ if (!vpu_buf) {
+ inst_err(inst, "decoded invalid frame[%d]\n", info->id);
+ ret = -EINVAL;
+ goto exit;
+ }
+ if (vpu_buf->state == VPU_BUF_STATE_DECODED)
+ inst_dbg(inst, LVL_INFO, "buf[%d] has been decoded\n", info->id);
+ vpu_buf->state = VPU_BUF_STATE_DECODED;
+ vdec->decoded_frame_count++;
+ if (vdec->ts_pre_count >= info->consumed_count)
+ vdec->ts_pre_count -= info->consumed_count;
+ else
+ vdec->ts_pre_count = 0;
+exit:
+ vpu_inst_unlock(inst);
+
+ return ret;
+}
+
+static struct vpu_vb2_buffer *vdec_find_buffer(struct vpu_inst *inst, u32 luma)
+{
+ struct vdec_t *vdec = inst->priv;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vdec->slots); i++) {
+ if (!vdec->slots[i])
+ continue;
+ if (luma == vdec->slots[i]->luma)
+ return vdec->slots[i];
+ }
+
+ return NULL;
+}
+
+static void vdec_buf_done(struct vpu_inst *inst, struct vpu_frame_info *frame)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_vb2_buffer *vpu_buf;
+ struct vb2_v4l2_buffer *vbuf;
+
+ if (!frame)
+ return;
+
+ vpu_inst_lock(inst);
+ vpu_buf = vdec_find_buffer(inst, frame->luma);
+ vpu_inst_unlock(inst);
+ if (!vpu_buf) {
+ inst_err(inst, "can't find buffer, id = %d, addr = 0x%x\n",
+ frame->id, frame->luma);
+ return;
+ }
+ if (frame->skipped) {
+ inst_dbg(inst, LVL_DEBUG, "frame skip\n");
+ vpu_notify_skip(inst);
+ return;
+ }
+
+ vbuf = &vpu_buf->m2m_buf.vb;
+ if (vbuf->vb2_buf.index != frame->id)
+ inst_err(inst, "buffer id(%d, %d) dismatch\n",
+ vbuf->vb2_buf.index, frame->id);
+
+ if (vpu_buf->state != VPU_BUF_STATE_DECODED)
+ inst_err(inst, "buffer(%d) ready without decoded\n", frame->id);
+ vpu_buf->state = VPU_BUF_STATE_READY;
+ vb2_set_plane_payload(&vbuf->vb2_buf, 0, inst->cap_format.sizeimage[0]);
+ vb2_set_plane_payload(&vbuf->vb2_buf, 1, inst->cap_format.sizeimage[1]);
+ vbuf->vb2_buf.timestamp = frame->timestamp;
+ vbuf->field = inst->cap_format.field;
+ inst_dbg(inst, LVL_TS, "[OUTPUT TS]%32lld\n", frame->timestamp);
+
+ v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE);
+ vpu_inst_lock(inst);
+ vdec->timestamp = frame->timestamp;
+ vdec->display_frame_count++;
+ vpu_inst_unlock(inst);
+ inst_dbg(inst, LVL_DEBUG, "decoded : %d, display : %d\n",
+ vdec->decoded_frame_count, vdec->display_frame_count);
+}
+
+static void vdec_stop_done(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ vpu_inst_lock(inst);
+ vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 0);
+ vdec->seq_hdr_found = 0;
+ vpu_inst_unlock(inst);
+}
+
+static bool vdec_check_source_change(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ const struct vpu_format *fmt;
+ int i;
+
+ fmt = vpu_helper_find_format(inst, inst->cap_format.type, vdec->codec_info.pixfmt);
+ if (inst->cap_format.pixfmt != vdec->codec_info.pixfmt)
+ return true;
+ if (inst->cap_format.width != vdec->codec_info.decoded_width)
+ return true;
+ if (inst->cap_format.height != vdec->codec_info.decoded_height)
+ return true;
+ if (vpu_get_num_buffers(inst, inst->cap_format.type) < inst->min_buffer_cap)
+ return true;
+ if (inst->crop.left != vdec->codec_info.offset_x)
+ return true;
+ if (inst->crop.top != vdec->codec_info.offset_y)
+ return true;
+ if (inst->crop.width != vdec->codec_info.width)
+ return true;
+ if (inst->crop.height != vdec->codec_info.height)
+ return true;
+ if (fmt && inst->cap_format.num_planes != fmt->num_planes)
+ return true;
+ for (i = 0; i < inst->cap_format.num_planes; i++) {
+ if (inst->cap_format.bytesperline[i] != vdec->codec_info.bytesperline[i])
+ return true;
+ if (inst->cap_format.sizeimage[i] != vdec->codec_info.sizeimage[i])
+ return true;
+ }
+
+ return false;
+}
+
+static void vdec_init_fmt(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ const struct vpu_format *fmt;
+ int i;
+
+ fmt = vpu_helper_find_format(inst, inst->cap_format.type, vdec->codec_info.pixfmt);
+ inst->out_format.width = vdec->codec_info.width;
+ inst->out_format.height = vdec->codec_info.height;
+ inst->cap_format.width = vdec->codec_info.decoded_width;
+ inst->cap_format.height = vdec->codec_info.decoded_height;
+ inst->cap_format.pixfmt = vdec->codec_info.pixfmt;
+ if (fmt) {
+ inst->cap_format.num_planes = fmt->num_planes;
+ inst->cap_format.flags = fmt->flags;
+ }
+ for (i = 0; i < inst->cap_format.num_planes; i++) {
+ inst->cap_format.bytesperline[i] = vdec->codec_info.bytesperline[i];
+ inst->cap_format.sizeimage[i] = vdec->codec_info.sizeimage[i];
+ }
+ if (vdec->codec_info.progressive)
+ inst->cap_format.field = V4L2_FIELD_NONE;
+ else
+ inst->cap_format.field = V4L2_FIELD_INTERLACED;
+ if (vdec->codec_info.color_primaries == V4L2_COLORSPACE_DEFAULT)
+ vdec->codec_info.color_primaries = V4L2_COLORSPACE_REC709;
+ if (vdec->codec_info.transfer_chars == V4L2_XFER_FUNC_DEFAULT)
+ vdec->codec_info.transfer_chars = V4L2_XFER_FUNC_709;
+ if (vdec->codec_info.matrix_coeffs == V4L2_YCBCR_ENC_DEFAULT)
+ vdec->codec_info.matrix_coeffs = V4L2_YCBCR_ENC_709;
+ if (vdec->codec_info.full_range == V4L2_QUANTIZATION_DEFAULT)
+ vdec->codec_info.full_range = V4L2_QUANTIZATION_LIM_RANGE;
+}
+
+static void vdec_init_crop(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ inst->crop.left = vdec->codec_info.offset_x;
+ inst->crop.top = vdec->codec_info.offset_y;
+ inst->crop.width = vdec->codec_info.width;
+ inst->crop.height = vdec->codec_info.height;
+}
+
+static void vdec_init_mbi(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ vdec->mbi.size = vdec->codec_info.mbi_size;
+ vdec->mbi.max_count = ARRAY_SIZE(vdec->mbi.buffer);
+ scnprintf(vdec->mbi.name, sizeof(vdec->mbi.name), "mbi");
+ vdec->mbi.type = MEM_RES_MBI;
+ vdec->mbi.tag = vdec->seq_tag;
+}
+
+static void vdec_init_dcp(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ vdec->dcp.size = vdec->codec_info.dcp_size;
+ vdec->dcp.max_count = ARRAY_SIZE(vdec->dcp.buffer);
+ scnprintf(vdec->dcp.name, sizeof(vdec->dcp.name), "dcp");
+ vdec->dcp.type = MEM_RES_DCP;
+ vdec->dcp.tag = vdec->seq_tag;
+}
+
+static void vdec_request_one_fs(struct vdec_fs_info *fs)
+{
+ WARN_ON(!fs);
+
+ fs->req_count++;
+ if (fs->req_count > fs->max_count) {
+ vpu_err("error:request %s over %d\n", fs->name, fs->max_count);
+ fs->req_count = fs->max_count;
+ }
+}
+
+static int vdec_alloc_fs_buffer(struct vpu_inst *inst, struct vdec_fs_info *fs)
+{
+ struct vpu_buffer *buffer;
+
+ if (!inst || !fs || !fs->size)
+ return -EINVAL;
+
+ if (fs->count >= fs->req_count)
+ return -EINVAL;
+
+ buffer = &fs->buffer[fs->count];
+ if (buffer->virt && buffer->length >= fs->size)
+ return 0;
+
+ vpu_free_dma(buffer);
+ buffer->length = fs->size;
+ return vpu_alloc_dma(inst->core, buffer);
+}
+
+static void vdec_alloc_fs(struct vpu_inst *inst, struct vdec_fs_info *fs)
+{
+ int ret;
+
+ while (fs->count < fs->req_count) {
+ ret = vdec_alloc_fs_buffer(inst, fs);
+ if (ret)
+ break;
+ fs->count++;
+ }
+}
+
+static void vdec_clear_fs(struct vdec_fs_info *fs)
+{
+ u32 i;
+
+ if (!fs)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(fs->buffer); i++)
+ vpu_free_dma(&fs->buffer[i]);
+ memset(fs, 0, sizeof(*fs));
+}
+
+static int vdec_response_fs(struct vpu_inst *inst, struct vdec_fs_info *fs)
+{
+ struct vpu_fs_info info;
+ int ret;
+
+ if (fs->index >= fs->count)
+ return 0;
+
+ memset(&info, 0, sizeof(info));
+ info.id = fs->index;
+ info.type = fs->type;
+ info.tag = fs->tag;
+ info.luma_addr = fs->buffer[fs->index].phys;
+ info.luma_size = fs->buffer[fs->index].length;
+ ret = vpu_session_alloc_fs(inst, &info);
+ if (ret)
+ return ret;
+
+ fs->index++;
+ return 0;
+}
+
+static int vdec_response_frame_abnormal(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_fs_info info;
+
+ if (!vdec->req_frame_count)
+ return 0;
+
+ memset(&info, 0, sizeof(info));
+ info.type = MEM_RES_FRAME;
+ info.tag = vdec->seq_tag + 0xf0;
+ vpu_session_alloc_fs(inst, &info);
+ vdec->req_frame_count--;
+
+ return 0;
+}
+
+static int vdec_response_frame(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_vb2_buffer *vpu_buf;
+ struct vpu_fs_info info;
+ int ret;
+
+ if (inst->state != VPU_CODEC_STATE_ACTIVE)
+ return -EINVAL;
+
+ if (!vdec->req_frame_count)
+ return -EINVAL;
+
+ if (!vbuf)
+ return -EINVAL;
+
+ if (vdec->slots[vbuf->vb2_buf.index]) {
+ inst_err(inst, "repeat alloc fs %d\n", vbuf->vb2_buf.index);
+ return -EINVAL;
+ }
+
+ inst_dbg(inst, LVL_DEBUG, "inst->state = %d, alloc fs %d, tag = 0x%x\n",
+ inst->state, vbuf->vb2_buf.index, vdec->seq_tag);
+ vpu_buf = to_vpu_vb2_buffer(vbuf);
+
+ memset(&info, 0, sizeof(info));
+ info.id = vbuf->vb2_buf.index;
+ info.type = MEM_RES_FRAME;
+ info.tag = vdec->seq_tag;
+ info.luma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 0);
+ info.luma_size = inst->cap_format.sizeimage[0];
+ info.chroma_addr = vpu_get_vb_phy_addr(&vbuf->vb2_buf, 1);
+ info.chromau_size = inst->cap_format.sizeimage[1];
+ info.bytesperline = inst->cap_format.bytesperline[0];
+ ret = vpu_session_alloc_fs(inst, &info);
+ if (ret)
+ return ret;
+
+ vpu_buf->tag = info.tag;
+ vpu_buf->luma = info.luma_addr;
+ vpu_buf->chroma_u = info.chromau_size;
+ vpu_buf->chroma_v = 0;
+ vpu_buf->state = VPU_BUF_STATE_INUSE;
+ vdec->slots[info.id] = vpu_buf;
+ vdec->req_frame_count--;
+
+ return 0;
+}
+
+static void vdec_response_fs_request(struct vpu_inst *inst, bool force)
+{
+ struct vdec_t *vdec = inst->priv;
+ int i;
+ int ret;
+
+ if (force) {
+ for (i = vdec->req_frame_count; i > 0; i--)
+ vdec_response_frame_abnormal(inst);
+ return;
+ }
+
+ for (i = vdec->req_frame_count; i > 0; i--) {
+ ret = vpu_process_capture_buffer(inst);
+ if (ret)
+ break;
+ if (vdec->eos_received)
+ break;
+ }
+
+ for (i = vdec->mbi.index; i < vdec->mbi.count; i++) {
+ if (vdec_response_fs(inst, &vdec->mbi))
+ break;
+ if (vdec->eos_received)
+ break;
+ }
+ for (i = vdec->dcp.index; i < vdec->dcp.count; i++) {
+ if (vdec_response_fs(inst, &vdec->dcp))
+ break;
+ if (vdec->eos_received)
+ break;
+ }
+}
+
+static void vdec_response_fs_release(struct vpu_inst *inst, u32 id, u32 tag)
+{
+ struct vpu_fs_info info;
+
+ memset(&info, 0, sizeof(info));
+ info.id = id;
+ info.tag = tag;
+ vpu_session_release_fs(inst, &info);
+}
+
+static void vdec_recycle_buffer(struct vpu_inst *inst, struct vb2_v4l2_buffer *vbuf)
+{
+ if (!inst || !vbuf)
+ return;
+
+ if (vbuf->vb2_buf.state != VB2_BUF_STATE_ACTIVE)
+ return;
+ if (vpu_find_buf_by_idx(inst, vbuf->vb2_buf.type, vbuf->vb2_buf.index))
+ return;
+ v4l2_m2m_buf_queue(inst->m2m_ctx, vbuf);
+}
+
+static void vdec_clear_slots(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_vb2_buffer *vpu_buf;
+ struct vb2_v4l2_buffer *vbuf;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vdec->slots); i++) {
+ if (!vdec->slots[i])
+ continue;
+
+ vpu_buf = vdec->slots[i];
+ vbuf = &vpu_buf->m2m_buf.vb;
+ if (vpu_buf->tag == vdec->seq_tag)
+ inst_dbg(inst, LVL_WARN, "clear slot[%d], %d, %d\n",
+ i,
+ vdec->slots[i]->state,
+ vbuf->vb2_buf.state);
+
+ vdec_response_fs_release(inst, i, vpu_buf->tag);
+ vdec_recycle_buffer(inst, vbuf);
+ vdec->slots[i]->state = VPU_BUF_STATE_IDLE;
+ vdec->slots[i] = NULL;
+ }
+}
+
+static void vdec_event_seq_hdr(struct vpu_inst *inst,
+ struct vpu_dec_codec_info *hdr)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ vpu_inst_lock(inst);
+ memcpy(&vdec->codec_info, hdr, sizeof(vdec->codec_info));
+
+ inst_dbg(inst, LVL_FLOW, "%d x %d, crop : (%d, %d) %d x %d\n",
+ vdec->codec_info.decoded_width,
+ vdec->codec_info.decoded_height,
+ vdec->codec_info.offset_x,
+ vdec->codec_info.offset_y,
+ vdec->codec_info.width,
+ vdec->codec_info.height);
+ inst->min_buffer_cap = hdr->num_ref_frms + hdr->num_dpb_frms;
+ vdec->is_source_changed = vdec_check_source_change(inst);
+ vdec_init_fmt(inst);
+ vdec_init_crop(inst);
+ vdec_init_mbi(inst);
+ vdec_init_dcp(inst);
+ if (!vdec->seq_hdr_found) {
+ vdec->seq_tag = vdec->codec_info.tag;
+ if (vdec->is_source_changed) {
+ vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
+ vpu_notify_source_change(inst);
+ vdec->is_source_changed = false;
+ }
+ }
+ if (vdec->seq_tag != vdec->codec_info.tag) {
+ vdec_response_fs_request(inst, true);
+ inst_dbg(inst, LVL_DEBUG, "seq tag change: %d -> %d\n",
+ vdec->seq_tag, vdec->codec_info.tag);
+ }
+ vdec->seq_hdr_found++;
+ vpu_inst_unlock(inst);
+}
+
+static void vdec_event_resolution_change(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ inst_dbg(inst, LVL_FLOW, "resolution change\n");
+ vpu_inst_lock(inst);
+ vdec->seq_tag = vdec->codec_info.tag;
+ vdec_clear_fs(&vdec->mbi);
+ vdec_clear_fs(&vdec->dcp);
+ vdec_clear_slots(inst);
+ vdec_init_mbi(inst);
+ vdec_init_dcp(inst);
+ if (vdec->is_source_changed) {
+ vdec_update_state(inst, VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE, 0);
+ vdec->source_change++;
+ vdec_handle_resolution_change(inst);
+ vdec->is_source_changed = false;
+ }
+ vpu_inst_unlock(inst);
+}
+
+static void vdec_event_req_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ if (!fs)
+ return;
+
+ vpu_inst_lock(inst);
+
+ switch (fs->type) {
+ case MEM_RES_FRAME:
+ vdec->req_frame_count++;
+ break;
+ case MEM_RES_MBI:
+ vdec_request_one_fs(&vdec->mbi);
+ break;
+ case MEM_RES_DCP:
+ vdec_request_one_fs(&vdec->dcp);
+ break;
+ default:
+ break;
+ }
+
+ vdec_alloc_fs(inst, &vdec->mbi);
+ vdec_alloc_fs(inst, &vdec->dcp);
+
+ vdec_response_fs_request(inst, false);
+
+ vpu_inst_unlock(inst);
+}
+
+static void vdec_evnet_rel_fs(struct vpu_inst *inst, struct vpu_fs_info *fs)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_vb2_buffer *vpu_buf;
+ struct vb2_v4l2_buffer *vbuf;
+
+ if (!fs || fs->id >= ARRAY_SIZE(vdec->slots))
+ return;
+ if (fs->type != MEM_RES_FRAME)
+ return;
+
+ if (fs->id >= vpu_get_num_buffers(inst, inst->cap_format.type)) {
+ inst_err(inst, "invalid fs(%d) to release\n", fs->id);
+ return;
+ }
+
+ vpu_inst_lock(inst);
+ vpu_buf = vdec->slots[fs->id];
+ vdec->slots[fs->id] = NULL;
+
+ if (!vpu_buf) {
+ inst_dbg(inst, LVL_DEBUG, "fs[%d] has bee released\n", fs->id);
+ goto exit;
+ }
+
+ if (vpu_buf->state == VPU_BUF_STATE_DECODED) {
+ inst_dbg(inst, LVL_DEBUG, "this frame is skipped\n");
+ vpu_notify_skip(inst);
+ }
+
+ vdec_response_fs_release(inst, fs->id, vpu_buf->tag);
+ vbuf = &vpu_buf->m2m_buf.vb;
+ if (vpu_buf->state != VPU_BUF_STATE_READY)
+ vdec_recycle_buffer(inst, vbuf);
+
+ vpu_buf->state = VPU_BUF_STATE_IDLE;
+ vpu_process_capture_buffer(inst);
+
+exit:
+ vpu_inst_unlock(inst);
+}
+
+static void vdec_event_eos(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ inst_dbg(inst, LVL_FLOW, "eos\n");
+ vpu_inst_lock(inst);
+ vdec->eos_received++;
+ vdec_update_state(inst, VPU_CODEC_STATE_DRAIN, 0);
+ vpu_process_capture_buffer(inst);
+ vdec_handle_eos(inst);
+ vpu_inst_unlock(inst);
+}
+
+static void vdec_event_notify(struct vpu_inst *inst, u32 event, void *data)
+{
+ switch (event) {
+ case VPU_MSG_ID_SEQ_HDR_FOUND:
+ vdec_event_seq_hdr(inst, data);
+ break;
+ case VPU_MSG_ID_RES_CHANGE:
+ vdec_event_resolution_change(inst);
+ break;
+ case VPU_MSG_ID_FRAME_REQ:
+ vdec_event_req_fs(inst, data);
+ break;
+ case VPU_MSG_ID_FRAME_RELEASE:
+ vdec_evnet_rel_fs(inst, data);
+ break;
+ case VPU_MSG_ID_PIC_EOS:
+ vdec_event_eos(inst);
+ break;
+ default:
+ break;
+ }
+}
+
+static int vdec_process_output(struct vpu_inst *inst, struct vb2_buffer *vb)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vb2_v4l2_buffer *vbuf;
+ struct vpu_vb2_buffer *vpu_buf;
+ struct vpu_rpc_buffer_desc desc;
+ s64 timestamp;
+ u32 free_space;
+ int ret;
+
+ vbuf = to_vb2_v4l2_buffer(vb);
+ vpu_buf = to_vpu_vb2_buffer(vbuf);
+ inst_dbg(inst, LVL_DEBUG, "dec output [%d] %d : %ld\n",
+ vbuf->sequence, vb->index, vb2_get_plane_payload(vb, 0));
+
+ if (inst->state == VPU_CODEC_STATE_DEINIT)
+ return -EINVAL;
+
+ if (inst->state == VPU_CODEC_STATE_STARTED)
+ vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0);
+
+ ret = vpu_iface_get_stream_buffer_desc(inst, &desc);
+ if (ret)
+ return ret;
+
+ free_space = vpu_helper_get_free_space(inst);
+ if (free_space < vb2_get_plane_payload(vb, 0) + 0x40000)
+ return -ENOMEM;
+
+ timestamp = vb->timestamp;
+ if (timestamp >= 0 && vdec->ts_start < 0)
+ vdec->ts_start = timestamp;
+ if (vdec->ts_input < timestamp)
+ vdec->ts_input = timestamp;
+
+ ret = vpu_iface_input_frame(inst, vb);
+ if (ret < 0)
+ return -ENOMEM;
+
+ inst_dbg(inst, LVL_TS, "[INPUT TS]%32lld\n", vb->timestamp);
+ vdec->ts_pre_count++;
+ vdec->params.frame_count++;
+
+ v4l2_m2m_src_buf_remove_by_buf(inst->m2m_ctx, vbuf);
+ vpu_buf->state = VPU_BUF_STATE_IDLE;
+ v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE);
+
+ if (vdec->drain)
+ vdec_drain(inst);
+
+ return 0;
+}
+
+static int vdec_process_capture(struct vpu_inst *inst, struct vb2_buffer *vb)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vb2_v4l2_buffer *vbuf;
+ int ret;
+
+ if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ return -EINVAL;
+
+ vbuf = to_vb2_v4l2_buffer(vb);
+
+ if (vdec->eos_received) {
+ if (vdec->eos_subscribed) {
+ vdec_handle_eos(inst);
+ } else {
+ vb2_set_plane_payload(vb, 0, 0);
+ vb2_set_plane_payload(vb, 1, 0);
+ vbuf->flags |= V4L2_BUF_FLAG_LAST;
+ v4l2_m2m_dst_buf_remove_by_buf(inst->m2m_ctx, vbuf);
+ v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE);
+ vdec->eos_received--;
+ }
+ return 0;
+ }
+
+ ret = vdec_response_frame(inst, vbuf);
+ if (ret)
+ return ret;
+ v4l2_m2m_dst_buf_remove_by_buf(inst->m2m_ctx, vbuf);
+ return 0;
+}
+
+static void vdec_on_queue_emtpy(struct vpu_inst *inst, u32 type)
+{
+ if (V4L2_TYPE_IS_OUTPUT(type))
+ return;
+
+ vdec_handle_resolution_change(inst);
+ vdec_handle_eos(inst);
+}
+
+static void vdec_abort(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ struct vpu_rpc_buffer_desc desc;
+ int ret;
+
+ inst_dbg(inst, LVL_FLOW, "abort, inst->state = %d\n", inst->state);
+ vpu_iface_add_scode(inst, SCODE_PADDING_ABORT);
+ vdec->params.end_flag = 1;
+ vpu_iface_set_decode_params(inst, &vdec->params, 1);
+
+ vpu_session_abort(inst);
+
+ ret = vpu_iface_get_stream_buffer_desc(inst, &desc);
+ if (!ret)
+ vpu_iface_update_stream_buffer(inst, desc.rptr, 1);
+
+ vpu_session_rst_buf(inst);
+ inst_dbg(inst, LVL_FLOW, "input : %d, decoded : %d, display : %d\n",
+ vdec->params.frame_count,
+ vdec->decoded_frame_count,
+ vdec->display_frame_count);
+ vdec->params.end_flag = 0;
+ vdec->drain = 0;
+ vdec->ts_pre_count = 0;
+ vdec->timestamp = VPU_INVALID_TIMESTAMP;
+ vdec->ts_start = VPU_INVALID_TIMESTAMP;
+ vdec->ts_input = VPU_INVALID_TIMESTAMP;
+ vdec->params.frame_count = 0;
+ vdec->decoded_frame_count = 0;
+ vdec->display_frame_count = 0;
+}
+
+static void vdec_release(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ inst_dbg(inst, LVL_FLOW, "release\n");
+ vpu_inst_lock(inst);
+ vdec_clear_slots(inst);
+ if (inst->state != VPU_CODEC_STATE_DEINIT)
+ vpu_session_stop(inst);
+ vdec_clear_fs(&vdec->mbi);
+ vdec_clear_fs(&vdec->dcp);
+ vpu_free_dma(&vdec->udata);
+ vpu_free_dma(&inst->stream_buffer);
+ vdec_update_state(inst, VPU_CODEC_STATE_DEINIT, 1);
+ vpu_inst_unlock(inst);
+}
+
+static void vdec_cleanup(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec;
+
+ if (!inst)
+ return;
+
+ vdec = inst->priv;
+ if (vdec)
+ vfree(vdec);
+ inst->priv = NULL;
+ vfree(inst);
+}
+
+static void vdec_init_params(struct vdec_t *vdec)
+{
+ vdec->params.frame_count = 0;
+ vdec->params.end_flag = 0;
+}
+
+static int vdec_start(struct vpu_inst *inst)
+{
+ struct vdec_t *vdec = inst->priv;
+ int stream_buffer_size;
+ int ret;
+
+ if (inst->state != VPU_CODEC_STATE_DEINIT)
+ return 0;
+
+ inst_dbg(inst, LVL_FLOW, "start\n");
+ vdec->udata.length = 0x1000;
+ ret = vpu_alloc_dma(inst->core, &vdec->udata);
+ if (ret) {
+ inst_err(inst, "alloc udata fail\n");
+ goto error;
+ }
+
+ vpu_iface_init_instance(inst);
+ stream_buffer_size = vpu_iface_get_stream_buffer_size(inst->core);
+ if (stream_buffer_size > 0) {
+ inst->stream_buffer.length = stream_buffer_size;
+ ret = vpu_alloc_dma(inst->core, &inst->stream_buffer);
+ if (ret) {
+ inst_err(inst, "alloc stream buffer fail\n");
+ goto error;
+ }
+ inst->use_stream_buffer = true;
+ vpu_iface_config_stream_buffer(inst, &inst->stream_buffer);
+ }
+
+ vdec->params.udata.base = vdec->udata.phys;
+ vdec->params.udata.size = vdec->udata.length;
+ ret = vpu_iface_set_decode_params(inst, &vdec->params, 0);
+ if (ret) {
+ inst_err(inst, "set decode params fail\n");
+ goto error;
+ }
+
+ vdec_init_params(vdec);
+ ret = vpu_session_start(inst);
+ if (ret) {
+ inst_err(inst, "start fail\n");
+ goto error;
+ }
+
+ vdec_update_state(inst, VPU_CODEC_STATE_STARTED, 0);
+
+ return 0;
+error:
+ vpu_free_dma(&vdec->udata);
+ vpu_free_dma(&inst->stream_buffer);
+ return ret;
+}
+
+static int vdec_start_session(struct vpu_inst *inst, u32 type)
+{
+ struct vdec_t *vdec = inst->priv;
+ int ret = 0;
+
+ if (inst->state == VPU_CODEC_STATE_DEINIT) {
+ if (V4L2_TYPE_IS_OUTPUT(type)) {
+ ret = vdec_start(inst);
+ if (ret)
+ return ret;
+ }
+ }
+
+ if (V4L2_TYPE_IS_OUTPUT(type)) {
+ if (inst->state == VPU_CODEC_STATE_SEEK)
+ vdec_update_state(inst, vdec->state, 1);
+ vdec->eos_received = 0;
+ vpu_process_output_buffer(inst);
+ } else {
+ if (inst->state == VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ vdec_update_state(inst, VPU_CODEC_STATE_ACTIVE, 0);
+ vpu_process_capture_buffer(inst);
+ }
+ if (inst->state == VPU_CODEC_STATE_ACTIVE)
+ vdec_response_fs_request(inst, false);
+
+ return ret;
+}
+
+static int vdec_stop_session(struct vpu_inst *inst, u32 type)
+{
+ struct vdec_t *vdec = inst->priv;
+
+ if (inst->state == VPU_CODEC_STATE_DEINIT)
+ return 0;
+
+ if (V4L2_TYPE_IS_OUTPUT(type)) {
+ vdec_update_state(inst, VPU_CODEC_STATE_SEEK, 0);
+ vdec->drain = 0;
+ } else {
+ if (inst->state != VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE)
+ vdec_abort(inst);
+
+ vdec->eos_received = 0;
+ vdec_clear_slots(inst);
+ }
+
+ return 0;
+}
+
+static int vdec_get_debug_info(struct vpu_inst *inst, char *str, u32 size, u32 i)
+{
+ struct vdec_t *vdec = inst->priv;
+ int num = -1;
+
+ switch (i) {
+ case 0:
+ num = scnprintf(str, size,
+ "req_frame_count = %d\ninterlaced = %d\n",
+ vdec->req_frame_count,
+ vdec->codec_info.progressive ? 0 : 1);
+ break;
+ case 1:
+ num = scnprintf(str, size,
+ "mbi: size = 0x%x request = %d, alloc = %d, response = %d\n",
+ vdec->mbi.size,
+ vdec->mbi.req_count,
+ vdec->mbi.count,
+ vdec->mbi.index);
+ break;
+ case 2:
+ num = scnprintf(str, size,
+ "dcp: size = 0x%x request = %d, alloc = %d, response = %d\n",
+ vdec->dcp.size,
+ vdec->dcp.req_count,
+ vdec->dcp.count,
+ vdec->dcp.index);
+ break;
+ case 3:
+ num = scnprintf(str, size, "input_frame_count = %d\n", vdec->params.frame_count);
+ break;
+ case 4:
+ num = scnprintf(str, size, "decoded_frame_count = %d\n", vdec->decoded_frame_count);
+ break;
+ case 5:
+ num = scnprintf(str, size, "display_frame_count = %d\n", vdec->display_frame_count);
+ break;
+ case 6:
+ num = scnprintf(str, size, "drain = %d, eos = %d, source_change = %d\n",
+ vdec->drain, vdec->eos_received, vdec->source_change);
+ break;
+ case 7:
+ num = scnprintf(str, size, "ts_pre_count = %d, frame_depth = %d\n",
+ vdec->ts_pre_count, vdec->frame_depth);
+ break;
+ case 8:
+ num = scnprintf(str, size, "b_dis_reorder = %d, b_non_frame = %d\n",
+ vdec->params.b_dis_reorder,
+ vdec->params.b_non_frame);
+ break;
+ case 9:
+ {
+ s64 timestamp = vdec->timestamp;
+ s64 ts_start = vdec->ts_start;
+ s64 ts_input = vdec->ts_input;
+
+ num = scnprintf(str, size, "timestamp = %9lld.%09lld(%9lld.%09lld, %9lld.%09lld)\n",
+ timestamp / NSEC_PER_SEC,
+ timestamp % NSEC_PER_SEC,
+ ts_start / NSEC_PER_SEC,
+ ts_start % NSEC_PER_SEC,
+ ts_input / NSEC_PER_SEC,
+ ts_input % NSEC_PER_SEC);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return num;
+}
+
+static struct vpu_inst_ops vdec_inst_ops = {
+ .ctrl_init = vdec_ctrl_init,
+ .check_ready = vdec_check_ready,
+ .buf_done = vdec_buf_done,
+ .get_one_frame = vdec_frame_decoded,
+ .stop_done = vdec_stop_done,
+ .event_notify = vdec_event_notify,
+ .release = vdec_release,
+ .cleanup = vdec_cleanup,
+ .start = vdec_start_session,
+ .stop = vdec_stop_session,
+ .process_output = vdec_process_output,
+ .process_capture = vdec_process_capture,
+ .on_queue_empty = vdec_on_queue_emtpy,
+ .get_debug_info = vdec_get_debug_info,
+ .wait_prepare = vpu_inst_unlock,
+ .wait_finish = vpu_inst_lock,
+};
+
+static void vdec_init(struct file *file)
+{
+ struct vpu_inst *inst = to_inst(file);
+ struct vdec_t *vdec;
+ struct v4l2_format f;
+
+ vdec = inst->priv;
+ vdec->frame_depth = VDEC_FRAME_DEPTH;
+ vdec->timestamp = VPU_INVALID_TIMESTAMP;
+ vdec->ts_start = VPU_INVALID_TIMESTAMP;
+ vdec->ts_input = VPU_INVALID_TIMESTAMP;
+
+ memset(&f, 0, sizeof(f));
+ f.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+ f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264;
+ f.fmt.pix_mp.width = 1280;
+ f.fmt.pix_mp.height = 720;
+ f.fmt.pix_mp.field = V4L2_FIELD_NONE;
+ vdec_s_fmt(file, &inst->fh, &f);
+
+ memset(&f, 0, sizeof(f));
+ f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12;
+ f.fmt.pix_mp.width = 1280;
+ f.fmt.pix_mp.height = 720;
+ f.fmt.pix_mp.field = V4L2_FIELD_NONE;
+ vdec_s_fmt(file, &inst->fh, &f);
+}
+
+int vdec_open(struct file *file)
+{
+ struct vpu_inst *inst;
+ struct vdec_t *vdec;
+ int ret;
+
+ inst = vzalloc(sizeof(*inst));
+ if (!inst)
+ return -ENOMEM;
+
+ vdec = vzalloc(sizeof(*vdec));
+ if (!vdec) {
+ vfree(inst);
+ return -ENOMEM;
+ }
+
+ inst->ops = &vdec_inst_ops;
+ inst->formats = vdec_formats;
+ inst->type = VPU_CORE_TYPE_DEC;
+ inst->priv = vdec;
+
+ ret = vpu_v4l2_open(file, inst);
+ if (ret) {
+ vdec_cleanup(inst);
+ return ret;
+ }
+
+ vdec_init(file);
+
+ return 0;
+}
+
+__poll_t vdec_poll(struct file *file, poll_table *wait)
+{
+ struct vpu_inst *inst = to_inst(file);
+ struct vb2_queue *src_q, *dst_q;
+ __poll_t ret;
+
+ ret = v4l2_m2m_fop_poll(file, wait);
+ src_q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
+ dst_q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
+ if (vb2_is_streaming(src_q) && !vb2_is_streaming(dst_q))
+ ret &= (~EPOLLERR);
+
+ return ret;
+}
+
+static const struct v4l2_file_operations vdec_fops = {
+ .owner = THIS_MODULE,
+ .open = vdec_open,
+ .release = vpu_v4l2_close,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vdec_poll,
+ .mmap = v4l2_m2m_fop_mmap,
+};
+
+int vdec_create_video_device(struct vpu_dev *vpu)
+{
+ struct video_device *vdec;
+ int ret;
+
+ if (!vpu)
+ return -EINVAL;
+
+ if (vpu->vdev_dec)
+ return 0;
+
+ vdec = video_device_alloc();
+ if (!vdec) {
+ vpu_err("alloc vpu decoder video device fail\n");
+ return -ENOMEM;
+ }
+ strscpy(vdec->name, "imx-vpu-decoder", sizeof(vdec->name));
+ vdec->release = video_device_release;
+ vdec->fops = &vdec_fops;
+ vdec->ioctl_ops = &vdec_ioctl_ops;
+ vdec->vfl_dir = VFL_DIR_M2M;
+ vdec->v4l2_dev = &vpu->v4l2_dev;
+ vdec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
+
+ ret = video_register_device(vdec, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ video_device_release(vdec);
+ return ret;
+ }
+ video_set_drvdata(vdec, vpu);
+ vpu->vdev_dec = vdec;
+
+ return 0;
+}
--
2.32.0
This part implements the malone decoder rpc interface.
Signed-off-by: Ming Qian <[email protected]>
Signed-off-by: Shijie Qin <[email protected]>
Signed-off-by: Zhou Peng <[email protected]>
---
.../media/platform/imx/vpu-8q/vpu_malone.c | 1744 +++++++++++++++++
.../media/platform/imx/vpu-8q/vpu_malone.h | 51 +
2 files changed, 1795 insertions(+)
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c
create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h
diff --git a/drivers/media/platform/imx/vpu-8q/vpu_malone.c b/drivers/media/platform/imx/vpu-8q/vpu_malone.c
new file mode 100644
index 000000000000..be67b491494f
--- /dev/null
+++ b/drivers/media/platform/imx/vpu-8q/vpu_malone.c
@@ -0,0 +1,1744 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020-2021 NXP
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define TAG "MALONE"
+#include <linux/init.h>
+#include <linux/interconnect.h>
+#include <linux/ioctl.h>
+#include <linux/list.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/videobuf2-dma-contig.h>
+#include <linux/videodev2.h>
+#include <linux/imx_vpu.h>
+#include "vpu.h"
+#include "vpu_rpc.h"
+#include "vpu_defs.h"
+#include "vpu_helpers.h"
+#include "vpu_cmds.h"
+#include "vpu_log.h"
+#include "vpu_imx8q.h"
+#include "vpu_malone.h"
+
+#define CMD_SIZE 25600
+#define MSG_SIZE 25600
+#define CODEC_SIZE 0x1000
+#define JPEG_SIZE 0x1000
+#define SEQ_SIZE 0x1000
+#define GOP_SIZE 0x1000
+#define PIC_SIZE 0x1000
+#define QMETER_SIZE 0x1000
+#define DBGLOG_SIZE 0x10000
+#define DEBUG_SIZE 0x80000
+#define ENG_SIZE 0x1000
+#define MALONE_SKIPPED_FRAME_ID 0x555
+
+#define MALONE_TILE_W 8
+#define MALONE_TILE_H 128
+#define MALONE_ALIGN_W (MALONE_TILE_W * 1)
+#define MALONE_ALIGN_H (MALONE_TILE_H * 2)
+#define MALONE_ALIGN_LINE (256)
+#define MALONE_ALIGN_MBI 0x800
+#define MALONE_DCP_CHUNK_BIT 16
+#define MALONE_DCP_SIZE_MAX 0x3000000
+#define MALONE_DCP_SIZE_MIN 0x100000
+#define MALONE_DCP_FIXED_MB_ALLOC 250
+
+#define CONFIG_SET(val, cfg, pos, mask) \
+ (*(cfg) |= (((val) << (pos)) & (mask)))
+//x means source data , y means destination data
+#define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F)
+#define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300)
+#define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400)
+#define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800)
+#define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000)
+#define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000)
+#define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000)
+#define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000)
+#define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000)
+#define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000)
+#define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000)
+#define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000)
+#define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000)
+#define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000)
+#define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000)
+#define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000)
+#define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000)
+#define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000)
+
+enum vpu_malone_stream_input_mode {
+ INVALID_MODE = 0,
+ FRAME_LVL,
+ NON_FRAME_LVL
+};
+
+enum vpu_malone_format {
+ MALONE_FMT_NULL = 0x0,
+ MALONE_FMT_AVC = 0x1,
+ MALONE_FMT_MP2 = 0x2,
+ MALONE_FMT_VC1 = 0x3,
+ MALONE_FMT_AVS = 0x4,
+ MALONE_FMT_ASP = 0x5,
+ MALONE_FMT_JPG = 0x6,
+ MALONE_FMT_RV = 0x7,
+ MALONE_FMT_VP6 = 0x8,
+ MALONE_FMT_SPK = 0x9,
+ MALONE_FMT_VP8 = 0xA,
+ MALONE_FMT_HEVC = 0xB,
+ MALONE_FMT_LAST = MALONE_FMT_HEVC
+};
+
+enum {
+ VID_API_CMD_NULL = 0x00,
+ VID_API_CMD_PARSE_NEXT_SEQ = 0x01,
+ VID_API_CMD_PARSE_NEXT_I = 0x02,
+ VID_API_CMD_PARSE_NEXT_IP = 0x03,
+ VID_API_CMD_PARSE_NEXT_ANY = 0x04,
+ VID_API_CMD_DEC_PIC = 0x05,
+ VID_API_CMD_UPDATE_ES_WR_PTR = 0x06,
+ VID_API_CMD_UPDATE_ES_RD_PTR = 0x07,
+ VID_API_CMD_UPDATE_UDATA = 0x08,
+ VID_API_CMD_GET_FSINFO = 0x09,
+ VID_API_CMD_SKIP_PIC = 0x0a,
+ VID_API_CMD_DEC_CHUNK = 0x0b,
+ VID_API_CMD_START = 0x10,
+ VID_API_CMD_STOP = 0x11,
+ VID_API_CMD_ABORT = 0x12,
+ VID_API_CMD_RST_BUF = 0x13,
+ VID_API_CMD_FS_RELEASE = 0x15,
+ VID_API_CMD_MEM_REGION_ATTACH = 0x16,
+ VID_API_CMD_MEM_REGION_DETACH = 0x17,
+ VID_API_CMD_MVC_VIEW_SELECT = 0x18,
+ VID_API_CMD_FS_ALLOC = 0x19,
+ VID_API_CMD_DBG_GET_STATUS = 0x1C,
+ VID_API_CMD_DBG_START_LOG = 0x1D,
+ VID_API_CMD_DBG_STOP_LOG = 0x1E,
+ VID_API_CMD_DBG_DUMP_LOG = 0x1F,
+ VID_API_CMD_YUV_READY = 0x20,
+ VID_API_CMD_TS = 0x21,
+
+ VID_API_CMD_FIRM_RESET = 0x40,
+
+ VID_API_CMD_SNAPSHOT = 0xAA,
+ VID_API_CMD_ROLL_SNAPSHOT = 0xAB,
+ VID_API_CMD_LOCK_SCHEDULER = 0xAC,
+ VID_API_CMD_UNLOCK_SCHEDULER = 0xAD,
+ VID_API_CMD_CQ_FIFO_DUMP = 0xAE,
+ VID_API_CMD_DBG_FIFO_DUMP = 0xAF,
+ VID_API_CMD_SVC_ILP = 0xBB,
+ VID_API_CMD_FW_STATUS = 0xF0,
+ VID_API_CMD_INVALID = 0xFF
+};
+
+enum {
+ VID_API_EVENT_NULL = 0x00,
+ VID_API_EVENT_RESET_DONE = 0x01,
+ VID_API_EVENT_SEQ_HDR_FOUND = 0x02,
+ VID_API_EVENT_PIC_HDR_FOUND = 0x03,
+ VID_API_EVENT_PIC_DECODED = 0x04,
+ VID_API_EVENT_FIFO_LOW = 0x05,
+ VID_API_EVENT_FIFO_HIGH = 0x06,
+ VID_API_EVENT_FIFO_EMPTY = 0x07,
+ VID_API_EVENT_FIFO_FULL = 0x08,
+ VID_API_EVENT_BS_ERROR = 0x09,
+ VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A,
+ VID_API_EVENT_RES_CHANGE = 0x0B,
+ VID_API_EVENT_FIFO_OVF = 0x0C,
+ VID_API_EVENT_CHUNK_DECODED = 0x0D,
+ VID_API_EVENT_REQ_FRAME_BUFF = 0x10,
+ VID_API_EVENT_FRAME_BUFF_RDY = 0x11,
+ VID_API_EVENT_REL_FRAME_BUFF = 0x12,
+ VID_API_EVENT_STR_BUF_RST = 0x13,
+ VID_API_EVENT_RET_PING = 0x14,
+ VID_API_EVENT_QMETER = 0x15,
+ VID_API_EVENT_STR_FMT_CHANGE = 0x16,
+ VID_API_EVENT_FIRMWARE_XCPT = 0x17,
+ VID_API_EVENT_START_DONE = 0x18,
+ VID_API_EVENT_STOPPED = 0x19,
+ VID_API_EVENT_ABORT_DONE = 0x1A,
+ VID_API_EVENT_FINISHED = 0x1B,
+ VID_API_EVENT_DBG_STAT_UPDATE = 0x1C,
+ VID_API_EVENT_DBG_LOG_STARTED = 0x1D,
+ VID_API_EVENT_DBG_LOG_STOPPED = 0x1E,
+ VID_API_EVENT_DBG_LOG_UPDATED = 0x1F,
+ VID_API_EVENT_DBG_MSG_DEC = 0x20,
+ VID_API_EVENT_DEC_SC_ERR = 0x21,
+ VID_API_EVENT_CQ_FIFO_DUMP = 0x22,
+ VID_API_EVENT_DBG_FIFO_DUMP = 0x23,
+ VID_API_EVENT_DEC_CHECK_RES = 0x24,
+ VID_API_EVENT_DEC_CFG_INFO = 0x25,
+ VID_API_EVENT_UNSUPPORTED_STREAM = 0x26,
+ VID_API_EVENT_STR_SUSPENDED = 0x30,
+ VID_API_EVENT_SNAPSHOT_DONE = 0x40,
+ VID_API_EVENT_FW_STATUS = 0xF0,
+ VID_API_EVENT_INVALID = 0xFF
+};
+
+struct vpu_malone_buffer_desc {
+ struct vpu_rpc_buffer_desc buffer;
+ u32 low;
+ u32 high;
+};
+
+struct vpu_malone_str_buffer {
+ u32 wptr;
+ u32 rptr;
+ u32 start;
+ u32 end;
+ u32 lwm;
+};
+
+struct vpu_malone_picth_info {
+ u32 frame_pitch;
+};
+
+struct vpu_malone_table_desc {
+ u32 array_base;
+ u32 size;
+};
+
+struct vpu_malone_dbglog_desc {
+ u32 addr;
+ u32 size;
+ u32 level;
+ u32 reserved;
+};
+
+struct vpu_malone_frame_buffer {
+ u32 addr;
+ u32 size;
+};
+
+struct vpu_malone_udata {
+ u32 base;
+ u32 total_size;
+ u32 slot_size;
+};
+
+struct vpu_malone_buffer_info {
+ u32 stream_input_mode;
+ u32 stream_pic_input_count;
+ u32 stream_pic_parsed_count;
+ u32 stream_buffer_threshold;
+ u32 stream_pic_end_flag;
+};
+
+struct vpu_malone_encrypt_info {
+ u32 rec4key[8];
+ u32 obfusc;
+};
+
+struct malone_iface {
+ u32 exec_base_addr;
+ u32 exec_area_size;
+ struct vpu_malone_buffer_desc cmd_buffer_desc;
+ struct vpu_malone_buffer_desc msg_buffer_desc;
+ u32 cmd_int_enable[VID_API_NUM_STREAMS];
+ struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
+ u32 stream_config[VID_API_NUM_STREAMS];
+ struct vpu_malone_table_desc codec_param_tab_desc;
+ struct vpu_malone_table_desc jpeg_param_tab_desc;
+ u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
+ struct vpu_malone_table_desc seq_info_tab_desc;
+ struct vpu_malone_table_desc pic_info_tab_desc;
+ struct vpu_malone_table_desc gop_info_tab_desc;
+ struct vpu_malone_table_desc qmeter_info_tab_desc;
+ u32 stream_error[VID_API_NUM_STREAMS];
+ u32 fw_version;
+ u32 fw_offset;
+ u32 max_streams;
+ struct vpu_malone_dbglog_desc dbglog_desc;
+ struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
+ struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
+ struct vpu_malone_buffer_desc debug_buffer_desc;
+ struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
+ u32 encrypt_info[VID_API_NUM_STREAMS];
+ struct vpu_rpc_system_config system_cfg;
+ u32 api_version;
+ struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
+};
+
+struct malone_jpg_params {
+ u32 rotation_angle;
+ u32 horiz_scale_factor;
+ u32 vert_scale_factor;
+ u32 rotation_mode;
+ u32 rgb_mode;
+ u32 chunk_mode; /* 0 ~ 1 */
+ u32 last_chunk; /* 0 ~ 1 */
+ u32 chunk_rows; /* 0 ~ 255 */
+ u32 num_bytes;
+ u32 jpg_crop_x;
+ u32 jpg_crop_y;
+ u32 jpg_crop_width;
+ u32 jpg_crop_height;
+ u32 jpg_mjpeg_mode;
+ u32 jpg_mjpeg_interlaced;
+};
+
+struct malone_codec_params {
+ u32 disp_imm;
+ u32 fourcc;
+ u32 codec_version;
+ u32 frame_rate;
+ u32 dbglog_enable;
+ u32 bsdma_lwm;
+ u32 bbd_coring;
+ u32 bbd_s_thr_row;
+ u32 bbd_p_thr_row;
+ u32 bbd_s_thr_logo_row;
+ u32 bbd_p_thr_logo_row;
+ u32 bbd_s_thr_col;
+ u32 bbd_p_thr_col;
+ u32 bbd_chr_thr_row;
+ u32 bbd_chr_thr_col;
+ u32 bbd_uv_mid_level;
+ u32 bbd_excl_win_mb_left;
+ u32 bbd_excl_win_mb_right;
+};
+
+struct malone_padding_scode {
+ u32 scode_type;
+ u32 pixelformat;
+ u32 data[2];
+};
+
+struct malone_fmt_mapping {
+ u32 pixelformat;
+ enum vpu_malone_format malone_format;
+};
+
+struct malone_scode_t {
+ struct vpu_inst *inst;
+ struct vb2_buffer *vb;
+ u32 wptr;
+ u32 need_data;
+};
+
+struct malone_scode_handler {
+ u32 pixelformat;
+ int (*insert_scode_seq)(struct malone_scode_t *scode);
+ int (*insert_scode_pic)(struct malone_scode_t *scode);
+};
+
+struct vpu_dec_ctrl {
+ struct malone_codec_params *codec_param;
+ struct malone_jpg_params *jpg;
+ void *seq_mem;
+ void *pic_mem;
+ void *gop_mem;
+ void *qmeter_mem;
+ void *dbglog_mem;
+ struct vpu_malone_str_buffer *str_buf[VID_API_NUM_STREAMS];
+ u32 buf_addr[VID_API_NUM_STREAMS];
+};
+
+u32 vpu_malone_get_data_size(void)
+{
+ return sizeof(struct vpu_dec_ctrl);
+}
+
+void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
+ struct vpu_buffer *rpc, dma_addr_t boot_addr)
+{
+ struct malone_iface *iface;
+ struct vpu_dec_ctrl *hc;
+ unsigned long base_phy_addr;
+ unsigned long phy_addr;
+ unsigned long offset;
+ unsigned int i;
+
+ WARN_ON(!shared || !shared->priv);
+ WARN_ON(!rpc || !rpc->phys || !rpc->length || rpc->phys < boot_addr);
+
+ iface = rpc->virt;
+ base_phy_addr = rpc->phys - boot_addr;
+ hc = shared->priv;
+
+ shared->iface = iface;
+ shared->boot_addr = boot_addr;
+
+ iface->exec_base_addr = base_phy_addr;
+ iface->exec_area_size = rpc->length;
+
+ offset = sizeof(struct malone_iface);
+ phy_addr = base_phy_addr + offset;
+
+ shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
+ shared->cmd_mem_vir = rpc->virt + offset;
+ iface->cmd_buffer_desc.buffer.start =
+ iface->cmd_buffer_desc.buffer.rptr =
+ iface->cmd_buffer_desc.buffer.wptr = phy_addr;
+ iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
+ offset += CMD_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ shared->msg_desc = &iface->msg_buffer_desc.buffer;
+ shared->msg_mem_vir = rpc->virt + offset;
+ iface->msg_buffer_desc.buffer.start =
+ iface->msg_buffer_desc.buffer.wptr =
+ iface->msg_buffer_desc.buffer.rptr = phy_addr;
+ iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
+ offset += MSG_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->codec_param_tab_desc.array_base = phy_addr;
+ hc->codec_param = rpc->virt + offset;
+ offset += CODEC_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->jpeg_param_tab_desc.array_base = phy_addr;
+ hc->jpg = rpc->virt + offset;
+ offset += JPEG_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->seq_info_tab_desc.array_base = phy_addr;
+ hc->seq_mem = rpc->virt + offset;
+ offset += SEQ_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->pic_info_tab_desc.array_base = phy_addr;
+ hc->pic_mem = rpc->virt + offset;
+ offset += PIC_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->gop_info_tab_desc.array_base = phy_addr;
+ hc->gop_mem = rpc->virt + offset;
+ offset += GOP_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->qmeter_info_tab_desc.array_base = phy_addr;
+ hc->qmeter_mem = rpc->virt + offset;
+ offset += QMETER_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ iface->dbglog_desc.addr = phy_addr;
+ iface->dbglog_desc.size = DBGLOG_SIZE;
+ hc->dbglog_mem = rpc->virt + offset;
+ offset += DBGLOG_SIZE;
+ phy_addr = base_phy_addr + offset;
+
+ for (i = 0; i < VID_API_NUM_STREAMS; i++) {
+ iface->eng_access_buff_desc[i].buffer.start =
+ iface->eng_access_buff_desc[i].buffer.wptr =
+ iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
+ iface->eng_access_buff_desc[i].buffer.end =
+ iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
+ offset += ENG_SIZE;
+ phy_addr = base_phy_addr + offset;
+ }
+
+ for (i = 0; i < VID_API_NUM_STREAMS; i++) {
+ iface->encrypt_info[i] = phy_addr;
+ offset += sizeof(struct vpu_malone_encrypt_info);
+ phy_addr = base_phy_addr + offset;
+ }
+
+ rpc->bytesused = offset;
+}
+
+void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
+ struct vpu_buffer *log)
+{
+ struct malone_iface *iface;
+
+ WARN_ON(!shared || !log || !log->phys);
+ vpu_dbg(LVL_DEBUG, "set log area <0x%llx, 0x%x> (0x%lx)\n",
+ log->phys, log->length, shared->boot_addr);
+ iface = shared->iface;
+ iface->debug_buffer_desc.buffer.start =
+ iface->debug_buffer_desc.buffer.wptr =
+ iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
+ iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
+}
+
+static u32 get_str_buffer_offset(u32 instance)
+{
+ return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
+}
+
+void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
+ u32 regs_base, void __iomem *regs, u32 core_id)
+{
+ struct malone_iface *iface;
+ struct vpu_rpc_system_config *config;
+ struct vpu_dec_ctrl *hc;
+ int i;
+
+ WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv);
+
+ iface = shared->iface;
+ config = &iface->system_cfg;
+ hc = shared->priv;
+
+ vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
+ for (i = 0; i < VID_API_NUM_STREAMS; i++) {
+ u32 offset = get_str_buffer_offset(i);
+
+ hc->buf_addr[i] = regs_base + offset;
+ hc->str_buf[i] = regs + offset;
+ }
+}
+
+u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
+{
+ struct malone_iface *iface;
+
+ WARN_ON(!shared || !shared->iface);
+
+ iface = shared->iface;
+ return iface->fw_version;
+}
+
+int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
+{
+ return 0xc00000;
+}
+
+int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
+ u32 instance,
+ struct vpu_buffer *buf)
+{
+ struct malone_iface *iface;
+ struct vpu_dec_ctrl *hc;
+ struct vpu_malone_str_buffer *str_buf;
+
+ WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv);
+
+ iface = shared->iface;
+ hc = shared->priv;
+ str_buf = hc->str_buf[instance];
+ str_buf->wptr = str_buf->rptr = str_buf->start = buf->phys;
+ str_buf->end = buf->phys + buf->length;
+ str_buf->lwm = 0x1;
+
+ iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
+
+ return 0;
+}
+
+int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_rpc_buffer_desc *desc)
+{
+ struct vpu_dec_ctrl *hc;
+ struct vpu_malone_str_buffer *str_buf;
+
+ WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv);
+
+ hc = shared->priv;
+ str_buf = hc->str_buf[instance];
+
+ if (desc) {
+ desc->wptr = str_buf->wptr;
+ desc->rptr = str_buf->rptr;
+ desc->start = str_buf->start;
+ desc->end = str_buf->end;
+ }
+
+ return 0;
+}
+
+static void vpu_malone_update_wptr(struct vpu_malone_str_buffer *str_buf,
+ u32 wptr)
+{
+ u32 size = str_buf->end - str_buf->start;
+ u32 space = (str_buf->rptr + size - str_buf->wptr) % size;
+ u32 step = (wptr + size - str_buf->wptr) % size;
+
+ if (space && step > space)
+ vpu_err("update wptr from 0x%x to 0x%x, cross over rptr 0x%x\n",
+ str_buf->wptr, wptr, str_buf->rptr);
+
+ /*update wptr after data is written*/
+ mb();
+ str_buf->wptr = wptr;
+}
+
+static void vpu_malone_update_rptr(struct vpu_malone_str_buffer *str_buf,
+ u32 rptr)
+{
+ u32 size = str_buf->end - str_buf->start;
+ u32 space = (str_buf->wptr + size - str_buf->rptr) % size;
+ u32 step = (rptr + size - str_buf->rptr) % size;
+
+ if (step > space)
+ vpu_err("update rptr from 0x%x to 0x%x, cross over wptr 0x%x\n",
+ str_buf->rptr, rptr, str_buf->wptr);
+ /*update rptr after data is read*/
+ mb();
+ str_buf->rptr = rptr;
+}
+
+int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
+ u32 instance, u32 ptr, bool write)
+{
+ struct vpu_dec_ctrl *hc;
+ struct vpu_malone_str_buffer *str_buf;
+
+ WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv);
+
+ hc = shared->priv;
+ str_buf = hc->str_buf[instance];
+
+ if (write)
+ vpu_malone_update_wptr(str_buf, ptr);
+ else
+ vpu_malone_update_rptr(str_buf, ptr);
+
+ return 0;
+}
+
+static struct malone_fmt_mapping fmt_mappings[] = {
+ {V4L2_PIX_FMT_H264, MALONE_FMT_AVC},
+ {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC},
+ {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC},
+ {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
+ {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
+ {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2},
+ {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP},
+ {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP},
+ {V4L2_PIX_FMT_H263, MALONE_FMT_ASP},
+ {V4L2_PIX_FMT_AVS, MALONE_FMT_AVS},
+ {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG},
+ {V4L2_PIX_FMT_VP6, MALONE_FMT_VP6},
+ {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8},
+ {V4L2_PIX_FMT_SPK, MALONE_FMT_SPK},
+};
+
+static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
+ if (pixelformat == fmt_mappings[i].pixelformat)
+ return fmt_mappings[i].malone_format;
+ }
+
+ return MALONE_FMT_NULL;
+}
+
+static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
+ u32 instance, enum vpu_malone_format malone_format)
+{
+ struct malone_iface *iface;
+ u32 *curr_str_cfg;
+
+ iface = shared->iface;
+ curr_str_cfg = &iface->stream_config[instance];
+
+ *curr_str_cfg = 0;
+ STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
+ STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
+ STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
+ STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
+ STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
+ STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
+ STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
+ STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
+ STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
+ STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
+ STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
+ STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
+ STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
+ STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
+ STREAM_CONFIG_PES_SET(0, curr_str_cfg);
+ STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
+}
+
+static int vpu_malone_set_params(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_decode_params *params)
+{
+ struct malone_iface *iface;
+ struct vpu_dec_ctrl *hc;
+ enum vpu_malone_format malone_format;
+
+ iface = shared->iface;
+ hc = shared->priv;
+ malone_format = vpu_malone_format_remap(params->codec_format);
+ iface->udata_buffer[instance].base = params->udata.base;
+ iface->udata_buffer[instance].slot_size = params->udata.size;
+
+ vpu_malone_set_stream_cfg(shared, instance, malone_format);
+
+ if (malone_format == MALONE_FMT_JPG) {
+ //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B
+ hc->jpg[instance].jpg_mjpeg_mode = 1;
+ //0: JPGD_MJPEG_PROGRESSIVE
+ hc->jpg[instance].jpg_mjpeg_interlaced = 0;
+ }
+
+ hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0;
+ hc->codec_param[instance].dbglog_enable = 0;
+ iface->dbglog_desc.level = 0;
+
+ if (params->b_non_frame)
+ iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
+ else
+ iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
+ iface->stream_buff_info[instance].stream_buffer_threshold = 0;
+ iface->stream_buff_info[instance].stream_pic_input_count = 0;
+
+ return 0;
+}
+
+static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared,
+ u32 instance)
+{
+ struct malone_iface *iface;
+
+ iface = shared->iface;
+ if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
+ return true;
+
+ return false;
+}
+
+static int vpu_malone_update_params(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_decode_params *params)
+{
+ struct malone_iface *iface;
+
+ iface = shared->iface;
+
+ if (params->end_flag)
+ iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
+ params->end_flag = 0;
+
+ return 0;
+}
+
+int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_decode_params *params, u32 update)
+{
+ if (!params)
+ return -EINVAL;
+
+ if (!update)
+ return vpu_malone_set_params(shared, instance, params);
+ else
+ return vpu_malone_update_params(shared, instance, params);
+}
+
+static struct vpu_pair malone_cmds[] = {
+ {VPU_CMD_ID_START, VID_API_CMD_START},
+ {VPU_CMD_ID_STOP, VID_API_CMD_STOP},
+ {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
+ {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
+ {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
+ {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
+ {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
+ {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
+ {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
+ {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
+};
+
+static struct vpu_pair malone_msgs[] = {
+ {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
+ {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
+ {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
+ {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
+ {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
+ {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
+ {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
+ {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
+ {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
+ {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
+ {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
+ {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
+ {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
+ {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
+ {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
+ {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
+ {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
+};
+
+static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
+ struct vpu_fs_info *fs)
+{
+ const u32 fs_type[] = {
+ [MEM_RES_FRAME] = 0,
+ [MEM_RES_MBI] = 1,
+ [MEM_RES_DCP] = 2,
+ };
+
+ pkt->hdr.num = 7;
+ pkt->data[0] = fs->id | (fs->tag << 24);
+ pkt->data[1] = fs->luma_addr;
+ if (fs->type == MEM_RES_FRAME) {
+ /*
+ * if luma_addr equal to chroma_addr,
+ * means luma(plane[0]) and chromau(plane[1]) used the
+ * same fd -- usage of NXP codec2. Need to manually
+ * offset chroma addr.
+ */
+ if (fs->luma_addr == fs->chroma_addr)
+ fs->chroma_addr = fs->luma_addr + fs->luma_size;
+ pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
+ pkt->data[3] = fs->chroma_addr;
+ pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
+ pkt->data[5] = fs->bytesperline;
+ } else {
+ pkt->data[2] = fs->luma_size;
+ pkt->data[3] = 0;
+ pkt->data[4] = 0;
+ pkt->data[5] = 0;
+ }
+ pkt->data[6] = fs_type[fs->type];
+}
+
+static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
+ struct vpu_fs_info *fs)
+{
+ pkt->hdr.num = 1;
+ pkt->data[0] = fs->id | (fs->tag << 24);
+}
+
+static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
+ struct vpu_ts_info *info)
+{
+ pkt->hdr.num = 3;
+ if (info->timestamp < 0) {
+ pkt->data[0] = (u32)-1;
+ pkt->data[1] = 0;
+ } else {
+ pkt->data[0] = info->timestamp / NSEC_PER_SEC;
+ pkt->data[1] = info->timestamp % NSEC_PER_SEC;
+ }
+ pkt->data[2] = info->size;
+}
+
+int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
+{
+ int ret;
+
+ WARN_ON(!pkt);
+
+ ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id);
+ if (ret < 0)
+ return ret;
+
+ pkt->hdr.id = ret;
+ pkt->hdr.num = 0;
+ pkt->hdr.index = index;
+
+ switch (id) {
+ case VPU_CMD_ID_FS_ALLOC:
+ vpu_malone_pack_fs_alloc(pkt, data);
+ break;
+ case VPU_CMD_ID_FS_RELEASE:
+ vpu_malone_pack_fs_release(pkt, data);
+ break;
+ case VPU_CMD_ID_TIMESTAMP:
+ vpu_malone_pack_timestamp(pkt, data);
+ break;
+ }
+
+ pkt->hdr.index = index;
+ return 0;
+}
+
+int vpu_malone_convert_msg_id(u32 id)
+{
+ return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id);
+}
+
+void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
+{
+ const u32 align_width = MALONE_ALIGN_W;
+ const u32 align_height = MALONE_ALIGN_H;
+ u32 width;
+ u32 height;
+ u32 bytesperline;
+ u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
+
+ width = ALIGN(info->decoded_width, align_width);
+ height = ALIGN(info->decoded_height, align_height);
+ if (!info->progressive)
+ height = ALIGN(info->decoded_height, align_height * 2);
+
+ bytesperline = DIV_ROUND_UP((width * info->bit_depth_luma), BITS_PER_BYTE);
+ bytesperline = ALIGN(bytesperline, MALONE_ALIGN_LINE);
+
+ info->bytesperline[0] = bytesperline;
+ info->bytesperline[1] = bytesperline;
+ info->sizeimage[0] = bytesperline * height;
+ info->sizeimage[1] = (bytesperline * height) >> 1;
+ info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
+ info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
+
+ info->dcp_size = MALONE_DCP_SIZE_MAX;
+ if (chunks) {
+ u32 mb_num;
+ u32 mb_w;
+ u32 mb_h;
+
+ mb_w = DIV_ROUND_UP(info->decoded_width, 16);
+ mb_h = DIV_ROUND_UP(info->decoded_height, 16);
+ mb_num = mb_w * mb_h;
+ info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
+ info->dcp_size = clamp_t(u32, info->dcp_size,
+ MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
+ }
+
+ info->decoded_width = width;
+ info->decoded_height = height;
+}
+
+static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
+ struct vpu_dec_codec_info *info)
+{
+ info->num_ref_frms = pkt->data[0];
+ info->num_dpb_frms = pkt->data[1];
+ info->num_dfe_area = pkt->data[2];
+ info->progressive = pkt->data[3];
+ info->width = pkt->data[5];
+ info->height = pkt->data[4];
+ info->decoded_width = pkt->data[12];
+ info->decoded_height = pkt->data[11];
+ info->frame_rate = pkt->data[8];
+ info->dsp_asp_ratio = pkt->data[9];
+ info->level_idc = pkt->data[10];
+ info->bit_depth_luma = pkt->data[13];
+ info->bit_depth_chroma = pkt->data[14];
+ info->chroma_fmt = pkt->data[15];
+ info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]);
+ info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]);
+ info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]);
+ info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]);
+ info->vui_present = pkt->data[20];
+ info->mvc_num_views = pkt->data[21];
+ info->offset_x = pkt->data[23];
+ info->offset_y = pkt->data[25];
+ info->tag = pkt->data[27];
+ if (info->bit_depth_luma > 8)
+ info->pixfmt = V4L2_PIX_FMT_NT10;
+ else /* fix me: should set to V4L2_PIX_FMT_NT8 for NXP Tiled NV12 Format in future*/
+ info->pixfmt = V4L2_PIX_FMT_NV12;
+ vpu_malone_init_seq_hdr(info);
+}
+
+static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
+ struct vpu_dec_pic_info *info)
+{
+ info->id = pkt->data[7];
+ info->luma = pkt->data[0];
+ info->start = pkt->data[10];
+ info->end = pkt->data[12];
+ info->pic_size = pkt->data[11];
+ info->stride = pkt->data[5];
+ info->consumed_count = pkt->data[13];
+ if (info->id == MALONE_SKIPPED_FRAME_ID)
+ info->skipped = 1;
+ else
+ info->skipped = 0;
+}
+
+static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
+ struct vpu_fs_info *info)
+{
+ info->type = pkt->data[1];
+}
+
+static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
+ struct vpu_fs_info *info)
+{
+ info->id = pkt->data[0];
+ info->type = pkt->data[1];
+ info->not_displayed = pkt->data[2];
+}
+
+static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
+ struct vpu_dec_pic_info *info)
+{
+ info->id = pkt->data[0];
+ info->luma = pkt->data[1];
+ info->stride = pkt->data[3];
+ if (info->id == MALONE_SKIPPED_FRAME_ID)
+ info->skipped = 1;
+ else
+ info->skipped = 0;
+ info->timestamp = MAKE_TIMESTAMP(pkt->data[9], pkt->data[10]);
+}
+
+int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
+{
+ if (!pkt || !data)
+ return -EINVAL;
+
+ switch (pkt->hdr.id) {
+ case VID_API_EVENT_SEQ_HDR_FOUND:
+ vpu_malone_unpack_seq_hdr(pkt, data);
+ break;
+ case VID_API_EVENT_PIC_DECODED:
+ vpu_malone_unpack_pic_info(pkt, data);
+ break;
+ case VID_API_EVENT_REQ_FRAME_BUFF:
+ vpu_malone_unpack_req_frame(pkt, data);
+ break;
+ case VID_API_EVENT_REL_FRAME_BUFF:
+ vpu_malone_unpack_rel_frame(pkt, data);
+ break;
+ case VID_API_EVENT_FRAME_BUFF_RDY:
+ vpu_malone_unpack_buff_rdy(pkt, data);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct malone_padding_scode padding_scodes[] = {
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_AVS, {0xCC010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP6, {0x34010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_AVS, {0xb1010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP6, {0x34010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
+ {SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}},
+ {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}},
+ {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}},
+ {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}},
+};
+static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
+
+static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
+{
+ const struct malone_padding_scode *s;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
+ s = &padding_scodes[i];
+
+ if (s->scode_type == type && s->pixelformat == fmt)
+ return s;
+ }
+
+ if (type != SCODE_PADDING_BUFFLUSH)
+ return &padding_scode_dft;
+
+ return NULL;
+}
+
+static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
+ struct vpu_malone_str_buffer *str_buf,
+ u32 pixelformat, u32 scode_type)
+{
+ u32 wptr;
+ u32 size;
+ u32 total_size = 0;
+ const struct malone_padding_scode *ps;
+ const u32 padding_size = 4096;
+ int ret;
+
+ ps = get_padding_scode(scode_type, pixelformat);
+ if (!ps)
+ return -EINVAL;
+
+ wptr = str_buf->wptr;
+ size = ALIGN(wptr, 4) - wptr;
+ if (size)
+ vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
+ total_size += size;
+
+ size = sizeof(ps->data);
+ ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data);
+ if (ret < size)
+ return -EINVAL;
+ total_size += size;
+
+ size = padding_size - sizeof(ps->data);
+ vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
+ total_size += size;
+
+ vpu_malone_update_wptr(str_buf, wptr);
+ return total_size;
+}
+
+int vpu_malone_add_scode(struct vpu_shared_addr *shared,
+ u32 instance,
+ struct vpu_buffer *stream_buffer,
+ u32 pixelformat,
+ u32 scode_type)
+{
+ struct vpu_dec_ctrl *hc;
+ struct vpu_malone_str_buffer *str_buf;
+ int ret = -EINVAL;
+
+ WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv);
+
+ hc = shared->priv;
+ str_buf = hc->str_buf[instance];
+
+ switch (scode_type) {
+ case SCODE_PADDING_EOS:
+ case SCODE_PADDING_ABORT:
+ case SCODE_PADDING_BUFFLUSH:
+ ret = vpu_malone_add_padding_scode(stream_buffer,
+ str_buf, pixelformat, scode_type);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+#define MALONE_PAYLOAD_HEADER_SIZE 16
+#define MALONE_CODEC_VERSION_ID 0x1
+#define MALONE_CODEC_ID_VC1_SIMPLE 0x10
+#define MALONE_CODEC_ID_VC1_MAIN 0x11
+#define MALONE_CODEC_ID_ARV8 0x28
+#define MALONE_CODEC_ID_ARV9 0x29
+#define MALONE_CODEC_ID_VP6 0x36
+#define MALONE_CODEC_ID_VP8 0x36
+#define MALONE_CODEC_ID_DIVX3 0x38
+#define MALONE_CODEC_ID_SPK 0x39
+
+#define MALONE_VP8_IVF_SEQ_HEADER_LEN 32
+#define MALONE_VP8_IVF_FRAME_HEADER_LEN 8
+
+#define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85
+#define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5
+#define MALONE_VC1_RCV_NUM_FRAMES 0xFF
+#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4
+#define MALONE_VC1_RCV_SEQ_HEADER_LEN 20
+#define MALONE_VC1_RCV_PIC_HEADER_LEN 4
+#define MALONE_VC1_NAL_HEADER_LEN 4
+#define MALONE_VC1_CONTAIN_NAL(data) ((data & 0x00FFFFFF) == 0x00010000)
+
+
+static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
+ u32 buffer_size, u32 width, u32 height)
+{
+ unsigned int payload_size;
+ /* payload_size = buffer_size + itself_size(16) - start_code(4) */
+ payload_size = buffer_size + 12;
+
+ dst[0] = 0x00;
+ dst[1] = 0x00;
+ dst[2] = 0x01;
+ dst[3] = scd_type;
+
+ /* length */
+ dst[4] = ((payload_size>>16)&0xff);
+ dst[5] = ((payload_size>>8)&0xff);
+ dst[6] = 0x4e;
+ dst[7] = ((payload_size>>0)&0xff);
+
+ /* Codec ID and Version */
+ dst[8] = codec_id;
+ dst[9] = MALONE_CODEC_VERSION_ID;
+
+ /* width */
+ dst[10] = ((width>>8)&0xff);
+ dst[11] = ((width>>0)&0xff);
+ dst[12] = 0x58;
+
+ /* height */
+ dst[13] = ((height>>8)&0xff);
+ dst[14] = ((height>>0)&0xff);
+ dst[15] = 0x50;
+}
+
+static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
+{
+ /* 0-3byte signature "DKIF" */
+ dst[0] = 0x44;
+ dst[1] = 0x4b;
+ dst[2] = 0x49;
+ dst[3] = 0x46;
+ /* 4-5byte version: should be 0*/
+ dst[4] = 0x00;
+ dst[5] = 0x00;
+ /* 6-7 length of Header */
+ dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
+ dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
+ /* 8-11 VP8 fourcc */
+ dst[8] = 0x56;
+ dst[9] = 0x50;
+ dst[10] = 0x38;
+ dst[11] = 0x30;
+ /* 12-13 width in pixels */
+ dst[12] = width;
+ dst[13] = width >> 8;
+ /* 14-15 height in pixels */
+ dst[14] = height;
+ dst[15] = height >> 8;
+ /* 16-19 frame rate */
+ dst[16] = 0xe8;
+ dst[17] = 0x03;
+ dst[18] = 0x00;
+ dst[19] = 0x00;
+ /* 20-23 time scale */
+ dst[20] = 0x01;
+ dst[21] = 0x00;
+ dst[22] = 0x00;
+ dst[23] = 0x00;
+ /* 24-27 number frames */
+ dst[24] = 0xdf;
+ dst[25] = 0xf9;
+ dst[26] = 0x09;
+ dst[27] = 0x00;
+ /* 28-31 reserved */
+}
+
+static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
+{
+ /*
+ * firmware just parse 64-bit timestamp(8 bytes).
+ * As not transfer timestamp to firmware, use default value(ZERO).
+ * No need to do anything here
+ */
+}
+
+static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
+{
+ u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
+ u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
+
+ /* 0-2 Number of frames, used default value 0xFF */
+ dst[0] = frames;
+ dst[1] = frames >> 8;
+ dst[2] = frames >> 16;
+
+ /* 3 RCV version, used V1 */
+ dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
+
+ /* 4-7 extension data size */
+ dst[4] = ext_data_size;
+ dst[5] = ext_data_size >> 8;
+ dst[6] = ext_data_size >> 16;
+ dst[7] = ext_data_size >> 24;
+ /* 8-11 extension data */
+ dst[8] = src[0];
+ dst[9] = src[1];
+ dst[10] = src[2];
+ dst[11] = src[3];
+
+ /* height */
+ dst[12] = height;
+ dst[13] = (height >> 8) & 0xff;
+ dst[14] = (height >> 16) & 0xff;
+ dst[15] = (height >> 24) & 0xff;
+ /* width */
+ dst[16] = width;
+ dst[17] = (width >> 8) & 0xff;
+ dst[18] = (width >> 16) & 0xff;
+ dst[19] = (width >> 24) & 0xff;
+}
+
+static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
+{
+ dst[0] = buffer_size;
+ dst[1] = buffer_size >> 8;
+ dst[2] = buffer_size >> 16;
+ dst[3] = buffer_size >> 24;
+}
+
+static void create_vc1_nal_pichdr(u8 *dst)
+{
+ /* need insert nal header: special ID */
+ dst[0] = 0x0;
+ dst[1] = 0x0;
+ dst[2] = 0x01;
+ dst[3] = 0x0D;
+}
+
+static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
+{
+ u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
+ int ret;
+
+ set_payload_hdr(hdr,
+ SCODE_SEQUENCE,
+ codec_id,
+ ext_size,
+ scode->inst->out_format.width,
+ scode->inst->out_format.height);
+ ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(hdr),
+ hdr);
+ return ret;
+}
+
+static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
+{
+ u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
+ int ret;
+
+ set_payload_hdr(hdr,
+ SCODE_PICTURE,
+ codec_id,
+ ext_size + vb2_get_plane_payload(scode->vb, 0),
+ scode->inst->out_format.width,
+ scode->inst->out_format.height);
+ ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(hdr),
+ hdr);
+ return 0;
+}
+
+static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
+{
+ struct vb2_v4l2_buffer *vbuf;
+ u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
+ u32 *data = NULL;
+
+ vbuf = to_vb2_v4l2_buffer(scode->vb);
+ data = vb2_plane_vaddr(scode->vb, 0);
+
+ if (vbuf->sequence == 0 || (vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG))
+ return 0;
+ if (MALONE_VC1_CONTAIN_NAL(*data))
+ return 0;
+
+ create_vc1_nal_pichdr(nal_hdr);
+ return vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(nal_hdr),
+ nal_hdr);
+}
+
+static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
+{
+ int ret;
+ int size = 0;
+ u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
+
+ scode->need_data = 0;
+
+ ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE,
+ sizeof(rcv_seqhdr));
+ if (ret < 0)
+ return ret;
+ size = ret;
+
+ set_vc1_rcv_seqhdr(rcv_seqhdr,
+ vb2_plane_vaddr(scode->vb, 0),
+ scode->inst->out_format.width,
+ scode->inst->out_format.height);
+ ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(rcv_seqhdr),
+ rcv_seqhdr);
+
+ if (ret < 0)
+ return ret;
+ size += ret;
+ return size;
+}
+
+static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
+{
+ int ret;
+ int size = 0;
+ u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
+
+ ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
+ sizeof(rcv_pichdr));
+ if (ret < 0)
+ return ret;
+ size = ret;
+
+ set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0));
+ ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(rcv_pichdr),
+ rcv_pichdr);
+ if (ret < 0)
+ return ret;
+ size += ret;
+ return size;
+}
+
+static int vpu_malone_insert_scode_vp6_seq(struct malone_scode_t *scode)
+{
+ return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP6, 0);
+}
+
+static int vpu_malone_insert_scode_vp6_pic(struct malone_scode_t *scode)
+{
+ return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP6, 0);
+}
+
+static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
+{
+ int ret;
+ int size = 0;
+ u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
+
+ ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
+ if (ret < 0)
+ return ret;
+ size = ret;
+
+ set_vp8_ivf_seqhdr(ivf_hdr,
+ scode->inst->out_format.width,
+ scode->inst->out_format.height);
+ ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(ivf_hdr),
+ ivf_hdr);
+ if (ret < 0)
+ return ret;
+ size += ret;
+
+ return size;
+}
+
+static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
+{
+ int ret;
+ int size = 0;
+ u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
+
+ ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
+ if (ret < 0)
+ return ret;
+ size = ret;
+
+ set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0));
+ ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
+ &scode->wptr,
+ sizeof(ivf_hdr),
+ ivf_hdr);
+ if (ret < 0)
+ return ret;
+ size += ret;
+
+ return size;
+}
+
+static int vpu_malone_insert_scode_spk_seq(struct malone_scode_t *scode)
+{
+ return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_SPK, 0);
+}
+
+static int vpu_malone_insert_scode_spk_pic(struct malone_scode_t *scode)
+{
+ return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_SPK, 0);
+}
+
+static const struct malone_scode_handler scode_handlers[] = {
+ {
+ /* fix me, need to swap return operation after gstreamer swap */
+ .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
+ .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
+ .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
+ },
+ {
+ .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
+ .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
+ },
+ {
+ .pixelformat = V4L2_PIX_FMT_VP6,
+ .insert_scode_seq = vpu_malone_insert_scode_vp6_seq,
+ .insert_scode_pic = vpu_malone_insert_scode_vp6_pic,
+ },
+ {
+ .pixelformat = V4L2_PIX_FMT_VP8,
+ .insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
+ .insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
+ },
+ {
+ .pixelformat = V4L2_PIX_FMT_SPK,
+ .insert_scode_seq = vpu_malone_insert_scode_spk_seq,
+ .insert_scode_pic = vpu_malone_insert_scode_spk_pic,
+ },
+};
+
+const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
+ if (scode_handlers[i].pixelformat == pixelformat)
+ return &scode_handlers[i];
+ }
+
+ return NULL;
+}
+
+static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
+{
+ const struct malone_scode_handler *handler;
+ int ret = 0;
+
+ if (!scode || !scode->inst || !scode->vb)
+ return 0;
+
+ scode->need_data = 1;
+ handler = get_scode_handler(scode->inst->out_format.pixfmt);
+ if (!handler)
+ return 0;
+
+ switch (type) {
+ case SCODE_SEQUENCE:
+ if (handler->insert_scode_seq)
+ ret = handler->insert_scode_seq(scode);
+ break;
+ case SCODE_PICTURE:
+ if (handler->insert_scode_pic)
+ ret = handler->insert_scode_pic(scode);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer *str_buf,
+ struct vpu_inst *inst, struct vb2_buffer *vb,
+ u32 disp_imm)
+{
+ struct malone_scode_t scode;
+ struct vb2_v4l2_buffer *vbuf;
+ u32 wptr;
+ int size = 0;
+ int ret = 0;
+
+ wptr = str_buf->wptr;
+
+ /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/
+ vbuf = to_vb2_v4l2_buffer(vb);
+ scode.inst = inst;
+ scode.vb = vb;
+ scode.wptr = wptr;
+ scode.need_data = 1;
+ if (vbuf->sequence == 0 || (vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG))
+ ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE);
+
+ if (ret < 0)
+ return -ENOMEM;
+ size += ret;
+ wptr = scode.wptr;
+ if (!scode.need_data) {
+ vpu_malone_update_wptr(str_buf, wptr);
+ return size;
+ }
+
+ ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE);
+ if (ret < 0)
+ return -ENOMEM;
+ size += ret;
+ wptr = scode.wptr;
+
+ ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
+ &wptr,
+ vb2_get_plane_payload(vb, 0),
+ vb2_plane_vaddr(vb, 0));
+ if (ret < vb2_get_plane_payload(vb, 0))
+ return -ENOMEM;
+ size += ret;
+
+ vpu_malone_update_wptr(str_buf, wptr);
+
+ if (disp_imm && !(vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG)) {
+ ret = vpu_malone_add_scode(inst->core->iface,
+ inst->id,
+ &inst->stream_buffer,
+ inst->out_format.pixfmt,
+ SCODE_PADDING_BUFFLUSH);
+ if (ret < 0)
+ return ret;
+ size += ret;
+ }
+
+ return size;
+}
+
+static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer *str_buf,
+ struct vpu_inst *inst, struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf;
+ u32 wptr;
+ int ret = 0;
+
+ wptr = str_buf->wptr;
+ vbuf = to_vb2_v4l2_buffer(vb);
+ ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
+ &wptr,
+ vb2_get_plane_payload(vb, 0),
+ vb2_plane_vaddr(vb, 0));
+ if (ret < vb2_get_plane_payload(vb, 0))
+ return -ENOMEM;
+
+ vpu_malone_update_wptr(str_buf, wptr);
+
+ return ret;
+}
+
+static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size)
+{
+ struct vpu_ts_info info;
+
+ memset(&info, 0, sizeof(info));
+ info.timestamp = timestamp;
+ info.size = size;
+
+ return vpu_session_fill_timestamp(inst, &info);
+}
+
+int vpu_malone_input_frame(struct vpu_shared_addr *shared,
+ struct vpu_inst *inst, struct vb2_buffer *vb)
+{
+ struct vpu_dec_ctrl *hc;
+ struct vb2_v4l2_buffer *vbuf;
+ struct vpu_malone_str_buffer *str_buf;
+ u32 disp_imm = 0;
+ u32 size;
+ int ret;
+
+ WARN_ON(!shared || !shared->iface || !shared->core || !shared->priv);
+ hc = shared->priv;
+ str_buf = hc->str_buf[inst->id];
+ disp_imm = hc->codec_param[inst->id].disp_imm;
+
+ if (vpu_malone_is_non_frame_mode(shared, inst->id))
+ ret = vpu_malone_input_stream_data(str_buf, inst, vb);
+ else
+ ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
+ if (ret < 0)
+ return ret;
+ size = ret;
+
+ /*
+ * if buffer only contain codec data, and the timestamp is invalid,
+ * don't put the invalid timestamp to resync
+ * merge the data to next frame
+ */
+ vbuf = to_vb2_v4l2_buffer(vb);
+ if ((vbuf->flags & V4L2_BUF_FLAG_CODECCONFIG) && (s64)vb->timestamp < 0) {
+ inst->extra_size += size;
+ return 0;
+ }
+ if (inst->extra_size) {
+ size += inst->extra_size;
+ inst->extra_size = 0;
+ }
+
+ ret = vpu_malone_input_ts(inst, vb->timestamp, size);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
+{
+ struct malone_iface *iface;
+ struct vpu_rpc_buffer_desc *desc;
+ u32 size;
+ u32 rptr;
+ u32 wptr;
+ u32 used;
+
+ iface = shared->iface;
+ desc = &iface->api_cmd_buffer_desc[instance];
+ size = desc->end - desc->start;
+ rptr = desc->rptr;
+ wptr = desc->wptr;
+ used = (wptr + size - rptr) % size;
+ if (!size || used < size / 2)
+ return true;
+
+ vpu_dbg(LVL_DEBUG, "[%d]api cmd used = %d/%d\n", instance, used, size);
+
+ return false;
+}
+
+bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
+{
+ u32 cnt = 0;
+
+ while (!vpu_malone_check_ready(shared, instance)) {
+ if (cnt > 30)
+ return false;
+ mdelay(1);
+ cnt++;
+ }
+ return true;
+}
+
+int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
+{
+ if (!vpu_malone_is_ready(shared, instance)) {
+ vpu_err("[%d] is not ready\n", instance);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
+{
+ struct malone_iface *iface;
+ struct vpu_rpc_buffer_desc *desc;
+
+ iface = shared->iface;
+ desc = &iface->api_cmd_buffer_desc[instance];
+ desc->wptr++;
+ if (desc->wptr == desc->end)
+ desc->wptr = desc->start;
+
+ return 0;
+}
+
+int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
+{
+ struct malone_iface *iface;
+ struct vpu_rpc_buffer_desc *desc;
+
+ iface = shared->iface;
+ desc = &iface->api_cmd_buffer_desc[instance];
+ desc->wptr = desc->rptr;
+ if (desc->wptr == desc->end)
+ desc->wptr = desc->start;
+
+ return 0;
+}
+
+u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
+{
+ struct malone_iface *iface = shared->iface;
+
+ return iface->max_streams;
+}
diff --git a/drivers/media/platform/imx/vpu-8q/vpu_malone.h b/drivers/media/platform/imx/vpu-8q/vpu_malone.h
new file mode 100644
index 000000000000..3e637374bc44
--- /dev/null
+++ b/drivers/media/platform/imx/vpu-8q/vpu_malone.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020-2021 NXP
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef _IMX_VPU_MALONE_H
+#define _IMX_VPU_MALONE_H
+
+u32 vpu_malone_get_data_size(void);
+void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
+ struct vpu_buffer *rpc, dma_addr_t boot_addr);
+void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
+ struct vpu_buffer *log);
+void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
+ u32 regs_base, void __iomem *regs, u32 core_id);
+u32 vpu_malone_get_version(struct vpu_shared_addr *shared);
+int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared);
+int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_buffer *buf);
+int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_rpc_buffer_desc *desc);
+int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
+ u32 instance, u32 ptr, bool write);
+int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
+ u32 instance, struct vpu_decode_params *params, u32 update);
+int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data);
+int vpu_malone_convert_msg_id(u32 msg_id);
+int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data);
+int vpu_malone_add_scode(struct vpu_shared_addr *shared,
+ u32 instance,
+ struct vpu_buffer *stream_buffer,
+ u32 pixelformat,
+ u32 scode_type);
+int vpu_malone_input_frame(struct vpu_shared_addr *shared,
+ struct vpu_inst *inst, struct vb2_buffer *vb);
+bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance);
+int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance);
+int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance);
+int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance);
+u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared);
+
+#endif
--
2.32.0
Hi Ming Qian,
Thank you for working on this.
Some high-level comments:
First of all, it looks like this series is based on a nxp-kernel. I noticed
references to e.g. V4L2_COLORSPACE_GENERIC_FILM which doesn't exist in the
mainline kernel. The patch series really should be based on the mainline
kernel, or (preferred) the linux-media kernel (https://git.linuxtv.org/media_tree.git/,
master branch).
On 20/07/2021 03:43, Ming Qian wrote:
> Hi all,
>
> This patch series adds support for
> the imx8q video encoder and decoder
> via the VPU block present in imx8q platforms.
> Currently, support for IMX8QXP and IMX8QM is included.
>
> It features decoding for the following formats:
> - H.264
> - HEVC
> - MPEG4
> - MPEG2
> - MJPEG
> - VC1
> - VP8
> - AVS
>
> It features encoding for the following formats:
> - H.264
>
> The driver creates a separate device node for
> the encoder and decoder.
>
> Changelog:
>
> v4:
> - redefine the memory-region in devicetree bindings documentation
> - use v4l2's mechanism to implement synchronize queuing ioctl
> - remove the unnecessary mutex ioctl_sync
> - don't notify source change event if the parameters are same as previously established
> - add flag V4L2_FMT_FLAG_DYN_RESOLUTION to decoder's capture format
>
> v3:
> - don't make vpu device node a simple-bus
> - trigger probing vpu core in the driver
> - remove unnecessary vpu core index property
>
> v2:
> - fix dt bindings build error
> - split driver patch into several parts to avoid exceeding bytes limit
>
> Compliance
> ==========
> # v4l2-compliance -d /dev/video0
> v4l2-compliance SHA: not available
> , 64 bits, 64-bit time_t
Always compile v4l2-compliance from the git repo (https://git.linuxtv.org/v4l-utils.git/).
Otherwise I cannot tell whether it is a recent version or if it is old. Since there is no
SHA I'm going with old.
>
> Compliance test for vpu B0 device /dev/video0:
>
> Driver Info:
> Driver name : vpu B0
> Card type : imx vpu decoder
> Bus info : platform: imx8q-vpu
> Driver version : 5.10.35
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
Hmm, v4l2-compliance should have detected a stateful decoder here.
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
>
> Allow for multiple opens:
> test second /dev/video0 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> test invalid ioctls: OK
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 3 Private Controls: 2
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK
> test Scaling: OK
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
>
> Total for vpu b0 device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 0
>
> # v4l2-compliance -d /dev/video1
> v4l2-compliance SHA: not available
> , 64 bits, 64-bit time_t
>
> Compliance test for imx vpu encoder device /dev/video1:
>
> Driver Info:
> Driver name : imx vpu encoder
> Card type : imx vpu encoder
> Bus info : platform: imx8q-vpu
> Driver version : 5.10.35
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Detected Stateful Encoder
Here it properly detects a stateful encoder.
Regards,
Hans
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
>
> Allow for multiple opens:
> test second /dev/video1 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> test invalid ioctls: OK
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 20 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK (Not Supported)
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
>
> Total for imx vpu encoder device /dev/video1: 45, Succeeded: 45, Failed: 0, Warnings: 0
>
> Ming Qian (13):
> dt-bindings: media: imx8q: add imx video codec bindings
> media: v4l: add some definition of v4l2
> colorspace/xfer_func/ycbcr_encoding
> media: imx: imx8q: add imx8q vpu device driver
> media: imx: imx8q: add vpu core driver
> media: imx: imx8q: implement vpu core communication based on mailbox
> media: imx: imx8q: add vpu v4l2 m2m support
> media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver
> media: imx: imx8q: add v4l2 m2m vpu decoder stateful driver
> media: imx: imx8q: implement windsor encoder rpc interface
> media: imx: imx8q: implement malone decoder rpc interface
> ARM64: dts: freescale: imx8q: add imx vpu codec entries
> firmware: imx: scu-pd: imx8q: add vpu mu resources
> MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
>
> .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++
> MAINTAINERS | 10 +
> .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 +
> drivers/firmware/imx/scu-pd.c | 4 +
> drivers/media/platform/Kconfig | 2 +
> drivers/media/platform/Makefile | 2 +
> drivers/media/platform/imx/Kconfig | 19 +
> drivers/media/platform/imx/Makefile | 1 +
> drivers/media/platform/imx/vpu-8q/Makefile | 23 +
> drivers/media/platform/imx/vpu-8q/vdec.c | 1817 +++++++++++++++++
> drivers/media/platform/imx/vpu-8q/venc.c | 1395 +++++++++++++
> drivers/media/platform/imx/vpu-8q/vpu.h | 343 ++++
> drivers/media/platform/imx/vpu-8q/vpu_cmds.c | 446 ++++
> drivers/media/platform/imx/vpu-8q/vpu_cmds.h | 34 +
> drivers/media/platform/imx/vpu-8q/vpu_codec.h | 77 +
> drivers/media/platform/imx/vpu-8q/vpu_color.c | 201 ++
> drivers/media/platform/imx/vpu-8q/vpu_core.c | 919 +++++++++
> drivers/media/platform/imx/vpu-8q/vpu_core.h | 25 +
> drivers/media/platform/imx/vpu-8q/vpu_dbg.c | 505 +++++
> drivers/media/platform/imx/vpu-8q/vpu_defs.h | 194 ++
> .../media/platform/imx/vpu-8q/vpu_dev_imx8q.c | 82 +
> drivers/media/platform/imx/vpu-8q/vpu_drv.c | 225 ++
> .../media/platform/imx/vpu-8q/vpu_helpers.c | 405 ++++
> .../media/platform/imx/vpu-8q/vpu_helpers.h | 80 +
> drivers/media/platform/imx/vpu-8q/vpu_imx8q.c | 227 ++
> drivers/media/platform/imx/vpu-8q/vpu_imx8q.h | 125 ++
> drivers/media/platform/imx/vpu-8q/vpu_log.h | 53 +
> .../media/platform/imx/vpu-8q/vpu_malone.c | 1744 ++++++++++++++++
> .../media/platform/imx/vpu-8q/vpu_malone.h | 51 +
> drivers/media/platform/imx/vpu-8q/vpu_mbox.c | 135 ++
> drivers/media/platform/imx/vpu-8q/vpu_mbox.h | 25 +
> drivers/media/platform/imx/vpu-8q/vpu_msgs.c | 420 ++++
> drivers/media/platform/imx/vpu-8q/vpu_msgs.h | 23 +
> drivers/media/platform/imx/vpu-8q/vpu_rpc.c | 266 +++
> drivers/media/platform/imx/vpu-8q/vpu_rpc.h | 472 +++++
> drivers/media/platform/imx/vpu-8q/vpu_v4l2.c | 662 ++++++
> drivers/media/platform/imx/vpu-8q/vpu_v4l2.h | 53 +
> .../media/platform/imx/vpu-8q/vpu_windsor.c | 1253 ++++++++++++
> .../media/platform/imx/vpu-8q/vpu_windsor.h | 48 +
> include/linux/imx_vpu.h | 19 +
> include/uapi/linux/imx_vpu.h | 120 ++
> include/uapi/linux/videodev2.h | 30 +
> 44 files changed, 12828 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
> create mode 100644 drivers/media/platform/imx/Kconfig
> create mode 100644 drivers/media/platform/imx/Makefile
> create mode 100644 drivers/media/platform/imx/vpu-8q/Makefile
> create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/venc.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_codec.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_color.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dbg.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_defs.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_drv.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_log.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.h
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.c
> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.h
> create mode 100644 include/linux/imx_vpu.h
> create mode 100644 include/uapi/linux/imx_vpu.h
>
> Hi Ming Qian,
>
> Thank you for working on this.
>
> Some high-level comments:
>
> First of all, it looks like this series is based on a nxp-kernel. I noticed references
> to e.g. V4L2_COLORSPACE_GENERIC_FILM which doesn't exist in the mainline
> kernel. The patch series really should be based on the mainline kernel, or
> (preferred) the linux-media kernel
> (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.linu
> xtv.org%2Fmedia_tree.git%2F&data=04%7C01%7Cming.qian%40nxp.com
> %7C3b39b6df4e6746d5e5c308d94c19dd55%7C686ea1d3bc2b4c6fa92cd99c
> 5c301635%7C0%7C1%7C637624496237171229%7CUnknown%7CTWFpbGZs
> b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> %3D%7C2000&sdata=FlBIfE5%2BT3vsO7urAeeic%2FslWCQIR0VhuUuhx8Z
> Xizk%3D&reserved=0,
> master branch).
Hi Hans,
The patches are indeed based on linux-media kernel, and the V4L2_COLORSPACE_GENERIC_FILM is added in the patch "media: v4l: add some definition of v4l2 colorspace/xfer_func/ycbcr_encoding", which is the second patch of these series.
>
> On 20/07/2021 03:43, Ming Qian wrote:
> > Hi all,
> >
> > This patch series adds support for
> > the imx8q video encoder and decoder
> > via the VPU block present in imx8q platforms.
> > Currently, support for IMX8QXP and IMX8QM is included.
> >
> > It features decoding for the following formats:
> > - H.264
> > - HEVC
> > - MPEG4
> > - MPEG2
> > - MJPEG
> > - VC1
> > - VP8
> > - AVS
> >
> > It features encoding for the following formats:
> > - H.264
> >
> > The driver creates a separate device node for the encoder and decoder.
> >
> > Changelog:
> >
> > v4:
> > - redefine the memory-region in devicetree bindings documentation
> > - use v4l2's mechanism to implement synchronize queuing ioctl
> > - remove the unnecessary mutex ioctl_sync
> > - don't notify source change event if the parameters are same as
> > previously established
> > - add flag V4L2_FMT_FLAG_DYN_RESOLUTION to decoder's capture format
> >
> > v3:
> > - don't make vpu device node a simple-bus
> > - trigger probing vpu core in the driver
> > - remove unnecessary vpu core index property
> >
> > v2:
> > - fix dt bindings build error
> > - split driver patch into several parts to avoid exceeding bytes limit
> >
> > Compliance
> > ==========
> > # v4l2-compliance -d /dev/video0
> > v4l2-compliance SHA: not available
> > , 64 bits, 64-bit time_t
>
> Always compile v4l2-compliance from the git repo
> (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.linu
> xtv.org%2Fv4l-utils.git%2F&data=04%7C01%7Cming.qian%40nxp.com%7
> C3b39b6df4e6746d5e5c308d94c19dd55%7C686ea1d3bc2b4c6fa92cd99c5c3
> 01635%7C0%7C1%7C637624496237171229%7CUnknown%7CTWFpbGZsb3d
> 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C2000&sdata=%2FWh5ObGzfWN%2B2z4J9qhuM7bpA%2Fd6iaZbJw
> QhMI%2FdzFI%3D&reserved=0).
> Otherwise I cannot tell whether it is a recent version or if it is old. Since there is
> no SHA I'm going with old.
>
OK, I'll use the latest v4l2-compliance to test it again.
> >
> > Compliance test for vpu B0 device /dev/video0:
> >
> > Driver Info:
> > Driver name : vpu B0
> > Card type : imx vpu decoder
> > Bus info : platform: imx8q-vpu
> > Driver version : 5.10.35
> > Capabilities : 0x84204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Device Capabilities
> > Device Caps : 0x04204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
>
> Hmm, v4l2-compliance should have detected a stateful decoder here.
OK, I'll use the latest v4l2-compliance to test it again.
>
> >
> > Required ioctls:
> > test VIDIOC_QUERYCAP: OK
> >
> > Allow for multiple opens:
> > test second /dev/video0 open: OK
> > test VIDIOC_QUERYCAP: OK
> > test VIDIOC_G/S_PRIORITY: OK
> > test for unlimited opens: OK
> >
> > test invalid ioctls: OK
> > Debug ioctls:
> > test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> > test VIDIOC_LOG_STATUS: OK (Not Supported)
> >
> > Input ioctls:
> > test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> > test VIDIOC_ENUMAUDIO: OK (Not Supported)
> > test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDIO: OK (Not Supported)
> > Inputs: 0 Audio Inputs: 0 Tuners: 0
> >
> > Output ioctls:
> > test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> > test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> > Outputs: 0 Audio Outputs: 0 Modulators: 0
> >
> > Input/Output configuration ioctls:
> > test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> > test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> > test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> > test VIDIOC_G/S_EDID: OK (Not Supported)
> >
> > Control ioctls:
> > test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> > test VIDIOC_QUERYCTRL: OK
> > test VIDIOC_G/S_CTRL: OK
> > test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> > test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> > test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> > Standard Controls: 3 Private Controls: 2
> >
> > Format ioctls:
> > test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> > test VIDIOC_G/S_PARM: OK (Not Supported)
> > test VIDIOC_G_FBUF: OK (Not Supported)
> > test VIDIOC_G_FMT: OK
> > test VIDIOC_TRY_FMT: OK
> > test VIDIOC_S_FMT: OK
> > test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> > test Cropping: OK
> > test Composing: OK
> > test Scaling: OK
> >
> > Codec ioctls:
> > test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> > test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> > test VIDIOC_(TRY_)DECODER_CMD: OK
> >
> > Buffer ioctls:
> > test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> > test VIDIOC_EXPBUF: OK
> > test Requests: OK (Not Supported)
> >
> > Total for vpu b0 device /dev/video0: 45, Succeeded: 45, Failed: 0,
> > Warnings: 0
> >
> > # v4l2-compliance -d /dev/video1
> > v4l2-compliance SHA: not available
> > , 64 bits, 64-bit time_t
> >
> > Compliance test for imx vpu encoder device /dev/video1:
> >
> > Driver Info:
> > Driver name : imx vpu encoder
> > Card type : imx vpu encoder
> > Bus info : platform: imx8q-vpu
> > Driver version : 5.10.35
> > Capabilities : 0x84204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Device Capabilities
> > Device Caps : 0x04204000
> > Video Memory-to-Memory Multiplanar
> > Streaming
> > Extended Pix Format
> > Detected Stateful Encoder
>
> Here it properly detects a stateful encoder.
>
> Regards,
>
> Hans
>
OK, I'll use the latest v4l2-compliance to test it again.
> >
> > Required ioctls:
> > test VIDIOC_QUERYCAP: OK
> >
> > Allow for multiple opens:
> > test second /dev/video1 open: OK
> > test VIDIOC_QUERYCAP: OK
> > test VIDIOC_G/S_PRIORITY: OK
> > test for unlimited opens: OK
> >
> > test invalid ioctls: OK
> > Debug ioctls:
> > test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> > test VIDIOC_LOG_STATUS: OK (Not Supported)
> >
> > Input ioctls:
> > test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> > test VIDIOC_ENUMAUDIO: OK (Not Supported)
> > test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDIO: OK (Not Supported)
> > Inputs: 0 Audio Inputs: 0 Tuners: 0
> >
> > Output ioctls:
> > test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> > test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> > test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> > test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> > test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> > Outputs: 0 Audio Outputs: 0 Modulators: 0
> >
> > Input/Output configuration ioctls:
> > test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> > test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> > test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> > test VIDIOC_G/S_EDID: OK (Not Supported)
> >
> > Control ioctls:
> > test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> > test VIDIOC_QUERYCTRL: OK
> > test VIDIOC_G/S_CTRL: OK
> > test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> > test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> > test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> > Standard Controls: 20 Private Controls: 0
> >
> > Format ioctls:
> > test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> > test VIDIOC_G/S_PARM: OK
> > test VIDIOC_G_FBUF: OK (Not Supported)
> > test VIDIOC_G_FMT: OK
> > test VIDIOC_TRY_FMT: OK
> > test VIDIOC_S_FMT: OK
> > test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> > test Cropping: OK
> > test Composing: OK (Not Supported)
> > test Scaling: OK (Not Supported)
> >
> > Codec ioctls:
> > test VIDIOC_(TRY_)ENCODER_CMD: OK
> > test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> > test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
> >
> > Buffer ioctls:
> > test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> > test VIDIOC_EXPBUF: OK
> > test Requests: OK (Not Supported)
> >
> > Total for imx vpu encoder device /dev/video1: 45, Succeeded: 45,
> > Failed: 0, Warnings: 0
> >
> > Ming Qian (13):
> > dt-bindings: media: imx8q: add imx video codec bindings
> > media: v4l: add some definition of v4l2
> > colorspace/xfer_func/ycbcr_encoding
> > media: imx: imx8q: add imx8q vpu device driver
> > media: imx: imx8q: add vpu core driver
> > media: imx: imx8q: implement vpu core communication based on
> mailbox
> > media: imx: imx8q: add vpu v4l2 m2m support
> > media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver
> > media: imx: imx8q: add v4l2 m2m vpu decoder stateful driver
> > media: imx: imx8q: implement windsor encoder rpc interface
> > media: imx: imx8q: implement malone decoder rpc interface
> > ARM64: dts: freescale: imx8q: add imx vpu codec entries
> > firmware: imx: scu-pd: imx8q: add vpu mu resources
> > MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
> >
> > .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++
> > MAINTAINERS | 10 +
> > .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +
> > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 +
> > drivers/firmware/imx/scu-pd.c | 4 +
> > drivers/media/platform/Kconfig | 2 +
> > drivers/media/platform/Makefile | 2 +
> > drivers/media/platform/imx/Kconfig | 19 +
> > drivers/media/platform/imx/Makefile | 1 +
> > drivers/media/platform/imx/vpu-8q/Makefile | 23 +
> > drivers/media/platform/imx/vpu-8q/vdec.c | 1817
> +++++++++++++++++
> > drivers/media/platform/imx/vpu-8q/venc.c | 1395 +++++++++++++
> > drivers/media/platform/imx/vpu-8q/vpu.h | 343 ++++
> > drivers/media/platform/imx/vpu-8q/vpu_cmds.c | 446 ++++
> > drivers/media/platform/imx/vpu-8q/vpu_cmds.h | 34 +
> > drivers/media/platform/imx/vpu-8q/vpu_codec.h | 77 +
> > drivers/media/platform/imx/vpu-8q/vpu_color.c | 201 ++
> > drivers/media/platform/imx/vpu-8q/vpu_core.c | 919 +++++++++
> > drivers/media/platform/imx/vpu-8q/vpu_core.h | 25 +
> > drivers/media/platform/imx/vpu-8q/vpu_dbg.c | 505 +++++
> > drivers/media/platform/imx/vpu-8q/vpu_defs.h | 194 ++
> > .../media/platform/imx/vpu-8q/vpu_dev_imx8q.c | 82 +
> > drivers/media/platform/imx/vpu-8q/vpu_drv.c | 225 ++
> > .../media/platform/imx/vpu-8q/vpu_helpers.c | 405 ++++
> > .../media/platform/imx/vpu-8q/vpu_helpers.h | 80 +
> > drivers/media/platform/imx/vpu-8q/vpu_imx8q.c | 227 ++
> > drivers/media/platform/imx/vpu-8q/vpu_imx8q.h | 125 ++
> > drivers/media/platform/imx/vpu-8q/vpu_log.h | 53 +
> > .../media/platform/imx/vpu-8q/vpu_malone.c | 1744
> ++++++++++++++++
> > .../media/platform/imx/vpu-8q/vpu_malone.h | 51 +
> > drivers/media/platform/imx/vpu-8q/vpu_mbox.c | 135 ++
> > drivers/media/platform/imx/vpu-8q/vpu_mbox.h | 25 +
> > drivers/media/platform/imx/vpu-8q/vpu_msgs.c | 420 ++++
> > drivers/media/platform/imx/vpu-8q/vpu_msgs.h | 23 +
> > drivers/media/platform/imx/vpu-8q/vpu_rpc.c | 266 +++
> > drivers/media/platform/imx/vpu-8q/vpu_rpc.h | 472 +++++
> > drivers/media/platform/imx/vpu-8q/vpu_v4l2.c | 662 ++++++
> > drivers/media/platform/imx/vpu-8q/vpu_v4l2.h | 53 +
> > .../media/platform/imx/vpu-8q/vpu_windsor.c | 1253 ++++++++++++
> > .../media/platform/imx/vpu-8q/vpu_windsor.h | 48 +
> > include/linux/imx_vpu.h | 19 +
> > include/uapi/linux/imx_vpu.h | 120 ++
> > include/uapi/linux/videodev2.h | 30 +
> > 44 files changed, 12828 insertions(+) create mode 100644
> > Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> > create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
> > create mode 100644 drivers/media/platform/imx/Kconfig
> > create mode 100644 drivers/media/platform/imx/Makefile
> > create mode 100644 drivers/media/platform/imx/vpu-8q/Makefile
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/venc.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_codec.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_color.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dbg.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_defs.h
> > create mode 100644
> drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_drv.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_log.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.h
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.c
> > create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.h
> > create mode 100644 include/linux/imx_vpu.h create mode 100644
> > include/uapi/linux/imx_vpu.h
> >
On 21/07/2021 10:53, Ming Qian wrote:
>> Hi Ming Qian,
>>
>> Thank you for working on this.
>>
>> Some high-level comments:
>>
>> First of all, it looks like this series is based on a nxp-kernel. I noticed references
>> to e.g. V4L2_COLORSPACE_GENERIC_FILM which doesn't exist in the mainline
>> kernel. The patch series really should be based on the mainline kernel, or
>> (preferred) the linux-media kernel
>> (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.linu
>> xtv.org%2Fmedia_tree.git%2F&data=04%7C01%7Cming.qian%40nxp.com
>> %7C3b39b6df4e6746d5e5c308d94c19dd55%7C686ea1d3bc2b4c6fa92cd99c
>> 5c301635%7C0%7C1%7C637624496237171229%7CUnknown%7CTWFpbGZs
>> b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
>> %3D%7C2000&sdata=FlBIfE5%2BT3vsO7urAeeic%2FslWCQIR0VhuUuhx8Z
>> Xizk%3D&reserved=0,
>> master branch).
>
> Hi Hans,
> The patches are indeed based on linux-media kernel, and the V4L2_COLORSPACE_GENERIC_FILM is added in the patch "media: v4l: add some definition of v4l2 colorspace/xfer_func/ycbcr_encoding", which is the second patch of these series.
My mistake, for some reason I totally overlooked that patch. Weird.
Regards,
Hans
>
>>
>> On 20/07/2021 03:43, Ming Qian wrote:
>>> Hi all,
>>>
>>> This patch series adds support for
>>> the imx8q video encoder and decoder
>>> via the VPU block present in imx8q platforms.
>>> Currently, support for IMX8QXP and IMX8QM is included.
>>>
>>> It features decoding for the following formats:
>>> - H.264
>>> - HEVC
>>> - MPEG4
>>> - MPEG2
>>> - MJPEG
>>> - VC1
>>> - VP8
>>> - AVS
>>>
>>> It features encoding for the following formats:
>>> - H.264
>>>
>>> The driver creates a separate device node for the encoder and decoder.
>>>
>>> Changelog:
>>>
>>> v4:
>>> - redefine the memory-region in devicetree bindings documentation
>>> - use v4l2's mechanism to implement synchronize queuing ioctl
>>> - remove the unnecessary mutex ioctl_sync
>>> - don't notify source change event if the parameters are same as
>>> previously established
>>> - add flag V4L2_FMT_FLAG_DYN_RESOLUTION to decoder's capture format
>>>
>>> v3:
>>> - don't make vpu device node a simple-bus
>>> - trigger probing vpu core in the driver
>>> - remove unnecessary vpu core index property
>>>
>>> v2:
>>> - fix dt bindings build error
>>> - split driver patch into several parts to avoid exceeding bytes limit
>>>
>>> Compliance
>>> ==========
>>> # v4l2-compliance -d /dev/video0
>>> v4l2-compliance SHA: not available
>>> , 64 bits, 64-bit time_t
>>
>> Always compile v4l2-compliance from the git repo
>> (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.linu
>> xtv.org%2Fv4l-utils.git%2F&data=04%7C01%7Cming.qian%40nxp.com%7
>> C3b39b6df4e6746d5e5c308d94c19dd55%7C686ea1d3bc2b4c6fa92cd99c5c3
>> 01635%7C0%7C1%7C637624496237171229%7CUnknown%7CTWFpbGZsb3d
>> 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
>> D%7C2000&sdata=%2FWh5ObGzfWN%2B2z4J9qhuM7bpA%2Fd6iaZbJw
>> QhMI%2FdzFI%3D&reserved=0).
>> Otherwise I cannot tell whether it is a recent version or if it is old. Since there is
>> no SHA I'm going with old.
>>
>
> OK, I'll use the latest v4l2-compliance to test it again.
>
>>>
>>> Compliance test for vpu B0 device /dev/video0:
>>>
>>> Driver Info:
>>> Driver name : vpu B0
>>> Card type : imx vpu decoder
>>> Bus info : platform: imx8q-vpu
>>> Driver version : 5.10.35
>>> Capabilities : 0x84204000
>>> Video Memory-to-Memory Multiplanar
>>> Streaming
>>> Extended Pix Format
>>> Device Capabilities
>>> Device Caps : 0x04204000
>>> Video Memory-to-Memory Multiplanar
>>> Streaming
>>> Extended Pix Format
>>
>> Hmm, v4l2-compliance should have detected a stateful decoder here.
>
> OK, I'll use the latest v4l2-compliance to test it again.
>
>>
>>>
>>> Required ioctls:
>>> test VIDIOC_QUERYCAP: OK
>>>
>>> Allow for multiple opens:
>>> test second /dev/video0 open: OK
>>> test VIDIOC_QUERYCAP: OK
>>> test VIDIOC_G/S_PRIORITY: OK
>>> test for unlimited opens: OK
>>>
>>> test invalid ioctls: OK
>>> Debug ioctls:
>>> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
>>> test VIDIOC_LOG_STATUS: OK (Not Supported)
>>>
>>> Input ioctls:
>>> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
>>> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
>>> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
>>> test VIDIOC_ENUMAUDIO: OK (Not Supported)
>>> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
>>> test VIDIOC_G/S_AUDIO: OK (Not Supported)
>>> Inputs: 0 Audio Inputs: 0 Tuners: 0
>>>
>>> Output ioctls:
>>> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
>>> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
>>> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
>>> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
>>> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
>>> Outputs: 0 Audio Outputs: 0 Modulators: 0
>>>
>>> Input/Output configuration ioctls:
>>> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
>>> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
>>> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
>>> test VIDIOC_G/S_EDID: OK (Not Supported)
>>>
>>> Control ioctls:
>>> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
>>> test VIDIOC_QUERYCTRL: OK
>>> test VIDIOC_G/S_CTRL: OK
>>> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
>>> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
>>> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
>>> Standard Controls: 3 Private Controls: 2
>>>
>>> Format ioctls:
>>> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
>>> test VIDIOC_G/S_PARM: OK (Not Supported)
>>> test VIDIOC_G_FBUF: OK (Not Supported)
>>> test VIDIOC_G_FMT: OK
>>> test VIDIOC_TRY_FMT: OK
>>> test VIDIOC_S_FMT: OK
>>> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
>>> test Cropping: OK
>>> test Composing: OK
>>> test Scaling: OK
>>>
>>> Codec ioctls:
>>> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
>>> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
>>> test VIDIOC_(TRY_)DECODER_CMD: OK
>>>
>>> Buffer ioctls:
>>> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
>>> test VIDIOC_EXPBUF: OK
>>> test Requests: OK (Not Supported)
>>>
>>> Total for vpu b0 device /dev/video0: 45, Succeeded: 45, Failed: 0,
>>> Warnings: 0
>>>
>>> # v4l2-compliance -d /dev/video1
>>> v4l2-compliance SHA: not available
>>> , 64 bits, 64-bit time_t
>>>
>>> Compliance test for imx vpu encoder device /dev/video1:
>>>
>>> Driver Info:
>>> Driver name : imx vpu encoder
>>> Card type : imx vpu encoder
>>> Bus info : platform: imx8q-vpu
>>> Driver version : 5.10.35
>>> Capabilities : 0x84204000
>>> Video Memory-to-Memory Multiplanar
>>> Streaming
>>> Extended Pix Format
>>> Device Capabilities
>>> Device Caps : 0x04204000
>>> Video Memory-to-Memory Multiplanar
>>> Streaming
>>> Extended Pix Format
>>> Detected Stateful Encoder
>>
>> Here it properly detects a stateful encoder.
>>
>> Regards,
>>
>> Hans
>>
>
> OK, I'll use the latest v4l2-compliance to test it again.
>
>>>
>>> Required ioctls:
>>> test VIDIOC_QUERYCAP: OK
>>>
>>> Allow for multiple opens:
>>> test second /dev/video1 open: OK
>>> test VIDIOC_QUERYCAP: OK
>>> test VIDIOC_G/S_PRIORITY: OK
>>> test for unlimited opens: OK
>>>
>>> test invalid ioctls: OK
>>> Debug ioctls:
>>> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
>>> test VIDIOC_LOG_STATUS: OK (Not Supported)
>>>
>>> Input ioctls:
>>> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
>>> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
>>> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
>>> test VIDIOC_ENUMAUDIO: OK (Not Supported)
>>> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
>>> test VIDIOC_G/S_AUDIO: OK (Not Supported)
>>> Inputs: 0 Audio Inputs: 0 Tuners: 0
>>>
>>> Output ioctls:
>>> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
>>> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
>>> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
>>> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
>>> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
>>> Outputs: 0 Audio Outputs: 0 Modulators: 0
>>>
>>> Input/Output configuration ioctls:
>>> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
>>> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
>>> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
>>> test VIDIOC_G/S_EDID: OK (Not Supported)
>>>
>>> Control ioctls:
>>> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
>>> test VIDIOC_QUERYCTRL: OK
>>> test VIDIOC_G/S_CTRL: OK
>>> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
>>> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
>>> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
>>> Standard Controls: 20 Private Controls: 0
>>>
>>> Format ioctls:
>>> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
>>> test VIDIOC_G/S_PARM: OK
>>> test VIDIOC_G_FBUF: OK (Not Supported)
>>> test VIDIOC_G_FMT: OK
>>> test VIDIOC_TRY_FMT: OK
>>> test VIDIOC_S_FMT: OK
>>> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
>>> test Cropping: OK
>>> test Composing: OK (Not Supported)
>>> test Scaling: OK (Not Supported)
>>>
>>> Codec ioctls:
>>> test VIDIOC_(TRY_)ENCODER_CMD: OK
>>> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
>>> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>>>
>>> Buffer ioctls:
>>> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
>>> test VIDIOC_EXPBUF: OK
>>> test Requests: OK (Not Supported)
>>>
>>> Total for imx vpu encoder device /dev/video1: 45, Succeeded: 45,
>>> Failed: 0, Warnings: 0
>>>
>>> Ming Qian (13):
>>> dt-bindings: media: imx8q: add imx video codec bindings
>>> media: v4l: add some definition of v4l2
>>> colorspace/xfer_func/ycbcr_encoding
>>> media: imx: imx8q: add imx8q vpu device driver
>>> media: imx: imx8q: add vpu core driver
>>> media: imx: imx8q: implement vpu core communication based on
>> mailbox
>>> media: imx: imx8q: add vpu v4l2 m2m support
>>> media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver
>>> media: imx: imx8q: add v4l2 m2m vpu decoder stateful driver
>>> media: imx: imx8q: implement windsor encoder rpc interface
>>> media: imx: imx8q: implement malone decoder rpc interface
>>> ARM64: dts: freescale: imx8q: add imx vpu codec entries
>>> firmware: imx: scu-pd: imx8q: add vpu mu resources
>>> MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
>>>
>>> .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++
>>> MAINTAINERS | 10 +
>>> .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +
>>> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +
>>> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 +
>>> drivers/firmware/imx/scu-pd.c | 4 +
>>> drivers/media/platform/Kconfig | 2 +
>>> drivers/media/platform/Makefile | 2 +
>>> drivers/media/platform/imx/Kconfig | 19 +
>>> drivers/media/platform/imx/Makefile | 1 +
>>> drivers/media/platform/imx/vpu-8q/Makefile | 23 +
>>> drivers/media/platform/imx/vpu-8q/vdec.c | 1817
>> +++++++++++++++++
>>> drivers/media/platform/imx/vpu-8q/venc.c | 1395 +++++++++++++
>>> drivers/media/platform/imx/vpu-8q/vpu.h | 343 ++++
>>> drivers/media/platform/imx/vpu-8q/vpu_cmds.c | 446 ++++
>>> drivers/media/platform/imx/vpu-8q/vpu_cmds.h | 34 +
>>> drivers/media/platform/imx/vpu-8q/vpu_codec.h | 77 +
>>> drivers/media/platform/imx/vpu-8q/vpu_color.c | 201 ++
>>> drivers/media/platform/imx/vpu-8q/vpu_core.c | 919 +++++++++
>>> drivers/media/platform/imx/vpu-8q/vpu_core.h | 25 +
>>> drivers/media/platform/imx/vpu-8q/vpu_dbg.c | 505 +++++
>>> drivers/media/platform/imx/vpu-8q/vpu_defs.h | 194 ++
>>> .../media/platform/imx/vpu-8q/vpu_dev_imx8q.c | 82 +
>>> drivers/media/platform/imx/vpu-8q/vpu_drv.c | 225 ++
>>> .../media/platform/imx/vpu-8q/vpu_helpers.c | 405 ++++
>>> .../media/platform/imx/vpu-8q/vpu_helpers.h | 80 +
>>> drivers/media/platform/imx/vpu-8q/vpu_imx8q.c | 227 ++
>>> drivers/media/platform/imx/vpu-8q/vpu_imx8q.h | 125 ++
>>> drivers/media/platform/imx/vpu-8q/vpu_log.h | 53 +
>>> .../media/platform/imx/vpu-8q/vpu_malone.c | 1744
>> ++++++++++++++++
>>> .../media/platform/imx/vpu-8q/vpu_malone.h | 51 +
>>> drivers/media/platform/imx/vpu-8q/vpu_mbox.c | 135 ++
>>> drivers/media/platform/imx/vpu-8q/vpu_mbox.h | 25 +
>>> drivers/media/platform/imx/vpu-8q/vpu_msgs.c | 420 ++++
>>> drivers/media/platform/imx/vpu-8q/vpu_msgs.h | 23 +
>>> drivers/media/platform/imx/vpu-8q/vpu_rpc.c | 266 +++
>>> drivers/media/platform/imx/vpu-8q/vpu_rpc.h | 472 +++++
>>> drivers/media/platform/imx/vpu-8q/vpu_v4l2.c | 662 ++++++
>>> drivers/media/platform/imx/vpu-8q/vpu_v4l2.h | 53 +
>>> .../media/platform/imx/vpu-8q/vpu_windsor.c | 1253 ++++++++++++
>>> .../media/platform/imx/vpu-8q/vpu_windsor.h | 48 +
>>> include/linux/imx_vpu.h | 19 +
>>> include/uapi/linux/imx_vpu.h | 120 ++
>>> include/uapi/linux/videodev2.h | 30 +
>>> 44 files changed, 12828 insertions(+) create mode 100644
>>> Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
>>> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
>>> create mode 100644 drivers/media/platform/imx/Kconfig
>>> create mode 100644 drivers/media/platform/imx/Makefile
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/Makefile
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/venc.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_codec.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_color.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dbg.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_defs.h
>>> create mode 100644
>> drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_drv.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_log.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.h
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.c
>>> create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.h
>>> create mode 100644 include/linux/imx_vpu.h create mode 100644
>>> include/uapi/linux/imx_vpu.h
>>>
>