The following are driver and documentation patches to enable UHS modes for
TI's AM65x, J721e, and J7200 boards. Device tree and defconfig patches
will be sent in a separate series.
With the complete set, the following maximum modes will be supported:
am654x-evm,idk - SDR104, HS200
j721e-common-proc-board - DDR50, HS200
j7200-common-proc-board - DDR50, HS200
These patches mainly add support for the software tuning algorithm[1]
needed for higher speed modes
[1] [1] https://www.ti.com/lit/pdf/spract9
Faiz Abbas (6):
dt-bindings: mmc: sdhci-am654: Convert sdhci-am654 controller
documentation to json schema
dt-bindings: mmc: sdhci-am654: Add documentation for input tap delay
mmc: sdhci_am654: Fix hard coded otap delay array size
mmc: sdhci_am654: Add support for input tap delay
mmc: sdhci_am654: Add support for software tuning
mmc: sdhci_am654: Enable tuning for SDR50
.../devicetree/bindings/mmc/sdhci-am654.txt | 65 ------
.../devicetree/bindings/mmc/sdhci-am654.yaml | 218 ++++++++++++++++++
drivers/mmc/host/sdhci_am654.c | 179 ++++++++++----
3 files changed, 358 insertions(+), 104 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.txt
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
--
2.17.1
Change hard coded array size value to depend on struct timing_data
array size.
Signed-off-by: Faiz Abbas <[email protected]>
---
drivers/mmc/host/sdhci_am654.c | 42 +++++++++++++++++-----------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index a4c6d9d80e88..9f3347bc3757 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -85,10 +85,30 @@ static struct regmap_config sdhci_am654_regmap_config = {
.fast_io = true,
};
+struct timing_data {
+ const char *binding;
+ u32 capability;
+};
+
+static const struct timing_data td[] = {
+ [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
+ [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
+ [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
+ [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
+ [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
+ [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
+ [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
+ MMC_CAP_UHS_SDR104},
+ [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
+ [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
+ [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
+ [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
+};
+
struct sdhci_am654_data {
struct regmap *base;
bool legacy_otapdly;
- int otap_del_sel[11];
+ int otap_del_sel[ARRAY_SIZE(td)];
int clkbuf_sel;
int trm_icp;
int drv_strength;
@@ -107,26 +127,6 @@ struct sdhci_am654_driver_data {
#define DLL_CALIB (1 << 4)
};
-struct timing_data {
- const char *binding;
- u32 capability;
-};
-
-static const struct timing_data td[] = {
- [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
- [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
- [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
- [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
- [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
- [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
- [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
- MMC_CAP_UHS_SDR104},
- [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
- [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
- [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
- [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
-};
-
static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
--
2.17.1
According to the SW tuning App note[1], tuning is required for all
UHS speed modes. Tuning for SDR50 is not enabled in Capabilities by
default so enable it from the CTL_CFG registers.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas <[email protected]>
---
drivers/mmc/host/sdhci_am654.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 5af7638ad606..2bce962bf7e4 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -19,9 +19,11 @@
/* CTL_CFG Registers */
#define CTL_CFG_2 0x14
+#define CTL_CFG_3 0x18
#define SLOTTYPE_MASK GENMASK(31, 30)
#define SLOTTYPE_EMBEDDED BIT(30)
+#define TUNINGFORSDR50_MASK BIT(13)
/* PHY Registers */
#define PHY_CTRL1 0x100
@@ -646,6 +648,10 @@ static int sdhci_am654_init(struct sdhci_host *host)
regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
ctl_cfg_2);
+ /* Enable tuning for SDR50 */
+ regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
+ TUNINGFORSDR50_MASK);
+
ret = sdhci_setup_host(host);
if (ret)
return ret;
--
2.17.1
With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas <[email protected]>
---
drivers/mmc/host/sdhci_am654.c | 41 ++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 1213b711e60a..5af7638ad606 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -396,7 +396,46 @@ static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
return 0;
}
+#define ITAP_MAX 32
+static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
+ u32 opcode)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
+ int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
+ u32 itap;
+
+ /* Enable ITAPDLY */
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
+ 1 << ITAPDLYENA_SHIFT);
+
+ for (itap = 0; itap < ITAP_MAX; itap++) {
+ sdhci_am654_write_itapdly(sdhci_am654, itap);
+
+ cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
+ if (cur_val && !prev_val)
+ pass_window = itap;
+
+ if (!cur_val)
+ fail_len++;
+
+ prev_val = cur_val;
+ }
+ /*
+ * Having determined the length of the failing window and start of
+ * the passing window calculate the length of the passing window and
+ * set the final value halfway through it considering the range as a
+ * circular buffer
+ */
+ pass_len = ITAP_MAX - fail_len;
+ itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
+ sdhci_am654_write_itapdly(sdhci_am654, itap);
+
+ return 0;
+}
+
static struct sdhci_ops sdhci_am654_ops = {
+ .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.set_uhs_signaling = sdhci_set_uhs_signaling,
@@ -426,6 +465,7 @@ static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
};
static struct sdhci_ops sdhci_j721e_8bit_ops = {
+ .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.set_uhs_signaling = sdhci_set_uhs_signaling,
@@ -449,6 +489,7 @@ static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
};
static struct sdhci_ops sdhci_j721e_4bit_ops = {
+ .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.set_uhs_signaling = sdhci_set_uhs_signaling,
--
2.17.1
On 23/09/20 4:22 pm, Faiz Abbas wrote:
> With the new SW tuning App note[1], a custom tuning algorithm is
> required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
> involves running through the 32 possible input tap delay values and
> sending the appropriate tuning command (CMD19/21) for each of them
> to get a fail or pass result for each of the values. Typically, the
> range will have a small contiguous failing window. Considering the
> tuning range as a circular buffer, the algorithm then sets a final
> tuned value directly opposite to the failing window.
>
> [1] https://www.ti.com/lit/pdf/spract9
>
> Signed-off-by: Faiz Abbas <[email protected]>
Reviewed-by: Kishon Vijay Abraham I <[email protected]>
> ---
> drivers/mmc/host/sdhci_am654.c | 41 ++++++++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
> index 1213b711e60a..5af7638ad606 100644
> --- a/drivers/mmc/host/sdhci_am654.c
> +++ b/drivers/mmc/host/sdhci_am654.c
> @@ -396,7 +396,46 @@ static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
> return 0;
> }
>
> +#define ITAP_MAX 32
> +static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
> + u32 opcode)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
> + int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
> + u32 itap;
> +
> + /* Enable ITAPDLY */
> + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
> + 1 << ITAPDLYENA_SHIFT);
> +
> + for (itap = 0; itap < ITAP_MAX; itap++) {
> + sdhci_am654_write_itapdly(sdhci_am654, itap);
> +
> + cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
> + if (cur_val && !prev_val)
> + pass_window = itap;
> +
> + if (!cur_val)
> + fail_len++;
> +
> + prev_val = cur_val;
> + }
> + /*
> + * Having determined the length of the failing window and start of
> + * the passing window calculate the length of the passing window and
> + * set the final value halfway through it considering the range as a
> + * circular buffer
> + */
> + pass_len = ITAP_MAX - fail_len;
> + itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
> + sdhci_am654_write_itapdly(sdhci_am654, itap);
> +
> + return 0;
> +}
> +
> static struct sdhci_ops sdhci_am654_ops = {
> + .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
> .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
> .set_uhs_signaling = sdhci_set_uhs_signaling,
> @@ -426,6 +465,7 @@ static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
> };
>
> static struct sdhci_ops sdhci_j721e_8bit_ops = {
> + .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
> .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
> .set_uhs_signaling = sdhci_set_uhs_signaling,
> @@ -449,6 +489,7 @@ static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
> };
>
> static struct sdhci_ops sdhci_j721e_4bit_ops = {
> + .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
> .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
> .set_uhs_signaling = sdhci_set_uhs_signaling,
>
On Wed, 23 Sep 2020 at 12:52, Faiz Abbas <[email protected]> wrote:
>
> The following are driver and documentation patches to enable UHS modes for
> TI's AM65x, J721e, and J7200 boards. Device tree and defconfig patches
> will be sent in a separate series.
>
> With the complete set, the following maximum modes will be supported:
>
> am654x-evm,idk - SDR104, HS200
> j721e-common-proc-board - DDR50, HS200
> j7200-common-proc-board - DDR50, HS200
>
> These patches mainly add support for the software tuning algorithm[1]
> needed for higher speed modes
>
> [1] [1] https://www.ti.com/lit/pdf/spract9
>
> Faiz Abbas (6):
> dt-bindings: mmc: sdhci-am654: Convert sdhci-am654 controller
> documentation to json schema
> dt-bindings: mmc: sdhci-am654: Add documentation for input tap delay
> mmc: sdhci_am654: Fix hard coded otap delay array size
> mmc: sdhci_am654: Add support for input tap delay
> mmc: sdhci_am654: Add support for software tuning
> mmc: sdhci_am654: Enable tuning for SDR50
>
> .../devicetree/bindings/mmc/sdhci-am654.txt | 65 ------
> .../devicetree/bindings/mmc/sdhci-am654.yaml | 218 ++++++++++++++++++
> drivers/mmc/host/sdhci_am654.c | 179 ++++++++++----
> 3 files changed, 358 insertions(+), 104 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
>
> --
> 2.17.1
>
Applied for next, thanks!
Kind regards
Uffe