2021-06-02 11:22:12

by James Lo

Subject: Add PMIC wrapper support for Mediatek MT8195 SoC IC

This series adds support for new SoC MT8195 to the pmic-wrap driver.

Henry Chen (2):
dt-bindings: mediatek: add compatible for MT8195 pwrap
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

.../bindings/soc/mediatek/pwrap.txt | 1 +
drivers/soc/mediatek/mtk-pmic-wrap.c | 35 +++++++++++++++++++
2 files changed, 36 insertions(+)

2021-06-02 11:22:31

by James Lo

Subject: [PATCH 2/2] soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

From: Henry Chen <[email protected]>

MT8195 are highly integrated SoC and use PMIC_MT6359 for
power management. This patch adds pwrap master driver to
access PMIC_MT6359.

Signed-off-by: Henry Chen <[email protected]>
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 35 ++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index e4de75f35c33..952bc554f443 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -961,6 +961,23 @@ static int mt8183_regs[] = {
[PWRAP_WACS2_VLDCLR] = 0xC28,
};

+static int mt8195_regs[] = {
+ [PWRAP_INIT_DONE2] = 0x0,
+ [PWRAP_STAUPD_CTRL] = 0x4C,
+ [PWRAP_TIMER_EN] = 0x3E4,
+ [PWRAP_INT_EN] = 0x420,
+ [PWRAP_INT_FLG] = 0x428,
+ [PWRAP_INT_CLR] = 0x42C,
+ [PWRAP_INT1_EN] = 0x450,
+ [PWRAP_INT1_FLG] = 0x458,
+ [PWRAP_INT1_CLR] = 0x45C,
+ [PWRAP_WACS2_CMD] = 0x880,
+ [PWRAP_SWINF_2_WDATA_31_0] = 0x884,
+ [PWRAP_SWINF_2_RDATA_31_0] = 0x894,
+ [PWRAP_WACS2_VLDCLR] = 0x8A4,
+ [PWRAP_WACS2_RDATA] = 0x8A8,
+};
+
static int mt8516_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
@@ -1066,6 +1083,7 @@ enum pwrap_type {
PWRAP_MT8135,
PWRAP_MT8173,
PWRAP_MT8183,
+ PWRAP_MT8195,
PWRAP_MT8516,
};

@@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
break;
case PWRAP_MT6873:
case PWRAP_MT8183:
+ case PWRAP_MT8195:
break;
}

@@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
.init_soc_specific = pwrap_mt8183_init_soc_specific,
};

+static struct pmic_wrapper_type pwrap_mt8195 = {
+ .regs = mt8195_regs,
+ .type = PWRAP_MT8195,
+ .arb_en_all = 0x777f, /* NEED CONFIRM */
+ .int_en_all = 0x180000, /* NEED CONFIRM */
+ .int1_en_all = 0,
+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+ .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,
+ .init_reg_clock = pwrap_common_init_reg_clock,
+ .init_soc_specific = NULL,
+};
+
static struct pmic_wrapper_type pwrap_mt8516 = {
.regs = mt8516_regs,
.type = PWRAP_MT8516,
@@ -2065,6 +2097,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
}, {
.compatible = "mediatek,mt8183-pwrap",
.data = &pwrap_mt8183,
+ }, {
+ .compatible = "mediatek,mt8195-pwrap",
+ .data = &pwrap_mt8195,
}, {
.compatible = "mediatek,mt8516-pwrap",
.data = &pwrap_mt8516,
--
2.18.0

2021-06-03 17:46:16

by Matthias Brugger

Subject: Re: Add PMIC wrapper support for Mediatek MT8195 SoC IC

On 02/06/2021 13:20, James Lo wrote:
> This series adds support for new SoC MT8195 to the pmic-wrap driver.
>
> Henry Chen (2):
> dt-bindings: mediatek: add compatible for MT8195 pwrap
> soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

Whole series pushed to v5.13-next/soc

Thanks!

>
> .../bindings/soc/mediatek/pwrap.txt | 1 +
> drivers/soc/mediatek/mtk-pmic-wrap.c | 35 +++++++++++++++++++
> 2 files changed, 36 insertions(+)
>
>

2021-06-09 17:11:30

by Fei Shao

Subject: Re: [PATCH 2/2] soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

On Wed, Jun 2, 2021 at 7:21 PM James Lo <[email protected]> wrote:
>
> From: Henry Chen <[email protected]>
>
> MT8195 are highly integrated SoC and use PMIC_MT6359 for
> power management. This patch adds pwrap master driver to
> access PMIC_MT6359.
>
> Signed-off-by: Henry Chen <[email protected]>
> ---
> drivers/soc/mediatek/mtk-pmic-wrap.c | 35 ++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index e4de75f35c33..952bc554f443 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -961,6 +961,23 @@ static int mt8183_regs[] = {
> [PWRAP_WACS2_VLDCLR] = 0xC28,
> };
>
> +static int mt8195_regs[] = {
> + [PWRAP_INIT_DONE2] = 0x0,
> + [PWRAP_STAUPD_CTRL] = 0x4C,
> + [PWRAP_TIMER_EN] = 0x3E4,
> + [PWRAP_INT_EN] = 0x420,
> + [PWRAP_INT_FLG] = 0x428,
> + [PWRAP_INT_CLR] = 0x42C,
> + [PWRAP_INT1_EN] = 0x450,
> + [PWRAP_INT1_FLG] = 0x458,
> + [PWRAP_INT1_CLR] = 0x45C,
> + [PWRAP_WACS2_CMD] = 0x880,
> + [PWRAP_SWINF_2_WDATA_31_0] = 0x884,
> + [PWRAP_SWINF_2_RDATA_31_0] = 0x894,
> + [PWRAP_WACS2_VLDCLR] = 0x8A4,
> + [PWRAP_WACS2_RDATA] = 0x8A8,
> +};
> +
> static int mt8516_regs[] = {
> [PWRAP_MUX_SEL] = 0x0,
> [PWRAP_WRAP_EN] = 0x4,
> @@ -1066,6 +1083,7 @@ enum pwrap_type {
> PWRAP_MT8135,
> PWRAP_MT8173,
> PWRAP_MT8183,
> + PWRAP_MT8195,
> PWRAP_MT8516,
> };
>
> @@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
> break;
> case PWRAP_MT6873:
> case PWRAP_MT8183:
> + case PWRAP_MT8195:
> break;
> }
>
> @@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
> .init_soc_specific = pwrap_mt8183_init_soc_specific,
> };
>
> +static struct pmic_wrapper_type pwrap_mt8195 = {
> + .regs = mt8195_regs,
> + .type = PWRAP_MT8195,
> + .arb_en_all = 0x777f, /* NEED CONFIRM */
> + .int_en_all = 0x180000, /* NEED CONFIRM */

Please get the confirmative values here then send the next patch, thanks.


> + .int1_en_all = 0,
> + .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
> + .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
> + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,
> + .init_reg_clock = pwrap_common_init_reg_clock,
> + .init_soc_specific = NULL,
> +};
> +
> static struct pmic_wrapper_type pwrap_mt8516 = {
> .regs = mt8516_regs,
> .type = PWRAP_MT8516,
> @@ -2065,6 +2097,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
> }, {
> .compatible = "mediatek,mt8183-pwrap",
> .data = &pwrap_mt8183,
> + }, {
> + .compatible = "mediatek,mt8195-pwrap",
> + .data = &pwrap_mt8195,
> }, {
> .compatible = "mediatek,mt8516-pwrap",
> .data = &pwrap_mt8516,
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

2021-06-09 17:13:49

by Matthias Brugger

Subject: Re: [PATCH 2/2] soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

On 09/06/2021 09:51, Fei Shao wrote:
> On Wed, Jun 2, 2021 at 7:21 PM James Lo <[email protected]> wrote:
>>
>> From: Henry Chen <[email protected]>
>>
>> MT8195 are highly integrated SoC and use PMIC_MT6359 for
>> power management. This patch adds pwrap master driver to
>> access PMIC_MT6359.
>>
>> Signed-off-by: Henry Chen <[email protected]>
>> ---
>> drivers/soc/mediatek/mtk-pmic-wrap.c | 35 ++++++++++++++++++++++++++++
>> 1 file changed, 35 insertions(+)
>>
>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> index e4de75f35c33..952bc554f443 100644
>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> @@ -961,6 +961,23 @@ static int mt8183_regs[] = {
>> [PWRAP_WACS2_VLDCLR] = 0xC28,
>> };
>>
>> +static int mt8195_regs[] = {
>> + [PWRAP_INIT_DONE2] = 0x0,
>> + [PWRAP_STAUPD_CTRL] = 0x4C,
>> + [PWRAP_TIMER_EN] = 0x3E4,
>> + [PWRAP_INT_EN] = 0x420,
>> + [PWRAP_INT_FLG] = 0x428,
>> + [PWRAP_INT_CLR] = 0x42C,
>> + [PWRAP_INT1_EN] = 0x450,
>> + [PWRAP_INT1_FLG] = 0x458,
>> + [PWRAP_INT1_CLR] = 0x45C,
>> + [PWRAP_WACS2_CMD] = 0x880,
>> + [PWRAP_SWINF_2_WDATA_31_0] = 0x884,
>> + [PWRAP_SWINF_2_RDATA_31_0] = 0x894,
>> + [PWRAP_WACS2_VLDCLR] = 0x8A4,
>> + [PWRAP_WACS2_RDATA] = 0x8A8,
>> +};
>> +
>> static int mt8516_regs[] = {
>> [PWRAP_MUX_SEL] = 0x0,
>> [PWRAP_WRAP_EN] = 0x4,
>> @@ -1066,6 +1083,7 @@ enum pwrap_type {
>> PWRAP_MT8135,
>> PWRAP_MT8173,
>> PWRAP_MT8183,
>> + PWRAP_MT8195,
>> PWRAP_MT8516,
>> };
>>
>> @@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
>> break;
>> case PWRAP_MT6873:
>> case PWRAP_MT8183:
>> + case PWRAP_MT8195:
>> break;
>> }
>>
>> @@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
>> .init_soc_specific = pwrap_mt8183_init_soc_specific,
>> };
>>
>> +static struct pmic_wrapper_type pwrap_mt8195 = {
>> + .regs = mt8195_regs,
>> + .type = PWRAP_MT8195,
>> + .arb_en_all = 0x777f, /* NEED CONFIRM */
>> + .int_en_all = 0x180000, /* NEED CONFIRM */
>
> Please get the confirmative values here then send the next patch, thanks.
>

Yes please. You can send this as a follow-up patch, otherwise I'd need to remove
this from my queue, as I have overseen the fact that not all values are confirmed.

Regards,
Matthias

2021-06-10 02:48:58

by James Lo

Subject: Re: [PATCH 2/2] soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

On Wed, 2021-06-09 at 10:06 +0200, Matthias Brugger wrote:
>
> On 09/06/2021 09:51, Fei Shao wrote:
> > On Wed, Jun 2, 2021 at 7:21 PM James Lo <[email protected]>
> > wrote:
> > >
> > > From: Henry Chen <[email protected]>
> > >
> > > MT8195 are highly integrated SoC and use PMIC_MT6359 for
> > > power management. This patch adds pwrap master driver to
> > > access PMIC_MT6359.
> > >
> > > Signed-off-by: Henry Chen <[email protected]>
> > > ---
> > > drivers/soc/mediatek/mtk-pmic-wrap.c | 35
> > > ++++++++++++++++++++++++++++
> > > 1 file changed, 35 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
> > > b/drivers/soc/mediatek/mtk-pmic-wrap.c
> > > index e4de75f35c33..952bc554f443 100644
> > > --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> > > +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> > > @@ -961,6 +961,23 @@ static int mt8183_regs[] = {
> > > [PWRAP_WACS2_VLDCLR] = 0xC28,
> > > };
> > >
> > > +static int mt8195_regs[] = {
> > > + [PWRAP_INIT_DONE2] = 0x0,
> > > + [PWRAP_STAUPD_CTRL] = 0x4C,
> > > + [PWRAP_TIMER_EN] = 0x3E4,
> > > + [PWRAP_INT_EN] = 0x420,
> > > + [PWRAP_INT_FLG] = 0x428,
> > > + [PWRAP_INT_CLR] = 0x42C,
> > > + [PWRAP_INT1_EN] = 0x450,
> > > + [PWRAP_INT1_FLG] = 0x458,
> > > + [PWRAP_INT1_CLR] = 0x45C,
> > > + [PWRAP_WACS2_CMD] = 0x880,
> > > + [PWRAP_SWINF_2_WDATA_31_0] = 0x884,
> > > + [PWRAP_SWINF_2_RDATA_31_0] = 0x894,
> > > + [PWRAP_WACS2_VLDCLR] = 0x8A4,
> > > + [PWRAP_WACS2_RDATA] = 0x8A8,
> > > +};
> > > +
> > > static int mt8516_regs[] = {
> > > [PWRAP_MUX_SEL] = 0x0,
> > > [PWRAP_WRAP_EN] = 0x4,
> > > @@ -1066,6 +1083,7 @@ enum pwrap_type {
> > > PWRAP_MT8135,
> > > PWRAP_MT8173,
> > > PWRAP_MT8183,
> > > + PWRAP_MT8195,
> > > PWRAP_MT8516,
> > > };
> > >
> > > @@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct
> > > pmic_wrapper *wrp)
> > > break;
> > > case PWRAP_MT6873:
> > > case PWRAP_MT8183:
> > > + case PWRAP_MT8195:
> > > break;
> > > }
> > >
> > > @@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type
> > > pwrap_mt8183 = {
> > > .init_soc_specific = pwrap_mt8183_init_soc_specific,
> > > };
> > >
> > > +static struct pmic_wrapper_type pwrap_mt8195 = {
> > > + .regs = mt8195_regs,
> > > + .type = PWRAP_MT8195,
> > > + .arb_en_all = 0x777f, /* NEED CONFIRM */
> > > + .int_en_all = 0x180000, /* NEED CONFIRM */
> >
> > Please get the confirmative values here then send the next patch,
> > thanks.
> >
>
> Yes please. You can send this as a follow-up patch, otherwise I'd
> need to remove
> this from my queue, as I have overseen the fact that not all values
> are confirmed.
>
> Regards,
> Matthias

All values are confirmed and sorry for I forget to remove those
comments. Could you please help us to remove those comments ?

Before :
.arb_en_all = 0x777f, /* NEED CONFIRM */
.int_en_all = 0x180000, /* NEED CONFIRM */

After :
.arb_en_all = 0x777f,
.int_en_all = 0x180000,

Many thanks
James Lo