Hi everyone,
Here's a (pretty long) series to introduce support in the VC4 DRM driver
for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
The main differences are that there's two HDMI controllers and that there's
more pixelvalve now. Those pixelvalve come with a mux in the HVS that still
have only 3 FIFOs. Both of those differences are breaking a bunch of
expectations in the driver, so we first need a good bunch of cleanup and
reworks to introduce support for the new controllers.
Similarly, the HDMI controller has all its registers shuffled and split in
multiple controllers now, so we need a bunch of changes to support this as
well.
Only the HDMI support is enabled for now (even though the DPI and DSI
outputs have been tested too).
Let me know if you have any comments
Maxime
Cc: [email protected]
Cc: [email protected]
Cc: Kamal Dasu <[email protected]>
Cc: [email protected]
Cc: Michael Turquette <[email protected]>
Cc: Philipp Zabel <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Changes from v3:
- Rebased on top of next-20200708
- Added a name to the HDMI audio codec component
- Only disable the BCM2711 HDMI pixelvalves at boot
- Fixed an error in the HVS binding
- Fix a framebuffer size condition that was inverted
- Changed the channel allocation algorithm using Eric's suggestion
- Always write the muxing values instead of updating if needed
- Improved a bit the hvs_available_channels comment in the structure
- Change atomic_complete_commit code to use for_each_new_crtc_in_state
- Change the muxing code to take into account disparities between the
BCM2711 and previous SoCs.
- Only change the clock rate on BCM2711 during a modeset
- Fix a crash at atomic_disable
- Use clk_set_min_rate for the core clock too
- Add a few defines, and simplify the FIFO level stuff
- Reordered the patches according to Eric's reviews
- Fixed a regression with VID_CTL setting on RPI3
Changes from v2:
- Rebased on top of next-20200526
- Split the firmware clock series away
- Removed the stuck pixel (with all the subsequent pixels being shifted
by one
- Fixed the writeback issue too.
- Fix the dual output
- Fixed the return value of phy_get_cp_current
- Enhanced the comment on the reset delay
- Increase the max width and height
- Made a proper Kconfig option for the DVP clock driver
- Fixed the alsa card name collision
Changes from v1:
- Rebased on top of 5.7-rc1
- Run checkpatch
- Added audio support
- Fixed some HDMI timeouts
- Swiched to clk_hw_register_gate_parent_data
- Reorder Kconfig symbols in drivers/i2c/busses
- Make the firmware clocks a child of the firmware node
- Switch DVP clock driver to clk_hw interface
- constify raspberrypi_clk_data in raspberrypi_clock_property
- Don't mark firmware clocks as IGNORE_UNUSED
- Change from reset_ms to reset_us in reset-simple, and add a bit more
comments
- Remove generic clk patch to test if a NULL pointer is returned
- Removed misleading message in the is_prepared renaming patch commit
message
- Constify HDMI controller variants
- Fix a bug in the allocation size of the clk data array
- Added a mention in the DT binding conversion patches about the breakage
- Merged a few fixes from kbuild
- Fixed a few bisection and CEC build issues
- Collected Acked-by and Reviewed-by
- Change Dave email address to raspberrypi.com
Dave Stevenson (7):
drm/vc4: Add support for the BCM2711 HVS5
drm/vc4: plane: Change LBM alignment constraint on LBM
drm/vc4: plane: Optimize the LBM allocation size
drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers
drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming
drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default.
drm/vc4: hdmi: Add audio-related callbacks
Maxime Ripard (71):
dt-bindings: display: Add support for the BCM2711 HVS
drm/vc4: hvs: Boost the core clock during modeset
drm/vc4: plane: Create more planes
drm/vc4: crtc: Deal with different number of pixel per clock
drm/vc4: crtc: Use a shared interrupt
drm/vc4: crtc: Move the cob allocation outside of bind
drm/vc4: crtc: Rename HVS channel to output
drm/vc4: crtc: Use local chan variable
drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable
drm/vc4: kms: Convert to for_each_new_crtc_state
drm/vc4: crtc: Assign output to channel automatically
drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
drm/vc4: crtc: Add function to compute FIFO level bits
drm/vc4: crtc: Rename HDMI encoder type to HDMI0
drm/vc4: crtc: Add HDMI1 encoder type
drm/vc4: crtc: Disable color management for HVS5
drm/vc4: crtc: Turn pixelvalve reset into a function
drm/vc4: crtc: Move PV dump to config_pv
drm/vc4: crtc: Move HVS init and close to a function
drm/vc4: crtc: Move the HVS gamma LUT setup to our init function
drm/vc4: hvs: Make sure our channel is reset
drm/vc4: crtc: Remove mode_set_nofb
drm/vc4: crtc: Remove redundant pixelvalve reset
drm/vc4: crtc: Move HVS channel init before the PV initialisation
drm/vc4: encoder: Add finer-grained encoder callbacks
drm/vc4: crtc: Add a delay after disabling the PixelValve output
drm/vc4: crtc: Clear the PixelValve FIFO on disable
drm/vc4: crtc: Clear the PixelValve FIFO during configuration
drm/vc4: hvs: Make the stop_channel function public
drm/vc4: hvs: Introduce a function to get the assigned FIFO
drm/vc4: crtc: Move the CRTC disable out
drm/vc4: drv: Disable the CRTC at boot time
dt-bindings: display: vc4: pv: Add BCM2711 pixel valves
drm/vc4: crtc: Add BCM2711 pixelvalves
drm/vc4: hdmi: Use debugfs private field
drm/vc4: hdmi: Move structure to header
drm/vc4: hdmi: rework connectors and encoders
drm/vc4: hdmi: Remove DDC argument to connector_init
drm/vc4: hdmi: Rename hdmi to vc4_hdmi
drm/vc4: hdmi: Move accessors to vc4_hdmi
drm/vc4: hdmi: Use local vc4_hdmi directly
drm/vc4: hdmi: Add container_of macros for encoders and connectors
drm/vc4: hdmi: Pass vc4_hdmi to CEC code
drm/vc4: hdmi: Retrieve the vc4_hdmi at unbind using our device
drm/vc4: hdmi: Remove vc4_dev hdmi pointer
drm/vc4: hdmi: Remove vc4_hdmi_connector
drm/vc4: hdmi: Introduce resource init and variant
drm/vc4: hdmi: Implement a register layout abstraction
drm/vc4: hdmi: Add reset callback
drm/vc4: hdmi: Add PHY init and disable function
drm/vc4: hdmi: Add PHY RNG enable / disable function
drm/vc4: hdmi: Add a CSC setup callback
drm/vc4: hdmi: Store the encoder type in the variant structure
drm/vc4: hdmi: Deal with multiple debugfs files
drm/vc4: hdmi: Move CEC init to its own function
drm/vc4: hdmi: Add CEC support flag
drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define
drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid
drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate
drm/vc4: hdmi: Use clk_set_min_rate instead
drm/vc4: hdmi: Deal with multiple ALSA cards
drm/vc4: hdmi: Remove register dumps in enable
drm/vc4: hdmi: Always recenter the HDMI FIFO
drm/vc4: hdmi: Implement finer-grained hooks
drm/vc4: hdmi: Do the VID_CTL configuration at once
drm/vc4: hdmi: Switch to blank pixels when disabled
drm/vc4: hdmi: Support the BCM2711 HDMI controllers
dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings
dt-bindings: display: vc4: Document BCM2711 VC5
drm/vc4: drv: Support BCM2711
ARM: dts: bcm2711: Enable the display pipeline
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml | 109 +++++-
Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 18 +-
Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 5 +-
Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 +-
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 46 ++-
arch/arm/boot/dts/bcm2711.dtsi | 115 ++++-
drivers/gpu/drm/vc4/Makefile | 1 +-
drivers/gpu/drm/vc4/vc4_crtc.c | 338 +++++++++++----
drivers/gpu/drm/vc4/vc4_drv.c | 5 +-
drivers/gpu/drm/vc4/vc4_drv.h | 43 +-
drivers/gpu/drm/vc4/vc4_hdmi.c | 1625 +++++++++++++++++++++++++++++++++++++++++++-----------------------------
drivers/gpu/drm/vc4/vc4_hdmi.h | 183 ++++++++-
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 520 +++++++++++++++++++++++-
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 442 ++++++++++++++++++++-
drivers/gpu/drm/vc4/vc4_hvs.c | 260 +++++++-----
drivers/gpu/drm/vc4/vc4_kms.c | 225 +++++++++-
drivers/gpu/drm/vc4/vc4_plane.c | 222 +++++++---
drivers/gpu/drm/vc4/vc4_regs.h | 177 +++-----
drivers/gpu/drm/vc4/vc4_txp.c | 4 +-
19 files changed, 3331 insertions(+), 1008 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h
base-commit: 5bdd2824d705fb8d339d6f96e464b907c9a1553d
--
git-series 0.9.1
The VIDEN bit in the pixelvalve currently being used to enable or disable
the pixelvalve seems to not be enough in some situations, which whill end
up with the pixelvalve stalling.
In such a case, even re-enabling VIDEN doesn't bring it back and we need to
clear the FIFO. This can only be done if the pixelvalve is disabled though.
In order to overcome this, we can configure the pixelvalve during
mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO
there, and in atomic_disable disable the pixelvalve again.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index cdeaa0cd981f..fe2e5675aed4 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -332,9 +332,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
PV_CONTROL_TRIGGER_UNDERFLOW |
PV_CONTROL_WAIT_HSTART |
VC4_SET_FIELD(vc4_encoder->clock_select,
- PV_CONTROL_CLK_SELECT) |
- PV_CONTROL_FIFO_CLR |
- PV_CONTROL_EN);
+ PV_CONTROL_CLK_SELECT));
}
static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
@@ -386,6 +384,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
+
vc4_hvs_atomic_disable(crtc, old_state);
/*
@@ -410,6 +410,10 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
require_hvs_enabled(dev);
+ /* Reset the PV fifo. */
+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) |
+ PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
+
/* Enable vblank irq handling before crtc is started otherwise
* drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
*/
--
git-series 0.9.1
The BCM2711 sports a second HDMI controller, so let's add that second HDMI
encoder type.
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 5781773aec4b..4126506b3a69 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -427,6 +427,7 @@ to_vc4_plane_state(struct drm_plane_state *state)
enum vc4_encoder_type {
VC4_ENCODER_TYPE_NONE,
VC4_ENCODER_TYPE_HDMI0,
+ VC4_ENCODER_TYPE_HDMI1,
VC4_ENCODER_TYPE_VEC,
VC4_ENCODER_TYPE_DSI0,
VC4_ENCODER_TYPE_DSI1,
--
git-series 0.9.1
The COB allocation depends on the HVS channel used for a given
pixelvalve.
While the channel allocation was entirely static in vc4, vc5 changes
that and at bind time, a pixelvalve can be assigned to multiple
HVS channels.
Let's prepare that rework by allocating the COB when it's actually
needed.
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 35 +++++++++++++++++------------------
drivers/gpu/drm/vc4/vc4_drv.h | 2 +--
2 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 9faae22cb0f8..fdecaba77836 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -65,6 +65,20 @@ static const struct debugfs_reg32 crtc_regs[] = {
VC4_REG32(PV_HACT_ACT),
};
+static unsigned int
+vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
+{
+ u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
+ /* Top/base are supposed to be 4-pixel aligned, but the
+ * Raspberry Pi firmware fills the low bits (which are
+ * presumably ignored).
+ */
+ u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
+ u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
+
+ return top - base + 4;
+}
+
static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
bool in_vblank_irq,
int *vpos, int *hpos,
@@ -74,6 +88,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ unsigned int cob_size;
u32 val;
int fifo_lines;
int vblank_lines;
@@ -109,8 +124,9 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
*hpos += mode->crtc_htotal / 2;
}
+ cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc->channel);
/* This is the offset we need for translating hvs -> pv scanout pos. */
- fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
+ fifo_lines = cob_size / mode->crtc_hdisplay;
if (fifo_lines > 0)
ret = true;
@@ -823,22 +839,6 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm,
}
}
-static void
-vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
-{
- struct drm_device *drm = vc4_crtc->base.dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
- u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
- /* Top/base are supposed to be 4-pixel aligned, but the
- * Raspberry Pi firmware fills the low bits (which are
- * presumably ignored).
- */
- u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
- u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
-
- vc4_crtc->cob_size = top - base + 4;
-}
-
int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
const struct drm_crtc_funcs *crtc_funcs,
const struct drm_crtc_helper_funcs *crtc_helper_funcs)
@@ -870,7 +870,6 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
* implemented as private driver state in vc4_kms, not here.
*/
drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
- vc4_crtc_get_cob_allocation(vc4_crtc);
for (i = 0; i < crtc->gamma_size; i++) {
vc4_crtc->lut_r[i] = i;
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 0bc150daafb2..d80fc3bbb450 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -477,8 +477,6 @@ struct vc4_crtc {
u8 lut_r[256];
u8 lut_g[256];
u8 lut_b[256];
- /* Size in pixels of the COB memory allocated to this CRTC. */
- u32 cob_size;
struct drm_pending_vblank_event *event;
--
git-series 0.9.1
In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with
pixelvalves each being assigned to a given output, but each output can
then be muxed to feed from multiple FIFOs.
Since vc4 had that entirely static, both were probably equivalent, but
since that changes, let's rename hvs_channel to hvs_output in the
vc4_crtc_data, since a pixelvalve is really connected to an output, and
not to a FIFO.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 8 ++++----
drivers/gpu/drm/vc4/vc4_drv.h | 4 ++--
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
drivers/gpu/drm/vc4/vc4_txp.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index fdecaba77836..d3126fe04d9a 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -775,7 +775,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
static const struct vc4_pv_data bcm2835_pv0_data = {
.base = {
- .hvs_channel = 0,
+ .hvs_output = 0,
},
.debugfs_name = "crtc0_regs",
.pixels_per_clock = 1,
@@ -787,7 +787,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
static const struct vc4_pv_data bcm2835_pv1_data = {
.base = {
- .hvs_channel = 2,
+ .hvs_output = 2,
},
.debugfs_name = "crtc1_regs",
.pixels_per_clock = 1,
@@ -799,7 +799,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
static const struct vc4_pv_data bcm2835_pv2_data = {
.base = {
- .hvs_channel = 1,
+ .hvs_output = 1,
},
.debugfs_name = "crtc2_regs",
.pixels_per_clock = 1,
@@ -862,7 +862,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
crtc_funcs, NULL);
drm_crtc_helper_add(crtc, crtc_helper_funcs);
- vc4_crtc->channel = vc4_crtc->data->hvs_channel;
+ vc4_crtc->channel = vc4_crtc->data->hvs_output;
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index d80fc3bbb450..d1cf4c038180 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -447,8 +447,8 @@ to_vc4_encoder(struct drm_encoder *encoder)
}
struct vc4_crtc_data {
- /* Which channel of the HVS this pixelvalve sources from. */
- int hvs_channel;
+ /* Which output of the HVS this pixelvalve sources from. */
+ int hvs_output;
};
struct vc4_pv_data {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 091fdf4908aa..6fd9de1dc65a 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -419,7 +419,7 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
- if (vc4_crtc->data->hvs_channel == 2) {
+ if (vc4_crtc->data->hvs_output == 2) {
u32 dispctrl;
u32 dsp3_mux;
diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c
index a7c3af0005a0..f39d9900d027 100644
--- a/drivers/gpu/drm/vc4/vc4_txp.c
+++ b/drivers/gpu/drm/vc4/vc4_txp.c
@@ -452,7 +452,7 @@ static irqreturn_t vc4_txp_interrupt(int irq, void *data)
}
static const struct vc4_crtc_data vc4_txp_crtc_data = {
- .hvs_channel = 2,
+ .hvs_output = 2,
};
static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
--
git-series 0.9.1
The vc4_crtc_handle_page_flip already has a local variable holding the
value of vc4_crtc->channel, so let's use it instead.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index d3126fe04d9a..cdeaa0cd981f 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -533,7 +533,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
* the CRTC and encoder already reconfigured, leading to
* underruns. This can be seen when reconfiguring the CRTC.
*/
- vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
+ vc4_hvs_unmask_underrun(dev, chan);
}
spin_unlock_irqrestore(&dev->event_lock, flags);
}
--
git-series 0.9.1
From: Dave Stevenson <[email protected]>
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Signed-off-by: Dave Stevenson <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_drv.h | 4 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 34 ++++--
drivers/gpu/drm/vc4/vc4_plane.c | 194 ++++++++++++++++++++++++---------
drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++-
4 files changed, 240 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index fa19160c801f..e4cde1f9224b 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -329,7 +329,11 @@ struct vc4_hvs {
spinlock_t mm_lock;
struct drm_mm_node mitchell_netravali_filter;
+
struct debugfs_regset32 regset;
+
+ /* HVS version 5 flag, therefore requires updated dlist structures */
+ bool hvs5;
};
struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 2d2bf59c0503..836d8799d79e 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -277,11 +277,19 @@ void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
* mode.
*/
dispctrl = SCALER_DISPCTRLX_ENABLE;
- dispctrl |= VC4_SET_FIELD(mode->hdisplay,
- SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay,
- SCALER_DISPCTRLX_HEIGHT) |
- (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
}
@@ -521,6 +529,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->pdev = pdev;
+ if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
+ hvs->hvs5 = true;
+
hvs->regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(hvs->regs))
return PTR_ERR(hvs->regs);
@@ -529,7 +540,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
- hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ if (!hvs->hvs5)
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ else
+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
spin_lock_init(&hvs->mm_lock);
@@ -547,7 +561,12 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
* between planes when they don't overlap on the screen, but
* for now we just allocate globally.
*/
- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ if (!hvs->hvs5)
+ /* 96kB */
+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ else
+ /* 70k words */
+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.
@@ -632,6 +651,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_hvs_dt_match[] = {
+ { .compatible = "brcm,bcm2711-hvs" },
{ .compatible = "brcm,bcm2835-hvs" },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index d040d9f12c6d..20c949b57827 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -32,45 +32,60 @@ static const struct hvs_format {
u32 drm; /* DRM_FORMAT_* */
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
+ u32 pixel_order_hvs5;
} hvs_formats[] = {
{
- .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XRGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ARGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ABGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XBGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_RGB565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_BGR565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
- .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_ARGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_XRGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_RGB888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_BGR888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
@@ -776,35 +791,6 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
return -EINVAL;
}
- /* Control word */
- vc4_dlist_write(vc4_state,
- SCALER_CTL0_VALID |
- (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
- (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
- VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
- (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
- (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
- VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
- (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
- VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
- VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
-
- /* Position Word 0: Image Positions and Alpha Value */
- vc4_state->pos0_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
- VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
- VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
-
- /* Position Word 1: Scaled Image Dimensions. */
- if (!vc4_state->is_unity) {
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(vc4_state->crtc_w,
- SCALER_POS1_SCL_WIDTH) |
- VC4_SET_FIELD(vc4_state->crtc_h,
- SCALER_POS1_SCL_HEIGHT));
- }
-
/* Don't waste cycles mixing with plane alpha if the set alpha
* is opaque or there is no per-pixel alpha information.
* In any case we use the alpha property value as the fixed alpha.
@@ -812,20 +798,120 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
fb->format->has_alpha;
- /* Position Word 2: Source Image Size, Alpha */
- vc4_state->pos2_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(fb->format->has_alpha ?
- SCALER_POS2_ALPHA_MODE_PIPELINE :
- SCALER_POS2_ALPHA_MODE_FIXED,
- SCALER_POS2_ALPHA_MODE) |
- (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
- (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
- VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
- VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
+ if (!vc4->hvs->hvs5) {
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
+ (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
+ VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size, Alpha */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+ (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
+ (fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_PREMULT : 0) |
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+ } else {
+ u32 hvs_pixel_order = format->pixel_order;
- /* Position Word 3: Context. Written by the HVS. */
- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ if (format->pixel_order_hvs5)
+ hvs_pixel_order = format->pixel_order_hvs5;
+
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ?
+ SCALER5_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
+ SCALER5_CTL0_ALPHA_EXPAND |
+ SCALER5_CTL0_RGB_EXPAND);
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ (rotation & DRM_MODE_REFLECT_Y ?
+ SCALER5_POS0_VFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_x,
+ SCALER_POS0_START_X) |
+ (rotation & DRM_MODE_REFLECT_X ?
+ SCALER5_POS0_HFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_y,
+ SCALER5_POS0_START_Y)
+ );
+
+ /* Control Word 2 */
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 4,
+ SCALER5_CTL2_ALPHA) |
+ fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_PREMULT : 0 |
+ (mix_plane_alpha ?
+ SCALER5_CTL2_ALPHA_MIX : 0) |
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_MODE_PIPELINE :
+ SCALER5_CTL2_ALPHA_MODE_FIXED,
+ SCALER5_CTL2_ALPHA_MODE)
+ );
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER5_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER5_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
@@ -1203,6 +1289,10 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
default:
return false;
}
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_BGRX1010102:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YVU422:
case DRM_FORMAT_YUV420:
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 324462cc9cd4..91b785725555 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -327,6 +327,20 @@
# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
+# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
+# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
+/* Generates a single frame when VSTART is seen and stops at the last
+ * pixel read from the FIFO.
+ */
+# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
+/* Processes a single context in the dlist and then task switch,
+ * instead of an entire line.
+ */
+# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
+# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
+# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
+
#define SCALER_DISPBKGND0 0x00000044
# define SCALER_DISPBKGND_AUTOHS BIT(31)
# define SCALER_DISPBKGND_INTERLACE BIT(30)
@@ -460,6 +474,8 @@
#define SCALER_DLIST_START 0x00002000
#define SCALER_DLIST_SIZE 0x00004000
+#define SCALER5_DLIST_START 0x00004000
+
#define VC4_HDMI_CORE_REV 0x000
#define VC4_HDMI_SW_RESET_CONTROL 0x004
@@ -825,6 +841,8 @@ enum hvs_pixel_format {
HVS_PIXEL_FORMAT_PALETTE = 13,
HVS_PIXEL_FORMAT_YUV444_RGB = 14,
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
+ HVS_PIXEL_FORMAT_RGBA1010102 = 16,
+ HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
};
/* Note: the LSB is the rightmost character shown. Only valid for
@@ -879,6 +897,10 @@ enum hvs_pixel_format {
#define SCALER_CTL0_RGBA_EXPAND_MSB 2
#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
+#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
+
+#define SCALER5_CTL0_RGB_EXPAND BIT(11)
+
#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
#define SCALER_CTL0_SCL1_SHIFT 8
@@ -896,10 +918,13 @@ enum hvs_pixel_format {
/* Set to indicate no scaling. */
#define SCALER_CTL0_UNITY BIT(4)
+#define SCALER5_CTL0_UNITY BIT(15)
#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
+#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
+
#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
@@ -909,12 +934,48 @@ enum hvs_pixel_format {
#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
#define SCALER_POS0_START_X_SHIFT 0
+#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
+#define SCALER5_POS0_START_Y_SHIFT 16
+
+#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
+#define SCALER5_POS0_START_X_SHIFT 0
+
+#define SCALER5_POS0_VFLIP BIT(31)
+#define SCALER5_POS0_HFLIP BIT(15)
+
+#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
+#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
+#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
+
+#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
+
+#define SCALER5_CTL2_ALPHA_MIX BIT(28)
+
+#define SCALER5_CTL2_ALPHA_LOC BIT(25)
+
+#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
+#define SCALER5_CTL2_MAP_SEL_SHIFT 17
+
+#define SCALER5_CTL2_GAMMA BIT(16)
+
+#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
+#define SCALER5_CTL2_ALPHA_SHIFT 4
+
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS1_SCL_WIDTH_SHIFT 0
+#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
+
+#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
+
#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
#define SCALER_POS2_ALPHA_MODE_SHIFT 30
#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
@@ -930,6 +991,12 @@ enum hvs_pixel_format {
#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS2_WIDTH_SHIFT 0
+#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS2_HEIGHT_SHIFT 16
+
+#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS2_WIDTH_SHIFT 0
+
/* Color Space Conversion words. Some values are S2.8 signed
* integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
* 0x2: 2, 0x3: -1}
--
git-series 0.9.1
Hi Maxime,
Thanks for your version 4 patch again.
I took the patches and applied them upon next-20200708.
I make system cold reboot to multi-user target and the text console shows on the
screen. Then, I simply hot re-plug the HDMI cable on HDMI0 port, I not only lose
the text console on the screen (the display shows blank, backlight is off), but
also kernel does not probe modes for the HDMI connector again.
But HDMI1 does probe modes again for hot re-plugging. So, HDMI1 does not hit the
issue like HDMI0.
* System probes modes only once for HDMI0 port (HDMI-A-1), even hot re-plug HDMI
cable to the same port:
[ 15.611072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:32:HDMI-A-1] probed modes :
[ 15.611079] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 15.611085] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
...
[ 15.611298] [drm:drm_mode_debug_printmodeline] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[ 15.611303] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:38:HDMI-A-2]
[ 15.612184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:38:HDMI-A-2] disconnected
[ 15.612191] [drm:drm_client_modeset_probe] connector 32 enabled? yes
[ 15.612194] [drm:drm_client_modeset_probe] connector 38 enabled? no
[ 15.612206] [drm:drm_client_modeset_probe] Not using firmware configuration
[ 15.612213] [drm:drm_client_modeset_probe] looking for cmdline mode on connector 32
[ 15.612218] [drm:drm_client_modeset_probe] looking for preferred mode on connector 32 0
[ 15.612221] [drm:drm_client_modeset_probe] found mode 1920x1080
...
[ 108.263384] [drm:output_poll_execute] [CONNECTOR:32:HDMI-A-1] status updated from disconnected to connected
[ 108.264307] vc4-drm gpu: [drm:drm_fb_helper_hotplug_event.part.0]
[ 108.264312] [drm:drm_client_modeset_probe]
[ 108.264321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:32:HDMI-A-1]
[ 109.303379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:38:HDMI-A-2]
[ 109.304258] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:38:HDMI-A-2] disconnected
[ 109.304266] [drm:drm_client_modeset_probe] No connectors reported connected with modes
* System probes modes again for HDMI1 port (HDMI-A-2), whenever hot re-plug the
HDMI cable:
[ 797.974649] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:38:HDMI-A-2] probed modes :
[ 797.974656] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 797.974662] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
...
[ 797.974874] [drm:drm_mode_debug_printmodeline] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[ 797.974880] [drm:drm_client_modeset_probe] connector 32 enabled? no
[ 797.974883] [drm:drm_client_modeset_probe] connector 38 enabled? yes
[ 797.974895] [drm:drm_client_modeset_probe] Not using firmware configuration
[ 797.974901] [drm:drm_client_modeset_probe] looking for cmdline mode on connector 38
[ 797.974905] [drm:drm_client_modeset_probe] looking for preferred mode on connector 38 0
[ 797.974908] [drm:drm_client_modeset_probe] found mode 1920x1080
...
[ 852.242615] vc4-drm gpu: [drm:drm_client_dev_hotplug] fbdev: ret=0
[ 873.718277] [drm:output_poll_execute] [CONNECTOR:38:HDMI-A-2] status updated from disconnected to connected
[ 873.718332] vc4-drm gpu: [drm:drm_fb_helper_hotplug_event.part.0]
[ 873.718338] [drm:drm_client_modeset_probe]
...
[ 874.264013] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:38:HDMI-A-2] probed modes :
[ 874.264020] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 874.264026] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
...
[ 874.264239] [drm:drm_mode_debug_printmodeline] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[ 874.264244] [drm:drm_client_modeset_probe] connector 32 enabled? no
[ 874.264247] [drm:drm_client_modeset_probe] connector 38 enabled? yes
[ 874.264259] [drm:drm_client_modeset_probe] Not using firmware configuration
[ 874.264264] [drm:drm_client_modeset_probe] looking for cmdline mode on connector 38
[ 874.264268] [drm:drm_client_modeset_probe] looking for preferred mode on connector 38 0
[ 874.264272] [drm:drm_client_modeset_probe] found mode 1920x1080
Here is the full dmesg: https://gist.github.com/starnight/5ffb86af552fedb9b6e5741d0540a878#file-dmesg-v4-log
Hi Maxime,
Am 08.07.20 um 19:41 schrieb Maxime Ripard:
> Hi everyone,
>
> Here's a (pretty long) series to introduce support in the VC4 DRM driver
> for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
>
> The main differences are that there's two HDMI controllers and that there's
> more pixelvalve now. Those pixelvalve come with a mux in the HVS that still
> have only 3 FIFOs. Both of those differences are breaking a bunch of
> expectations in the driver, so we first need a good bunch of cleanup and
> reworks to introduce support for the new controllers.
>
> Similarly, the HDMI controller has all its registers shuffled and split in
> multiple controllers now, so we need a bunch of changes to support this as
> well.
>
> Only the HDMI support is enabled for now (even though the DPI and DSI
> outputs have been tested too).
>
> Let me know if you have any comments
> Maxime
>
> Cc: [email protected]
> Cc: [email protected]
> Cc: Kamal Dasu <[email protected]>
> Cc: [email protected]
> Cc: Michael Turquette <[email protected]>
> Cc: Philipp Zabel <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Stephen Boyd <[email protected]>
>
> Changes from v3:
> - Rebased on top of next-20200708
> - Added a name to the HDMI audio codec component
> - Only disable the BCM2711 HDMI pixelvalves at boot
> - Fixed an error in the HVS binding
> - Fix a framebuffer size condition that was inverted
> - Changed the channel allocation algorithm using Eric's suggestion
> - Always write the muxing values instead of updating if needed
> - Improved a bit the hvs_available_channels comment in the structure
> - Change atomic_complete_commit code to use for_each_new_crtc_in_state
> - Change the muxing code to take into account disparities between the
> BCM2711 and previous SoCs.
> - Only change the clock rate on BCM2711 during a modeset
> - Fix a crash at atomic_disable
> - Use clk_set_min_rate for the core clock too
> - Add a few defines, and simplify the FIFO level stuff
> - Reordered the patches according to Eric's reviews
> - Fixed a regression with VID_CTL setting on RPI3
>
i additionally applied "drm/vc4/vc4_hdmi: fill ASoC card owner" on top
of your series (potential merge conflict).
I didn't see any issues with a RPI 3B or RPI 4B.
So this whole series is
Tested-by: Stefan Wahren <[email protected]>
Regards
Stefan
Hi Maxime
On Wed, 8 Jul 2020 at 18:42, Maxime Ripard <[email protected]> wrote:
>
> In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with
> pixelvalves each being assigned to a given output, but each output can
> then be muxed to feed from multiple FIFOs.
>
> Since vc4 had that entirely static, both were probably equivalent, but
> since that changes, let's rename hvs_channel to hvs_output in the
> vc4_crtc_data, since a pixelvalve is really connected to an output, and
> not to a FIFO.
>
> Signed-off-by: Maxime Ripard <[email protected]>
Reviewed-by: Dave Stevenson <[email protected]>
> ---
> drivers/gpu/drm/vc4/vc4_crtc.c | 8 ++++----
> drivers/gpu/drm/vc4/vc4_drv.h | 4 ++--
> drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
> drivers/gpu/drm/vc4/vc4_txp.c | 2 +-
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index fdecaba77836..d3126fe04d9a 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -775,7 +775,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
>
> static const struct vc4_pv_data bcm2835_pv0_data = {
> .base = {
> - .hvs_channel = 0,
> + .hvs_output = 0,
> },
> .debugfs_name = "crtc0_regs",
> .pixels_per_clock = 1,
> @@ -787,7 +787,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
>
> static const struct vc4_pv_data bcm2835_pv1_data = {
> .base = {
> - .hvs_channel = 2,
> + .hvs_output = 2,
> },
> .debugfs_name = "crtc1_regs",
> .pixels_per_clock = 1,
> @@ -799,7 +799,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
>
> static const struct vc4_pv_data bcm2835_pv2_data = {
> .base = {
> - .hvs_channel = 1,
> + .hvs_output = 1,
> },
> .debugfs_name = "crtc2_regs",
> .pixels_per_clock = 1,
> @@ -862,7 +862,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
> drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
> crtc_funcs, NULL);
> drm_crtc_helper_add(crtc, crtc_helper_funcs);
> - vc4_crtc->channel = vc4_crtc->data->hvs_channel;
> + vc4_crtc->channel = vc4_crtc->data->hvs_output;
> drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
> drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
>
> diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
> index d80fc3bbb450..d1cf4c038180 100644
> --- a/drivers/gpu/drm/vc4/vc4_drv.h
> +++ b/drivers/gpu/drm/vc4/vc4_drv.h
> @@ -447,8 +447,8 @@ to_vc4_encoder(struct drm_encoder *encoder)
> }
>
> struct vc4_crtc_data {
> - /* Which channel of the HVS this pixelvalve sources from. */
> - int hvs_channel;
> + /* Which output of the HVS this pixelvalve sources from. */
> + int hvs_output;
> };
>
> struct vc4_pv_data {
> diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
> index 091fdf4908aa..6fd9de1dc65a 100644
> --- a/drivers/gpu/drm/vc4/vc4_hvs.c
> +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
> @@ -419,7 +419,7 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
> struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
>
> - if (vc4_crtc->data->hvs_channel == 2) {
> + if (vc4_crtc->data->hvs_output == 2) {
> u32 dispctrl;
> u32 dsp3_mux;
>
> diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c
> index a7c3af0005a0..f39d9900d027 100644
> --- a/drivers/gpu/drm/vc4/vc4_txp.c
> +++ b/drivers/gpu/drm/vc4/vc4_txp.c
> @@ -452,7 +452,7 @@ static irqreturn_t vc4_txp_interrupt(int irq, void *data)
> }
>
> static const struct vc4_crtc_data vc4_txp_crtc_data = {
> - .hvs_channel = 2,
> + .hvs_output = 2,
> };
>
> static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
> --
> git-series 0.9.1
Hi Maxime
On Wed, 8 Jul 2020 at 18:42, Maxime Ripard <[email protected]> wrote:
>
> The vc4_crtc_handle_page_flip already has a local variable holding the
> value of vc4_crtc->channel, so let's use it instead.
>
> Signed-off-by: Maxime Ripard <[email protected]>
Reviewed-by: Dave Stevenson <[email protected]>
> ---
> drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index d3126fe04d9a..cdeaa0cd981f 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -533,7 +533,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
> * the CRTC and encoder already reconfigured, leading to
> * underruns. This can be seen when reconfiguring the CRTC.
> */
> - vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
> + vc4_hvs_unmask_underrun(dev, chan);
> }
> spin_unlock_irqrestore(&dev->event_lock, flags);
> }
> --
> git-series 0.9.1
Hi Maxime
On Wed, 8 Jul 2020 at 18:42, Maxime Ripard <[email protected]> wrote:
>
> The VIDEN bit in the pixelvalve currently being used to enable or disable
> the pixelvalve seems to not be enough in some situations, which whill end
> up with the pixelvalve stalling.
>
> In such a case, even re-enabling VIDEN doesn't bring it back and we need to
> clear the FIFO. This can only be done if the pixelvalve is disabled though.
>
> In order to overcome this, we can configure the pixelvalve during
> mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO
> there, and in atomic_disable disable the pixelvalve again.
Very minor nitpick: the configure is in vc4_crtc_config_pv, but that
is called from mode_set_no_fb. The comment is correct from a DRM
overview perspective, but not from the actual code. Describing the DRM
call is probably the better approach, but it looks odd when compared
to the code.
> Signed-off-by: Maxime Ripard <[email protected]>
Reviewed-by: Dave Stevenson <[email protected]>
> ---
> drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index cdeaa0cd981f..fe2e5675aed4 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -332,9 +332,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
> PV_CONTROL_TRIGGER_UNDERFLOW |
> PV_CONTROL_WAIT_HSTART |
> VC4_SET_FIELD(vc4_encoder->clock_select,
> - PV_CONTROL_CLK_SELECT) |
> - PV_CONTROL_FIFO_CLR |
> - PV_CONTROL_EN);
> + PV_CONTROL_CLK_SELECT));
> }
>
> static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
> @@ -386,6 +384,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
> ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
> WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
>
> + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
> +
> vc4_hvs_atomic_disable(crtc, old_state);
>
> /*
> @@ -410,6 +410,10 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
>
> require_hvs_enabled(dev);
>
> + /* Reset the PV fifo. */
> + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) |
> + PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
> +
> /* Enable vblank irq handling before crtc is started otherwise
> * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
> */
> --
> git-series 0.9.1
Hi Maxime,
Thank you for your version 4 patch.
I tested all 78 patches based on the next-20200708.
Dual HDMI opearation does not work normally.
flip_done timed out occurs and doesn't work.
Could you check please it.
[ 105.694541] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
[CRTC:64:crtc-3] flip_done timed out
[ 115.934994] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
[CONNECTOR:32:HDMI-A-1] flip_done timed out
[ 126.174545] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
[PLANE:60:plane-3] flip_done timed out
And there is a problem with 4k UDH not outputting...
So this problem worked as I fixed it like patches[1].
[1] [PATCH 0/3] drm/vc4: Support HDMI QHD or higher output
"[PATCH v4 00/78] drm/vc4: Support BCM2711 Display Pipeline" all patches.
Tested-by: Hoegeun Kwon <[email protected]>
Best regards,
Hoegeun
> Hi everyone,
>
> Here's a (pretty long) series to introduce support in the VC4 DRM driver
> for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
>
> The main differences are that there's two HDMI controllers and that there's
> more pixelvalve now. Those pixelvalve come with a mux in the HVS that still
> have only 3 FIFOs. Both of those differences are breaking a bunch of
> expectations in the driver, so we first need a good bunch of cleanup and
> reworks to introduce support for the new controllers.
>
> Similarly, the HDMI controller has all its registers shuffled and split in
> multiple controllers now, so we need a bunch of changes to support this as
> well.
>
> Only the HDMI support is enabled for now (even though the DPI and DSI
> outputs have been tested too).
>
> Let me know if you have any comments
> Maxime
>
> Cc: [email protected]
> Cc: [email protected]
> Cc: Kamal Dasu <[email protected]>
> Cc: [email protected]
> Cc: Michael Turquette <[email protected]>
> Cc: Philipp Zabel <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Stephen Boyd <[email protected]>
>
> Changes from v3:
> - Rebased on top of next-20200708
> - Added a name to the HDMI audio codec component
> - Only disable the BCM2711 HDMI pixelvalves at boot
> - Fixed an error in the HVS binding
> - Fix a framebuffer size condition that was inverted
> - Changed the channel allocation algorithm using Eric's suggestion
> - Always write the muxing values instead of updating if needed
> - Improved a bit the hvs_available_channels comment in the structure
> - Change atomic_complete_commit code to use for_each_new_crtc_in_state
> - Change the muxing code to take into account disparities between the
> BCM2711 and previous SoCs.
> - Only change the clock rate on BCM2711 during a modeset
> - Fix a crash at atomic_disable
> - Use clk_set_min_rate for the core clock too
> - Add a few defines, and simplify the FIFO level stuff
> - Reordered the patches according to Eric's reviews
> - Fixed a regression with VID_CTL setting on RPI3
>
> Changes from v2:
> - Rebased on top of next-20200526
> - Split the firmware clock series away
> - Removed the stuck pixel (with all the subsequent pixels being shifted
> by one
> - Fixed the writeback issue too.
> - Fix the dual output
> - Fixed the return value of phy_get_cp_current
> - Enhanced the comment on the reset delay
> - Increase the max width and height
> - Made a proper Kconfig option for the DVP clock driver
> - Fixed the alsa card name collision
>
> Changes from v1:
> - Rebased on top of 5.7-rc1
> - Run checkpatch
> - Added audio support
> - Fixed some HDMI timeouts
> - Swiched to clk_hw_register_gate_parent_data
> - Reorder Kconfig symbols in drivers/i2c/busses
> - Make the firmware clocks a child of the firmware node
> - Switch DVP clock driver to clk_hw interface
> - constify raspberrypi_clk_data in raspberrypi_clock_property
> - Don't mark firmware clocks as IGNORE_UNUSED
> - Change from reset_ms to reset_us in reset-simple, and add a bit more
> comments
> - Remove generic clk patch to test if a NULL pointer is returned
> - Removed misleading message in the is_prepared renaming patch commit
> message
> - Constify HDMI controller variants
> - Fix a bug in the allocation size of the clk data array
> - Added a mention in the DT binding conversion patches about the breakage
> - Merged a few fixes from kbuild
> - Fixed a few bisection and CEC build issues
> - Collected Acked-by and Reviewed-by
> - Change Dave email address to raspberrypi.com
>
> Dave Stevenson (7):
> drm/vc4: Add support for the BCM2711 HVS5
> drm/vc4: plane: Change LBM alignment constraint on LBM
> drm/vc4: plane: Optimize the LBM allocation size
> drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers
> drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming
> drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default.
> drm/vc4: hdmi: Add audio-related callbacks
>
> Maxime Ripard (71):
> dt-bindings: display: Add support for the BCM2711 HVS
> drm/vc4: hvs: Boost the core clock during modeset
> drm/vc4: plane: Create more planes
> drm/vc4: crtc: Deal with different number of pixel per clock
> drm/vc4: crtc: Use a shared interrupt
> drm/vc4: crtc: Move the cob allocation outside of bind
> drm/vc4: crtc: Rename HVS channel to output
> drm/vc4: crtc: Use local chan variable
> drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable
> drm/vc4: kms: Convert to for_each_new_crtc_state
> drm/vc4: crtc: Assign output to channel automatically
> drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
> drm/vc4: crtc: Add function to compute FIFO level bits
> drm/vc4: crtc: Rename HDMI encoder type to HDMI0
> drm/vc4: crtc: Add HDMI1 encoder type
> drm/vc4: crtc: Disable color management for HVS5
> drm/vc4: crtc: Turn pixelvalve reset into a function
> drm/vc4: crtc: Move PV dump to config_pv
> drm/vc4: crtc: Move HVS init and close to a function
> drm/vc4: crtc: Move the HVS gamma LUT setup to our init function
> drm/vc4: hvs: Make sure our channel is reset
> drm/vc4: crtc: Remove mode_set_nofb
> drm/vc4: crtc: Remove redundant pixelvalve reset
> drm/vc4: crtc: Move HVS channel init before the PV initialisation
> drm/vc4: encoder: Add finer-grained encoder callbacks
> drm/vc4: crtc: Add a delay after disabling the PixelValve output
> drm/vc4: crtc: Clear the PixelValve FIFO on disable
> drm/vc4: crtc: Clear the PixelValve FIFO during configuration
> drm/vc4: hvs: Make the stop_channel function public
> drm/vc4: hvs: Introduce a function to get the assigned FIFO
> drm/vc4: crtc: Move the CRTC disable out
> drm/vc4: drv: Disable the CRTC at boot time
> dt-bindings: display: vc4: pv: Add BCM2711 pixel valves
> drm/vc4: crtc: Add BCM2711 pixelvalves
> drm/vc4: hdmi: Use debugfs private field
> drm/vc4: hdmi: Move structure to header
> drm/vc4: hdmi: rework connectors and encoders
> drm/vc4: hdmi: Remove DDC argument to connector_init
> drm/vc4: hdmi: Rename hdmi to vc4_hdmi
> drm/vc4: hdmi: Move accessors to vc4_hdmi
> drm/vc4: hdmi: Use local vc4_hdmi directly
> drm/vc4: hdmi: Add container_of macros for encoders and connectors
> drm/vc4: hdmi: Pass vc4_hdmi to CEC code
> drm/vc4: hdmi: Retrieve the vc4_hdmi at unbind using our device
> drm/vc4: hdmi: Remove vc4_dev hdmi pointer
> drm/vc4: hdmi: Remove vc4_hdmi_connector
> drm/vc4: hdmi: Introduce resource init and variant
> drm/vc4: hdmi: Implement a register layout abstraction
> drm/vc4: hdmi: Add reset callback
> drm/vc4: hdmi: Add PHY init and disable function
> drm/vc4: hdmi: Add PHY RNG enable / disable function
> drm/vc4: hdmi: Add a CSC setup callback
> drm/vc4: hdmi: Store the encoder type in the variant structure
> drm/vc4: hdmi: Deal with multiple debugfs files
> drm/vc4: hdmi: Move CEC init to its own function
> drm/vc4: hdmi: Add CEC support flag
> drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define
> drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid
> drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate
> drm/vc4: hdmi: Use clk_set_min_rate instead
> drm/vc4: hdmi: Deal with multiple ALSA cards
> drm/vc4: hdmi: Remove register dumps in enable
> drm/vc4: hdmi: Always recenter the HDMI FIFO
> drm/vc4: hdmi: Implement finer-grained hooks
> drm/vc4: hdmi: Do the VID_CTL configuration at once
> drm/vc4: hdmi: Switch to blank pixels when disabled
> drm/vc4: hdmi: Support the BCM2711 HDMI controllers
> dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings
> dt-bindings: display: vc4: Document BCM2711 VC5
> drm/vc4: drv: Support BCM2711
> ARM: dts: bcm2711: Enable the display pipeline
>
> Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml | 109 +++++-
> Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 18 +-
> Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 5 +-
> Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 +-
> arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 46 ++-
> arch/arm/boot/dts/bcm2711.dtsi | 115 ++++-
> drivers/gpu/drm/vc4/Makefile | 1 +-
> drivers/gpu/drm/vc4/vc4_crtc.c | 338 +++++++++++----
> drivers/gpu/drm/vc4/vc4_drv.c | 5 +-
> drivers/gpu/drm/vc4/vc4_drv.h | 43 +-
> drivers/gpu/drm/vc4/vc4_hdmi.c | 1625 +++++++++++++++++++++++++++++++++++++++++++-----------------------------
> drivers/gpu/drm/vc4/vc4_hdmi.h | 183 ++++++++-
> drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 520 +++++++++++++++++++++++-
> drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 442 ++++++++++++++++++++-
> drivers/gpu/drm/vc4/vc4_hvs.c | 260 +++++++-----
> drivers/gpu/drm/vc4/vc4_kms.c | 225 +++++++++-
> drivers/gpu/drm/vc4/vc4_plane.c | 222 +++++++---
> drivers/gpu/drm/vc4/vc4_regs.h | 177 +++-----
> drivers/gpu/drm/vc4/vc4_txp.c | 4 +-
> 19 files changed, 3331 insertions(+), 1008 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
> create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h
> create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c
> create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h
>
> base-commit: 5bdd2824d705fb8d339d6f96e464b907c9a1553d
Hi Maxime,
On 7/9/20 2:41 AM, Maxime Ripard wrote:
> Hi everyone,
>
> Here's a (pretty long) series to introduce support in the VC4 DRM driver
> for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
>
> The main differences are that there's two HDMI controllers and that there's
> more pixelvalve now. Those pixelvalve come with a mux in the HVS that still
> have only 3 FIFOs. Both of those differences are breaking a bunch of
> expectations in the driver, so we first need a good bunch of cleanup and
> reworks to introduce support for the new controllers.
>
> Similarly, the HDMI controller has all its registers shuffled and split in
> multiple controllers now, so we need a bunch of changes to support this as
> well.
>
> Only the HDMI support is enabled for now (even though the DPI and DSI
> outputs have been tested too).
>
> Let me know if you have any comments
> Maxime
>
> Cc: [email protected]
> Cc: [email protected]
> Cc: Kamal Dasu <[email protected]>
> Cc: [email protected]
> Cc: Michael Turquette <[email protected]>
> Cc: Philipp Zabel <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Stephen Boyd <[email protected]>
>
> Changes from v3:
> - Rebased on top of next-20200708
> - Added a name to the HDMI audio codec component
> - Only disable the BCM2711 HDMI pixelvalves at boot
> - Fixed an error in the HVS binding
> - Fix a framebuffer size condition that was inverted
> - Changed the channel allocation algorithm using Eric's suggestion
> - Always write the muxing values instead of updating if needed
> - Improved a bit the hvs_available_channels comment in the structure
> - Change atomic_complete_commit code to use for_each_new_crtc_in_state
> - Change the muxing code to take into account disparities between the
> BCM2711 and previous SoCs.
> - Only change the clock rate on BCM2711 during a modeset
> - Fix a crash at atomic_disable
> - Use clk_set_min_rate for the core clock too
> - Add a few defines, and simplify the FIFO level stuff
> - Reordered the patches according to Eric's reviews
> - Fixed a regression with VID_CTL setting on RPI3
>
> Changes from v2:
> - Rebased on top of next-20200526
> - Split the firmware clock series away
> - Removed the stuck pixel (with all the subsequent pixels being shifted
> by one
> - Fixed the writeback issue too.
> - Fix the dual output
> - Fixed the return value of phy_get_cp_current
> - Enhanced the comment on the reset delay
> - Increase the max width and height
> - Made a proper Kconfig option for the DVP clock driver
> - Fixed the alsa card name collision
>
> Changes from v1:
> - Rebased on top of 5.7-rc1
> - Run checkpatch
> - Added audio support
> - Fixed some HDMI timeouts
> - Swiched to clk_hw_register_gate_parent_data
> - Reorder Kconfig symbols in drivers/i2c/busses
> - Make the firmware clocks a child of the firmware node
> - Switch DVP clock driver to clk_hw interface
> - constify raspberrypi_clk_data in raspberrypi_clock_property
> - Don't mark firmware clocks as IGNORE_UNUSED
> - Change from reset_ms to reset_us in reset-simple, and add a bit more
> comments
> - Remove generic clk patch to test if a NULL pointer is returned
> - Removed misleading message in the is_prepared renaming patch commit
> message
> - Constify HDMI controller variants
> - Fix a bug in the allocation size of the clk data array
> - Added a mention in the DT binding conversion patches about the breakage
> - Merged a few fixes from kbuild
> - Fixed a few bisection and CEC build issues
> - Collected Acked-by and Reviewed-by
> - Change Dave email address to raspberrypi.com
>
> Dave Stevenson (7):
> drm/vc4: Add support for the BCM2711 HVS5
> drm/vc4: plane: Change LBM alignment constraint on LBM
> drm/vc4: plane: Optimize the LBM allocation size
> drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers
> drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming
> drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default.
> drm/vc4: hdmi: Add audio-related callbacks
>
> Maxime Ripard (71):
> dt-bindings: display: Add support for the BCM2711 HVS
> drm/vc4: hvs: Boost the core clock during modeset
> drm/vc4: plane: Create more planes
> drm/vc4: crtc: Deal with different number of pixel per clock
> drm/vc4: crtc: Use a shared interrupt
> drm/vc4: crtc: Move the cob allocation outside of bind
> drm/vc4: crtc: Rename HVS channel to output
> drm/vc4: crtc: Use local chan variable
> drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable
> drm/vc4: kms: Convert to for_each_new_crtc_state
> drm/vc4: crtc: Assign output to channel automatically
> drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
> drm/vc4: crtc: Add function to compute FIFO level bits
> drm/vc4: crtc: Rename HDMI encoder type to HDMI0
> drm/vc4: crtc: Add HDMI1 encoder type
> drm/vc4: crtc: Disable color management for HVS5
> drm/vc4: crtc: Turn pixelvalve reset into a function
> drm/vc4: crtc: Move PV dump to config_pv
> drm/vc4: crtc: Move HVS init and close to a function
> drm/vc4: crtc: Move the HVS gamma LUT setup to our init function
> drm/vc4: hvs: Make sure our channel is reset
> drm/vc4: crtc: Remove mode_set_nofb
> drm/vc4: crtc: Remove redundant pixelvalve reset
> drm/vc4: crtc: Move HVS channel init before the PV initialisation
> drm/vc4: encoder: Add finer-grained encoder callbacks
> drm/vc4: crtc: Add a delay after disabling the PixelValve output
> drm/vc4: crtc: Clear the PixelValve FIFO on disable
> drm/vc4: crtc: Clear the PixelValve FIFO during configuration
> drm/vc4: hvs: Make the stop_channel function public
> drm/vc4: hvs: Introduce a function to get the assigned FIFO
> drm/vc4: crtc: Move the CRTC disable out
> drm/vc4: drv: Disable the CRTC at boot time
> dt-bindings: display: vc4: pv: Add BCM2711 pixel valves
> drm/vc4: crtc: Add BCM2711 pixelvalves
> drm/vc4: hdmi: Use debugfs private field
> drm/vc4: hdmi: Move structure to header
> drm/vc4: hdmi: rework connectors and encoders
> drm/vc4: hdmi: Remove DDC argument to connector_init
> drm/vc4: hdmi: Rename hdmi to vc4_hdmi
> drm/vc4: hdmi: Move accessors to vc4_hdmi
> drm/vc4: hdmi: Use local vc4_hdmi directly
> drm/vc4: hdmi: Add container_of macros for encoders and connectors
> drm/vc4: hdmi: Pass vc4_hdmi to CEC code
> drm/vc4: hdmi: Retrieve the vc4_hdmi at unbind using our device
> drm/vc4: hdmi: Remove vc4_dev hdmi pointer
> drm/vc4: hdmi: Remove vc4_hdmi_connector
> drm/vc4: hdmi: Introduce resource init and variant
> drm/vc4: hdmi: Implement a register layout abstraction
> drm/vc4: hdmi: Add reset callback
> drm/vc4: hdmi: Add PHY init and disable function
> drm/vc4: hdmi: Add PHY RNG enable / disable function
> drm/vc4: hdmi: Add a CSC setup callback
> drm/vc4: hdmi: Store the encoder type in the variant structure
> drm/vc4: hdmi: Deal with multiple debugfs files
> drm/vc4: hdmi: Move CEC init to its own function
> drm/vc4: hdmi: Add CEC support flag
> drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define
> drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid
> drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate
> drm/vc4: hdmi: Use clk_set_min_rate instead
> drm/vc4: hdmi: Deal with multiple ALSA cards
> drm/vc4: hdmi: Remove register dumps in enable
> drm/vc4: hdmi: Always recenter the HDMI FIFO
> drm/vc4: hdmi: Implement finer-grained hooks
> drm/vc4: hdmi: Do the VID_CTL configuration at once
> drm/vc4: hdmi: Switch to blank pixels when disabled
> drm/vc4: hdmi: Support the BCM2711 HDMI controllers
> dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings
> dt-bindings: display: vc4: Document BCM2711 VC5
> drm/vc4: drv: Support BCM2711
> ARM: dts: bcm2711: Enable the display pipeline
>
> Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml | 109 +++++-
> Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 18 +-
> Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 5 +-
> Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 +-
> arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 46 ++-
> arch/arm/boot/dts/bcm2711.dtsi | 115 ++++-
> drivers/gpu/drm/vc4/Makefile | 1 +-
> drivers/gpu/drm/vc4/vc4_crtc.c | 338 +++++++++++----
> drivers/gpu/drm/vc4/vc4_drv.c | 5 +-
> drivers/gpu/drm/vc4/vc4_drv.h | 43 +-
> drivers/gpu/drm/vc4/vc4_hdmi.c | 1625 +++++++++++++++++++++++++++++++++++++++++++-----------------------------
> drivers/gpu/drm/vc4/vc4_hdmi.h | 183 ++++++++-
> drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 520 +++++++++++++++++++++++-
> drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 442 ++++++++++++++++++++-
> drivers/gpu/drm/vc4/vc4_hvs.c | 260 +++++++-----
> drivers/gpu/drm/vc4/vc4_kms.c | 225 +++++++++-
> drivers/gpu/drm/vc4/vc4_plane.c | 222 +++++++---
> drivers/gpu/drm/vc4/vc4_regs.h | 177 +++-----
> drivers/gpu/drm/vc4/vc4_txp.c | 4 +-
> 19 files changed, 3331 insertions(+), 1008 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
> create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h
> create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c
> create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h
>
> base-commit: 5bdd2824d705fb8d339d6f96e464b907c9a1553d
>
I tested it for stress test with reboot command repetitively
for verifying this patchset. It is well working.
Tested-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Hoegeun
On Fri, Aug 21, 2020 at 04:18:34PM +0900, Hoegeun Kwon wrote:
> Hi Maxime,
>
> Thank you for your version 4 patch.
> I tested all 78 patches based on the next-20200708.
>
>
> Dual HDMI opearation does not work normally.
> flip_done timed out occurs and doesn't work.
> Could you check please it.
>
> [? 105.694541] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
> [CRTC:64:crtc-3] flip_done timed out
> [? 115.934994] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
> [CONNECTOR:32:HDMI-A-1] flip_done timed out
> [? 126.174545] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
> [PLANE:60:plane-3] flip_done timed out
Thanks for testing and reporting this. I've been looking into it, and it
seems that it's not just the dual output that's broken, but HDMI1
entirely (so even a single display connected to HDMI1 doesn't work).
Is it happening for you as well?
Maxime
On Wed, Sep 02, 2020 at 03:32:20PM +0200, Maxime Ripard wrote:
> Hi Hoegeun
>
> On Fri, Aug 21, 2020 at 04:18:34PM +0900, Hoegeun Kwon wrote:
> > Hi Maxime,
> >
> > Thank you for your version 4 patch.
> > I tested all 78 patches based on the next-20200708.
> >
> >
> > Dual HDMI opearation does not work normally.
> > flip_done timed out occurs and doesn't work.
> > Could you check please it.
> >
> > [? 105.694541] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
> > [CRTC:64:crtc-3] flip_done timed out
> > [? 115.934994] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
> > [CONNECTOR:32:HDMI-A-1] flip_done timed out
> > [? 126.174545] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR*
> > [PLANE:60:plane-3] flip_done timed out
>
> Thanks for testing and reporting this. I've been looking into it, and it
> seems that it's not just the dual output that's broken, but HDMI1
> entirely (so even a single display connected to HDMI1 doesn't work).
>
> Is it happening for you as well?
Nevermind, I had the DSI panel connected and it was interfering
Maxime