Hi John,
[ + mailing list ]
I'd like to confirm the latest upstream status for SMMUv3 PMU event
aliasing.
I see the patch set v6 of "perf pmu-events: Support event aliasing for
system PMUs" [1] has been landed on the mainline kernel, and as an
example, imx8mm DDR PMU has been supported as system PMU [2].
On the other hand, I can see patch set 5 contains the SMMUv3 PMU event
aliasing with patch "perf vendor events arm64: Add Architected events
smmuv3-pmcg.json" [3], but this patch was left out in patch set 6 and
it's never landed on the mainline kernel.
Could you share current status (or plan) for upstreaming SMMUv3 PMU
event alias? Or if there have any block issue to prevent merging the
changes in the mainline kernel?
Thanks for your help!
Leo
[1] https://lore.kernel.org/lkml/[email protected]/
[2] pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
[3] https://lore.kernel.org/lkml/[email protected]/
On 08/11/2021 12:19, Leo Yan wrote:
> Hi John,
>
> [ + mailing list ]
Hi Leo,
>
> I'd like to confirm the latest upstream status for SMMUv3 PMU event
> aliasing.
>
> I see the patch set v6 of "perf pmu-events: Support event aliasing for
> system PMUs" [1] has been landed on the mainline kernel, and as an
> example, imx8mm DDR PMU has been supported as system PMU [2].
>
> On the other hand, I can see patch set 5 contains the SMMUv3 PMU event
> aliasing with patch "perf vendor events arm64: Add Architected events
> smmuv3-pmcg.json" [3], but this patch was left out in patch set 6 and
> it's never landed on the mainline kernel.
>
> Could you share current status (or plan) for upstreaming SMMUv3 PMU
> event alias? Or if there have any block issue to prevent merging the
> changes in the mainline kernel?
This feature should be supported in the SMMUv3 PMU kernel driver and
perf tool.
However it relies on the SMMU PMU identifier sysfs file to work. This
relies on SMMU_PMCG_IIDR being set, which is introduced latest spec,
which not much HW will support yet - see commit 2c255223362e. In theory
we don't need that for the fixed, non-IMPDEF events, but I did not
complicate perf tool with that mixed support.
That's the reason for which I paused smmuv3-pmcg.json upstream in [3]. I
will revive that for new gen HW when concrete IMPDEF events known and
shared.
Thanks,
John
>
> Thanks for your help!
>
> Leo
>
> [1] https://lore.kernel.org/lkml/[email protected]/
> [2] pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
> [3] https://lore.kernel.org/lkml/[email protected]/
> .
>
Hi John,
On Mon, Nov 08, 2021 at 12:41:33PM +0000, John Garry wrote:
[...]
> > Could you share current status (or plan) for upstreaming SMMUv3 PMU
> > event alias? Or if there have any block issue to prevent merging the
> > changes in the mainline kernel?
>
> This feature should be supported in the SMMUv3 PMU kernel driver and perf
> tool.
>
> However it relies on the SMMU PMU identifier sysfs file to work. This relies
> on SMMU_PMCG_IIDR being set, which is introduced latest spec, which not much
> HW will support yet - see commit 2c255223362e. In theory we don't need that
> for the fixed, non-IMPDEF events, but I did not complicate perf tool with
> that mixed support.
>
> That's the reason for which I paused smmuv3-pmcg.json upstream in [3]. I
> will revive that for new gen HW when concrete IMPDEF events known and
> shared.
Thanks for info. When send out the new patch, you are welcome to Cc
to me, I am glad to give a test on D06 board (its IIDR is zero, so
I need to tweak a bit in driver for IIDR :)).
Thanks,
Leo
On 2021-11-08 12:41, John Garry wrote:
> On 08/11/2021 12:19, Leo Yan wrote:
>> Hi John,
>>
>> [ + mailing list ]
>
> Hi Leo,
>
>>
>> I'd like to confirm the latest upstream status for SMMUv3 PMU event
>> aliasing.
>>
>> I see the patch set v6 of "perf pmu-events: Support event aliasing for
>> system PMUs" [1] has been landed on the mainline kernel, and as an
>> example, imx8mm DDR PMU has been supported as system PMU [2].
>>
>> On the other hand, I can see patch set 5 contains the SMMUv3 PMU event
>> aliasing with patch "perf vendor events arm64: Add Architected events
>> smmuv3-pmcg.json" [3], but this patch was left out in patch set 6 and
>> it's never landed on the mainline kernel.
>>
>> Could you share current status (or plan) for upstreaming SMMUv3 PMU
>> event alias? Or if there have any block issue to prevent merging the
>> changes in the mainline kernel?
>
> This feature should be supported in the SMMUv3 PMU kernel driver and
> perf tool.
>
> However it relies on the SMMU PMU identifier sysfs file to work. This
> relies on SMMU_PMCG_IIDR being set, which is introduced latest spec,
> which not much HW will support yet - see commit 2c255223362e. In theory
> we don't need that for the fixed, non-IMPDEF events, but I did not
> complicate perf tool with that mixed support.
>
> That's the reason for which I paused smmuv3-pmcg.json upstream in [3]. I
> will revive that for new gen HW when concrete IMPDEF events known and
> shared.
FWIW, imp-def-events are readily available for the existing Arm
implementations[1][2], and annoyingly we could trivially synthesise an
IIDR value from their imp-def PIDR registers if only we knew that that
was valid to do in the first place. I feel tempted now to resurrect
Jean-Philippe's DT binding and have a quick hack at that, then maybe a
much longer think about how to attempt it for IORT...
Cheers,
Robin.
[1]
https://developer.arm.com/documentation/100310/0202/Functional-description/Operation/Performance-Monitoring-Unit
[2]
https://developer.arm.com/documentation/101542/0001/Functional-description/Operation/Performance-Monitoring-Unit
>
> Thanks,
> John
>
>>
>> Thanks for your help!
>>
>> Leo
>>
>> [1]
>> https://lore.kernel.org/lkml/[email protected]/
>>
>> [2] pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
>> [3]
>> https://lore.kernel.org/lkml/[email protected]/
>>
>> .
>>
>
>
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