LinuxLists.cc - [PATCH] clk: samsung: remove s3c24xx specific pll bits

2023-01-05 14:21:34

Subject: [PATCH] clk: samsung: remove s3c24xx specific pll bits

From: Arnd Bergmann <[email protected]>

With the s3c24xx clk driver gone, the portions of the pll driver
for it can also be removed.

Suggested-by: Chanwoo Choi <[email protected]>
Cc: Chanwoo Choi <[email protected]>
Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
---
I'm trying to get the boardfile removal patches into shape for
6.3, and came across the comment from Chanwoo Choi that I had
not addressed yet. I've added this patch to my s3c24xx series now,
to be merged through the soc tree unless there are objections.

drivers/clk/samsung/clk-pll.c | 181 ----------------------------------
drivers/clk/samsung/clk-pll.h | 21 ----
2 files changed, 202 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0ff28938943f..df7812371d70 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -940,169 +940,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = {
.recalc_rate = samsung_pll6553_recalc_rate,
};

-/*
- * PLL Clock Type of S3C24XX before S3C2443
- */
-
-#define PLLS3C2410_MDIV_MASK (0xff)
-#define PLLS3C2410_PDIV_MASK (0x1f)
-#define PLLS3C2410_SDIV_MASK (0x3)
-#define PLLS3C2410_MDIV_SHIFT (12)
-#define PLLS3C2410_PDIV_SHIFT (4)
-#define PLLS3C2410_SDIV_SHIFT (0)
-
-#define PLLS3C2410_ENABLE_REG_OFFSET 0x10
-
-static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct samsung_clk_pll *pll = to_clk_pll(hw);
- u32 pll_con, mdiv, pdiv, sdiv;
- u64 fvco = parent_rate;
-
- pll_con = readl_relaxed(pll->con_reg);
- mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
- pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
- sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
-
- fvco *= (mdiv + 8);
- do_div(fvco, (pdiv + 2) << sdiv);
-
- return (unsigned int)fvco;
-}
-
-static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct samsung_clk_pll *pll = to_clk_pll(hw);
- u32 pll_con, mdiv, pdiv, sdiv;
- u64 fvco = parent_rate;
-
- pll_con = readl_relaxed(pll->con_reg);
- mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
- pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
- sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
-
- fvco *= (2 * (mdiv + 8));
- do_div(fvco, (pdiv + 2) << sdiv);
-
- return (unsigned int)fvco;
-}
-
-static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long prate)
-{
- struct samsung_clk_pll *pll = to_clk_pll(hw);
- const struct samsung_pll_rate_table *rate;
- u32 tmp;
-
- /* Get required rate settings from table */
- rate = samsung_get_pll_settings(pll, drate);
- if (!rate) {
- pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
- drate, clk_hw_get_name(hw));
- return -EINVAL;
- }
-
- tmp = readl_relaxed(pll->con_reg);
-
- /* Change PLL PMS values */
- tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
- (PLLS3C2410_PDIV_MASK << PLLS3C2410_PDIV_SHIFT) |
- (PLLS3C2410_SDIV_MASK << PLLS3C2410_SDIV_SHIFT));
- tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
- (rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
- (rate->sdiv << PLLS3C2410_SDIV_SHIFT);
- writel_relaxed(tmp, pll->con_reg);
-
- /* Time to settle according to the manual */
- udelay(300);
-
- return 0;
-}
-
-static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
-{
- struct samsung_clk_pll *pll = to_clk_pll(hw);
- u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
- u32 pll_en_orig = pll_en;
-
- if (enable)
- pll_en &= ~BIT(bit);
- else
- pll_en |= BIT(bit);
-
- writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
-
- /* if we started the UPLL, then allow to settle */
- if (enable && (pll_en_orig & BIT(bit)))
- udelay(300);
-
- return 0;
-}
-
-static int samsung_s3c2410_mpll_enable(struct clk_hw *hw)
-{
- return samsung_s3c2410_pll_enable(hw, 5, true);
-}
-
-static void samsung_s3c2410_mpll_disable(struct clk_hw *hw)
-{
- samsung_s3c2410_pll_enable(hw, 5, false);
-}
-
-static int samsung_s3c2410_upll_enable(struct clk_hw *hw)
-{
- return samsung_s3c2410_pll_enable(hw, 7, true);
-}
-
-static void samsung_s3c2410_upll_disable(struct clk_hw *hw)
-{
- samsung_s3c2410_pll_enable(hw, 7, false);
-}
-
-static const struct clk_ops samsung_s3c2410_mpll_clk_min_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
-};
-
-static const struct clk_ops samsung_s3c2410_upll_clk_min_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_upll_enable,
- .disable = samsung_s3c2410_upll_disable,
-};
-
-static const struct clk_ops samsung_s3c2440_mpll_clk_min_ops = {
- .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
-};
-
-static const struct clk_ops samsung_s3c2410_mpll_clk_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
- .round_rate = samsung_pll_round_rate,
- .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-static const struct clk_ops samsung_s3c2410_upll_clk_ops = {
- .recalc_rate = samsung_s3c2410_pll_recalc_rate,
- .enable = samsung_s3c2410_upll_enable,
- .disable = samsung_s3c2410_upll_disable,
- .round_rate = samsung_pll_round_rate,
- .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-static const struct clk_ops samsung_s3c2440_mpll_clk_ops = {
- .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
- .enable = samsung_s3c2410_mpll_enable,
- .disable = samsung_s3c2410_mpll_disable,
- .round_rate = samsung_pll_round_rate,
- .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
/*
* PLL2550x Clock Type
*/
@@ -1530,24 +1367,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll46xx_clk_ops;
break;
- case pll_s3c2410_mpll:
- if (!pll->rate_table)
- init.ops = &samsung_s3c2410_mpll_clk_min_ops;
- else
- init.ops = &samsung_s3c2410_mpll_clk_ops;
- break;
- case pll_s3c2410_upll:
- if (!pll->rate_table)
- init.ops = &samsung_s3c2410_upll_clk_min_ops;
- else
- init.ops = &samsung_s3c2410_upll_clk_ops;
- break;
- case pll_s3c2440_mpll:
- if (!pll->rate_table)
- init.ops = &samsung_s3c2440_mpll_clk_min_ops;
- else
- init.ops = &samsung_s3c2440_mpll_clk_ops;
- break;
case pll_2550x:
init.ops = &samsung_pll2550x_clk_ops;
break;
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a9892c2d1f57..5d5a58d40e7e 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,9 +25,6 @@ enum samsung_pll_type {
pll_6552,
pll_6552_s3c2416,
pll_6553,
- pll_s3c2410_mpll,
- pll_s3c2410_upll,
- pll_s3c2440_mpll,
pll_2550x,
pll_2550xx,
pll_2650x,
@@ -56,24 +53,6 @@ enum samsung_pll_type {
.sdiv = (_s), \
}

-#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
- { \
- .rate = PLL_VALID_RATE(_fin, _rate, \
- _m + 8, _p + 2, _s, 0, 16), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
- { \
- .rate = PLL_VALID_RATE(_fin, _rate, \
- 2 * (_m + 8), _p + 2, _s, 0, 16), \
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
{ \
.rate = PLL_VALID_RATE(_fin, _rate, \
--
2.39.0

2023-01-05 20:14:25

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH] clk: samsung: remove s3c24xx specific pll bits

Hi Arnd,

I love your patch! Yet something to improve:

[auto build test ERROR on krzk/for-next]
[also build test ERROR on linus/master v6.2-rc2 next-20230105]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Arnd-Bergmann/clk-samsung-remove-s3c24xx-specific-pll-bits/20230105-221537
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20230105141231.2006353-1-arnd%40kernel.org
patch subject: [PATCH] clk: samsung: remove s3c24xx specific pll bits
config: s390-allyesconfig
compiler: s390-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f3493e33c0b212b32ebc32a7e4fe6e7cf1c325d2
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Arnd-Bergmann/clk-samsung-remove-s3c24xx-specific-pll-bits/20230105-221537
git checkout f3493e33c0b212b32ebc32a7e4fe6e7cf1c325d2
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=s390 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=s390 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>

All errors (new ones prefixed by >>):

>> drivers/clk/samsung/clk-s3c2410.c:123:9: error: implicit declaration of function 'PLL_S3C2410_MPLL_RATE' [-Werror=implicit-function-declaration]
123 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
>> drivers/clk/samsung/clk-s3c2410.c:123:9: error: initializer element is not constant
drivers/clk/samsung/clk-s3c2410.c:123:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].rate')
drivers/clk/samsung/clk-s3c2410.c:124:9: error: initializer element is not constant
124 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:124:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].pdiv')
drivers/clk/samsung/clk-s3c2410.c:125:9: error: initializer element is not constant
125 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:125:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].mdiv')
drivers/clk/samsung/clk-s3c2410.c:126:9: error: initializer element is not constant
126 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:126:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].sdiv')
drivers/clk/samsung/clk-s3c2410.c:127:9: error: initializer element is not constant
127 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:127:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].kdiv')
drivers/clk/samsung/clk-s3c2410.c:129:9: error: initializer element is not constant
129 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:129:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].afc')
drivers/clk/samsung/clk-s3c2410.c:130:9: error: initializer element is not constant
130 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:130:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].mfr')
drivers/clk/samsung/clk-s3c2410.c:131:9: error: initializer element is not constant
131 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:131:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].mrr')
drivers/clk/samsung/clk-s3c2410.c:132:9: error: initializer element is not constant
132 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:132:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[0].vsel')
drivers/clk/samsung/clk-s3c2410.c:133:9: error: initializer element is not constant
133 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:133:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].rate')
drivers/clk/samsung/clk-s3c2410.c:134:9: error: initializer element is not constant
134 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:134:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].pdiv')
drivers/clk/samsung/clk-s3c2410.c:135:9: error: initializer element is not constant
135 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:135:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].mdiv')
drivers/clk/samsung/clk-s3c2410.c:136:9: error: initializer element is not constant
136 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:136:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].sdiv')
drivers/clk/samsung/clk-s3c2410.c:137:9: error: initializer element is not constant
137 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:137:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].kdiv')
drivers/clk/samsung/clk-s3c2410.c:138:9: error: initializer element is not constant
138 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:138:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].afc')
drivers/clk/samsung/clk-s3c2410.c:139:9: error: initializer element is not constant
139 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:139:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].mfr')
drivers/clk/samsung/clk-s3c2410.c:140:9: error: initializer element is not constant
140 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:140:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].mrr')
drivers/clk/samsung/clk-s3c2410.c:141:9: error: initializer element is not constant
141 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:141:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[1].vsel')
drivers/clk/samsung/clk-s3c2410.c:142:9: error: initializer element is not constant
142 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:142:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].rate')
drivers/clk/samsung/clk-s3c2410.c:143:9: error: initializer element is not constant
143 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:143:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].pdiv')
drivers/clk/samsung/clk-s3c2410.c:144:9: error: initializer element is not constant
144 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:144:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].mdiv')
drivers/clk/samsung/clk-s3c2410.c:145:9: error: initializer element is not constant
145 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:145:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].sdiv')
drivers/clk/samsung/clk-s3c2410.c:146:9: error: initializer element is not constant
146 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:146:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].kdiv')
drivers/clk/samsung/clk-s3c2410.c:147:9: error: initializer element is not constant
147 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:147:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].afc')
drivers/clk/samsung/clk-s3c2410.c:148:9: error: initializer element is not constant
148 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:148:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].mfr')
drivers/clk/samsung/clk-s3c2410.c:149:9: error: initializer element is not constant
149 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:149:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].mrr')
drivers/clk/samsung/clk-s3c2410.c:150:9: error: initializer element is not constant
150 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:150:9: note: (near initialization for 'pll_s3c2410_12mhz_tbl[2].vsel')
In file included from drivers/clk/samsung/clk-s3c2410.c:15:
>> drivers/clk/samsung/clk-s3c2410.c:155:22: error: 'pll_s3c2410_mpll' undeclared here (not in a function); did you mean 's3c2410_plls'?
155 | [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:261:35: note: in definition of macro '__PLL'
261 | .type = _typ, \
| ^~~~
drivers/clk/samsung/clk-s3c2410.c:155:18: note: in expansion of macro 'PLL'
155 | [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
| ^~~
>> drivers/clk/samsung/clk-s3c2410.c:157:22: error: 'pll_s3c2410_upll' undeclared here (not in a function); did you mean 's3c2410_plls'?
157 | [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:261:35: note: in definition of macro '__PLL'
261 | .type = _typ, \
| ^~~~
drivers/clk/samsung/clk-s3c2410.c:157:18: note: in expansion of macro 'PLL'
157 | [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
| ^~~
>> drivers/clk/samsung/clk-s3c2410.c:190:9: error: implicit declaration of function 'PLL_S3C2440_MPLL_RATE' [-Werror=implicit-function-declaration]
190 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:190:9: error: initializer element is not constant
drivers/clk/samsung/clk-s3c2410.c:190:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].rate')
drivers/clk/samsung/clk-s3c2410.c:191:9: error: initializer element is not constant
191 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:191:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].pdiv')
drivers/clk/samsung/clk-s3c2410.c:192:9: error: initializer element is not constant
192 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:192:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].mdiv')
drivers/clk/samsung/clk-s3c2410.c:193:9: error: initializer element is not constant
193 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:193:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].sdiv')
drivers/clk/samsung/clk-s3c2410.c:194:9: error: initializer element is not constant
194 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:194:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].kdiv')
drivers/clk/samsung/clk-s3c2410.c:195:9: error: initializer element is not constant
195 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:195:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].afc')
drivers/clk/samsung/clk-s3c2410.c:196:9: error: initializer element is not constant
196 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:196:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].mfr')
drivers/clk/samsung/clk-s3c2410.c:197:9: error: initializer element is not constant
197 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:197:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].mrr')
drivers/clk/samsung/clk-s3c2410.c:198:9: error: initializer element is not constant
198 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:198:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[0].vsel')
drivers/clk/samsung/clk-s3c2410.c:199:9: error: initializer element is not constant
199 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:199:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].rate')
drivers/clk/samsung/clk-s3c2410.c:200:9: error: initializer element is not constant
200 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:200:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].pdiv')
drivers/clk/samsung/clk-s3c2410.c:201:9: error: initializer element is not constant
201 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:201:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].mdiv')
drivers/clk/samsung/clk-s3c2410.c:202:9: error: initializer element is not constant
202 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:202:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].sdiv')
drivers/clk/samsung/clk-s3c2410.c:203:9: error: initializer element is not constant
203 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:203:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].kdiv')
drivers/clk/samsung/clk-s3c2410.c:204:9: error: initializer element is not constant
204 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:204:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].afc')
drivers/clk/samsung/clk-s3c2410.c:205:9: error: initializer element is not constant
205 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:205:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].mfr')
drivers/clk/samsung/clk-s3c2410.c:206:9: error: initializer element is not constant
206 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:206:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].mrr')
drivers/clk/samsung/clk-s3c2410.c:207:9: error: initializer element is not constant
207 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:207:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[1].vsel')
drivers/clk/samsung/clk-s3c2410.c:208:9: error: initializer element is not constant
208 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:208:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].rate')
drivers/clk/samsung/clk-s3c2410.c:209:9: error: initializer element is not constant
209 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:209:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].pdiv')
drivers/clk/samsung/clk-s3c2410.c:210:9: error: initializer element is not constant
210 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:210:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].mdiv')
drivers/clk/samsung/clk-s3c2410.c:211:9: error: initializer element is not constant
211 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:211:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].sdiv')
drivers/clk/samsung/clk-s3c2410.c:212:9: error: initializer element is not constant
212 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:212:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].kdiv')
drivers/clk/samsung/clk-s3c2410.c:213:9: error: initializer element is not constant
213 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:213:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].afc')
drivers/clk/samsung/clk-s3c2410.c:214:9: error: initializer element is not constant
214 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:214:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].mfr')
drivers/clk/samsung/clk-s3c2410.c:215:9: error: initializer element is not constant
215 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:215:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].mrr')
drivers/clk/samsung/clk-s3c2410.c:216:9: error: initializer element is not constant
216 | PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
| ^~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2410.c:216:9: note: (near initialization for 'pll_s3c244x_12mhz_tbl[2].vsel')
>> drivers/clk/samsung/clk-s3c2410.c:221:22: error: 'pll_s3c2440_mpll' undeclared here (not in a function)
221 | [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:261:35: note: in definition of macro '__PLL'
261 | .type = _typ, \
| ^~~~
drivers/clk/samsung/clk-s3c2410.c:221:18: note: in expansion of macro 'PLL'
221 | [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
| ^~~
cc1: some warnings being treated as errors
--
In file included from drivers/clk/samsung/clk-s3c2412.c:17:
>> drivers/clk/samsung/clk-s3c2412.c:101:13: error: 'pll_s3c2440_mpll' undeclared here (not in a function)
101 | PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:261:35: note: in definition of macro '__PLL'
261 | .type = _typ, \
| ^~~~
drivers/clk/samsung/clk-s3c2412.c:101:9: note: in expansion of macro 'PLL'
101 | PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
| ^~~
>> drivers/clk/samsung/clk-s3c2412.c:102:13: error: 'pll_s3c2410_upll' undeclared here (not in a function)
102 | PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:261:35: note: in definition of macro '__PLL'
261 | .type = _typ, \
| ^~~~
drivers/clk/samsung/clk-s3c2412.c:102:9: note: in expansion of macro 'PLL'
102 | PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
| ^~~

vim +/PLL_S3C2410_MPLL_RATE +123 drivers/clk/samsung/clk-s3c2410.c

3f7c01ade226e7 Heiko Stuebner 2014-05-09 119
3f7c01ade226e7 Heiko Stuebner 2014-05-09 120 static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 121 /* sorted in descending order */
3f7c01ade226e7 Heiko Stuebner 2014-05-09 122 /* 2410A extras */
1d5013f1b64dbd Andrzej Hajda 2018-02-20 @123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 128 /* 2410 common */
1d5013f1b64dbd Andrzej Hajda 2018-02-20 129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 134 PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 135 PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 136 PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 137 PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 138 PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 139 PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 140 PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 141 PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 142 PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 143 PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 144 PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 145 PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 146 PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 147 PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 148 PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 149 PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 150 PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 151 { /* sentinel */ },
3f7c01ade226e7 Heiko Stuebner 2014-05-09 152 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 153
3f7c01ade226e7 Heiko Stuebner 2014-05-09 154 static struct samsung_pll_clock s3c2410_plls[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 @155 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
3f7c01ade226e7 Heiko Stuebner 2014-05-09 156 LOCKTIME, MPLLCON, NULL),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 @157 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
3f7c01ade226e7 Heiko Stuebner 2014-05-09 158 LOCKTIME, UPLLCON, NULL),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 159 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 160
1871f0fcba5deb Stephen Boyd 2018-03-16 161 static struct samsung_div_clock s3c2410_dividers[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 162 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 163 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 164
1871f0fcba5deb Stephen Boyd 2018-03-16 165 static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 166 /*
3f7c01ade226e7 Heiko Stuebner 2014-05-09 167 * armclk is directly supplied by the fclk, without
3f7c01ade226e7 Heiko Stuebner 2014-05-09 168 * switching possibility like on the s3c244x below.
3f7c01ade226e7 Heiko Stuebner 2014-05-09 169 */
3f7c01ade226e7 Heiko Stuebner 2014-05-09 170 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 171
3f7c01ade226e7 Heiko Stuebner 2014-05-09 172 /* uclk is fed from the unmodified upll */
3f7c01ade226e7 Heiko Stuebner 2014-05-09 173 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 174 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 175
1871f0fcba5deb Stephen Boyd 2018-03-16 176 static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 177 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 178 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 179 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 180 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 181 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 182 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 183 ALIAS(UCLK, NULL, "clk_uart_baud1"),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 184 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 185
3f7c01ade226e7 Heiko Stuebner 2014-05-09 186 /* S3C244x specific clocks */
3f7c01ade226e7 Heiko Stuebner 2014-05-09 187
3f7c01ade226e7 Heiko Stuebner 2014-05-09 188 static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 189 /* sorted in descending order */
1d5013f1b64dbd Andrzej Hajda 2018-02-20 @190 PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 191 PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 192 PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 193 PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 194 PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 195 PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 196 PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 197 PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 198 PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 199 PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 200 PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 201 PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 202 PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 203 PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 204 PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 205 PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 206 PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 207 PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 208 PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 209 PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 210 PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 211 PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 212 PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 213 PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 214 PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 215 PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
1d5013f1b64dbd Andrzej Hajda 2018-02-20 216 PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 217 { /* sentinel */ },
3f7c01ade226e7 Heiko Stuebner 2014-05-09 218 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 219
3f7c01ade226e7 Heiko Stuebner 2014-05-09 220 static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
3f7c01ade226e7 Heiko Stuebner 2014-05-09 @221 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
3f7c01ade226e7 Heiko Stuebner 2014-05-09 222 LOCKTIME, MPLLCON, NULL),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 223 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
3f7c01ade226e7 Heiko Stuebner 2014-05-09 224 LOCKTIME, UPLLCON, NULL),
3f7c01ade226e7 Heiko Stuebner 2014-05-09 225 };
3f7c01ade226e7 Heiko Stuebner 2014-05-09 226

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2023-01-05 22:24:55

by Arnd Bergmann

[permalink] [raw]

Subject: Re: [PATCH] clk: samsung: remove s3c24xx specific pll bits

On Thu, Jan 5, 2023, at 20:49, kernel test robot wrote:
> Hi Arnd,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on krzk/for-next]
> [also build test ERROR on linus/master v6.2-rc2 next-20230105]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
>
>>> drivers/clk/samsung/clk-s3c2410.c:123:9: error: implicit declaration of function 'PLL_S3C2410_MPLL_RATE' [-Werror=implicit-function-declaration]
> 123 | PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
> | ^~~~~~~~~~~~~~~~~~~~~

For clarification, the order in the patch series puts this
patch after the one that removes clk-s3c2410.c, so there should
be no bisection problem.

Arnd

2023-01-06 00:16:03

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH] clk: samsung: remove s3c24xx specific pll bits

Hi Arnd,

I love your patch! Yet
[auto build test ERROR [also build test ERROR [If your patch is applied And when submitting wget mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER_INSTALL_PATH=$HOME/0day
If you fix the issue, | Reported-by: kernel
All errors (new ones
>> drivers/clk/samsung/ PLL(pll_s3c2440_mpll, ^
>> drivers/clk/samsung/ PLL(pll_s3c2410_upll, ^
>> drivers/clk/samsung/ samsung_clk_register_pll(ctx, include/linux/kernel.h:55:32: #define ARRAY_SIZE(arr) 3 errors generated.

vim +/pll_s3c2440_mpll
ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 35615917ef0273 Chanwoo Choi 35615917ef0273 Chanwoo Choi ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 1871f0fcba5deb Stephen Boyd ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 1871f0fcba5deb Stephen Boyd ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 1871f0fcba5deb Stephen Boyd 728f288d2aed7d Stephen Boyd 728f288d2aed7d Stephen Boyd ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma 976face4b46ab3 Rahul Sharma 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma e317c19470f6d6 Heiko St?bner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma 976face4b46ab3 Rahul Sharma 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner 976face4b46ab3 Rahul Sharma ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner 1b3493d755c85b Marek Szyprowski 1b3493d755c85b Marek Szyprowski d5e136a21b2028 Sylwester d5e136a21b2028 Sylwester e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner e317c19470f6d6 Heiko St?bner ca2e90ac1809c4 Heiko Stuebner ca2e90ac1809c4 Heiko Stuebner
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https://git-scm.com/docs/git-format-patch#_base_tree_information]
hub.com/intel-lab-lkp/linux/commits/Arnd-Bergmann/clk-samsung-remove-s3c24xx-specific-pll-bits/20230105-221537">https://github.com/intel-lab-lkp/linux/commits/Arnd-Bergmann/clk-samsung-remove-s3c24xx-specific-pll-bits/20230105-221537
.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
s://lore.kernel.org/r/20230105141231.2006353-1-arnd%40kernel.org">https://lore.kernel.org/r/20230105141231.2006353-1-arnd%40kernel.org
clk: samsung: remove s3c24xx specific pll bits
/> href="https://github.com/llvm/llvm-project">https://github.com/llvm/llvm-project 8d9828ef5aa9688500657d36cd2aefbe12bbd162)
//raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross">https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
cross compiling tool for clang build
binutils-arm-linux-gnueabi
ithub.com/intel-lab-lkp/linux/commit/f3493e33c0b212b32ebc32a7e4fe6e7cf1c325d2">https://github.com/intel-lab-lkp/linux/commit/f3493e33c0b212b32ebc32a7e4fe6e7cf1c325d2
href="https://github.com/intel-lab-lkp/linux">https://github.com/intel-lab-lkp/linux
linux-review Arnd-Bergmann/clk-samsung-remove-s3c24xx-specific-pll-bits/20230105-221537
f3493e33c0b212b32ebc32a7e4fe6e7cf1c325d2
&& cp config build_dir/.config
COMPILER=clang make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/clk/samsung/
kindly add following tag where applicable
test robot <[email protected]>
prefixed by >>):
clk-s3c2412.c:101:6: error: use of undeclared identifier 'pll_s3c2440_mpll'
MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
clk-s3c2412.c:102:6: error: use of undeclared identifier 'pll_s3c2410_upll'
UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
clk-s3c2412.c:226:46: error: invalid application of 'sizeof' to an incomplete type 'struct samsung_pll_clock[]'
s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
^~~~~~~~~~~~~~~~~~~~~~~~
note: expanded from macro 'ARRAY_SIZE'
(sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
^~~~~
+101 drivers/clk/samsung/clk-s3c2412.c
2014-02-25 99
2014-02-25 100 static struct samsung_pll_clock s3c2412_plls[] __initdata = {
2017-11-27 @101 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
2017-11-27 @102 PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
2014-02-25 103 };
2014-02-25 104
2018-03-16 105 static struct samsung_gate_clock s3c2412_gates[] __initdata = {
2014-02-25 106 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
2014-02-25 107 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
2014-02-25 108 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
2014-02-25 109 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
2014-02-25 110 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
2014-02-25 111 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
2014-02-25 112 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
2014-02-25 113 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
2014-02-25 114 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
2014-02-25 115 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
2014-02-25 116 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
2014-02-25 117 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
2014-02-25 118 GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
2014-02-25 119 GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
2014-02-25 120 GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
2014-02-25 121 GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
2014-02-25 122 GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
2014-02-25 123 GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
2014-02-25 124 GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
2014-02-25 125 GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
2014-02-25 126 GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
2014-02-25 127 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
2014-02-25 128 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
2014-02-25 129 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
2014-02-25 130 GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
2014-02-25 131 GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
2014-02-25 132 GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
2014-02-25 133 GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
2014-02-25 134 };
2014-02-25 135
2018-03-16 136 static struct samsung_clock_alias s3c2412_aliases[] __initdata = {
2014-02-25 137 ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
2014-02-25 138 ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
2014-02-25 139 ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
2014-02-25 140 ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
2014-02-25 141 ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
2014-02-25 142 ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
2014-02-25 143 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
2014-02-25 144 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
2014-02-25 145 ALIAS(PCLK_ADC, NULL, "adc"),
2014-02-25 146 ALIAS(PCLK_RTC, NULL, "rtc"),
2014-02-25 147 ALIAS(PCLK_PWM, NULL, "timers"),
2014-02-25 148 ALIAS(HCLK_LCD, NULL, "lcd"),
2014-02-25 149 ALIAS(PCLK_USBD, NULL, "usb-device"),
2014-02-25 150 ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
2014-02-25 151 ALIAS(HCLK_USBH, NULL, "usb-host"),
2014-02-25 152 ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
2014-02-25 153 ALIAS(ARMCLK, NULL, "armclk"),
2014-02-25 154 ALIAS(HCLK, NULL, "hclk"),
2014-02-25 155 ALIAS(MPLL, NULL, "mpll"),
2014-02-25 156 ALIAS(MSYSCLK, NULL, "fclk"),
2014-02-25 157 };
2014-02-25 158
2014-08-19 159 static int s3c2412_restart(struct notifier_block *this,
2014-08-19 160 unsigned long mode, void *cmd)
2014-08-19 161 {
2014-08-19 162 /* errata "Watch-dog/Software Reset Problem" specifies that
2014-08-19 163 * this reset must be done with the SYSCLK sourced from
2014-08-19 164 * EXTCLK instead of FOUT to avoid a glitch in the reset
2014-08-19 165 * mechanism.
2014-08-19 166 *
2014-08-19 167 * See the watchdog section of the S3C2412 manual for more
2014-08-19 168 * information on this fix.
2014-08-19 169 */
2014-08-19 170
2014-08-19 171 __raw_writel(0x00, reg_base + CLKSRC);
2014-08-19 172 __raw_writel(0x533C2412, reg_base + SWRST);
2014-08-19 173 return NOTIFY_DONE;
2014-08-19 174 }
2014-08-19 175
2014-08-19 176 static struct notifier_block s3c2412_restart_handler = {
2014-08-19 177 .notifier_call = s3c2412_restart,
2014-08-19 178 .priority = 129,
2014-08-19 179 };
2014-08-19 180
2014-02-25 181 /*
2014-02-25 182 * fixed rate clocks generated outside the soc
2014-02-25 183 * Only necessary until the devicetree-move is complete
2014-02-25 184 */
2014-02-25 185 #define XTI 1
2018-03-16 186 static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
2016-03-01 187 FRATE(XTI, "xti", NULL, 0, 0),
2016-03-01 188 FRATE(0, "ext", NULL, 0, 0),
2014-02-25 189 };
2014-02-25 190
2014-03-12 191 static void __init s3c2412_common_clk_register_fixed_ext(
2014-03-12 192 struct samsung_clk_provider *ctx,
2014-03-12 193 unsigned long xti_f, unsigned long ext_f)
2014-02-25 194 {
2014-02-25 195 /* xtal alias is necessary for the current cpufreq driver */
2014-02-25 196 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
2014-02-25 197
2014-02-25 198 s3c2412_common_frate_clks[0].fixed_rate = xti_f;
2014-02-25 199 s3c2412_common_frate_clks[1].fixed_rate = ext_f;
2014-03-12 200 samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
2014-02-25 201 ARRAY_SIZE(s3c2412_common_frate_clks));
2014-02-25 202
2014-03-12 203 samsung_clk_register_alias(ctx, &xti_alias, 1);
2014-02-25 204 }
2014-02-25 205
2014-02-25 206 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
2014-02-25 207 unsigned long ext_f, void __iomem *base)
2014-02-25 208 {
2014-03-12 209 struct samsung_clk_provider *ctx;
2014-08-19 210 int ret;
2014-02-25 211 reg_base = base;
2014-02-25 212
2014-02-25 213 if (np) {
2014-02-25 214 reg_base = of_iomap(np, 0);
2014-02-25 215 if (!reg_base)
2014-02-25 216 panic("%s: failed to map registers\n", __func__);
2014-02-25 217 }
2014-02-25 218
2014-03-12 219 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
2014-02-25 220
2014-02-25 221 /* Register external clocks only in non-dt cases */
2014-02-25 222 if (!np)
2014-03-12 223 s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
2014-02-25 224
2014-02-25 225 /* Register PLLs. */
2014-03-12 @226 samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
2014-02-25 227 reg_base);
2014-02-25 228
2014-02-25 229 /* Register common internal clocks. */
2014-03-12 230 samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
2014-03-12 231 samsung_clk_register_div(ctx, s3c2412_dividers,
2014-02-25 232 ARRAY_SIZE(s3c2412_dividers));
2014-03-12 233 samsung_clk_register_gate(ctx, s3c2412_gates,
2014-03-12 234 ARRAY_SIZE(s3c2412_gates));
2014-03-12 235 samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
2014-02-25 236 ARRAY_SIZE(s3c2412_ffactor));
2014-03-12 237 samsung_clk_register_alias(ctx, s3c2412_aliases,
2014-02-25 238 ARRAY_SIZE(s3c2412_aliases));
2014-02-25 239
2018-09-06 240 samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
2018-09-06 241 ARRAY_SIZE(s3c2412_clk_regs));
Nawrocki 2014-06-18 242
Nawrocki 2014-06-18 243 samsung_clk_of_add_provider(np, ctx);
2014-08-19 244
2014-08-19 245 ret = register_restart_handler(&s3c2412_restart_handler);
2014-08-19 246 if (ret)
2014-08-19 247 pr_warn("cannot register restart handler, %d\n", ret);
2014-02-25 248 }
2014-02-25 249
intel/lkp-tests">https://github.com/intel/lkp-tests

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2023-01-10 13:21:00

by Chanwoo Choi

[permalink] [raw]

Subject: Re: [PATCH] clk: samsung: remove s3c24xx specific pll bits

On 23. 1. 5. 23:12, Arnd Bergmann wrote:
> From: Arnd Bergmann <[email protected]>
>
> With the s3c24xx clk driver gone, the portions of the pll driver
> for it can also be removed.
>
> Suggested-by: Chanwoo Choi <[email protected]>
> Cc: Chanwoo Choi <[email protected]>
> Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/
> Cc: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Arnd Bergmann <[email protected]>
> ---
> I'm trying to get the boardfile removal patches into shape for
> 6.3, and came across the comment from Chanwoo Choi that I had
> not addressed yet. I've added this patch to my s3c24xx series now,
> to be merged through the soc tree unless there are objections.
>
> drivers/clk/samsung/clk-pll.c | 181 ----------------------------------
> drivers/clk/samsung/clk-pll.h | 21 ----
> 2 files changed, 202 deletions(-)

(snip)

Acked-by: Chanwoo Choi <[email protected]>

Thanks.

--
Best Regards,
Samsung Electronics
Chanwoo Choi

2023-01-12 21:34:42

by Stephen Boyd

[permalink] [raw]

Subject: Re: [PATCH] clk: samsung: remove s3c24xx specific pll bits

Quoting Arnd Bergmann (2023-01-05 06:12:13)
> From: Arnd Bergmann <[email protected]>
>
> With the s3c24xx clk driver gone, the portions of the pll driver
> for it can also be removed.
>
> Suggested-by: Chanwoo Choi <[email protected]>
> Cc: Chanwoo Choi <[email protected]>
> Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/
> Cc: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Arnd Bergmann <[email protected]>
> ---

Acked-by: Stephen Boyd <[email protected]>