2021-06-22 13:08:06

by Alim Akhtar

Subject: [PATCH v2 1/2] arm64: dts: exynos7: Add cpu cache information

This patch adds cpu caches information to its dt
nodes so that the same is available to userspace
via sysfs.
This SoC has 48/32 KB I/D cache for each cores
and 2MB of L2 cache.

Signed-off-by: Alim Akhtar <[email protected]>
---
Changes since v1:
* no change in this patch
* changes as per Krzysztof's review comments in patch 2/2

arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++
1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 10244e59d56d..8b06397ba6e7 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -54,6 +54,13 @@
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};

cpu_atlas1: cpu@1 {
@@ -61,6 +68,13 @@
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};

cpu_atlas2: cpu@2 {
@@ -68,6 +82,13 @@
compatible = "arm,cortex-a57";
reg = <0x2>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};

cpu_atlas3: cpu@3 {
@@ -75,6 +96,20 @@
compatible = "arm,cortex-a57";
reg = <0x3>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
+ };
+
+ atlas_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
};
};


base-commit: 614124bea77e452aa6df7a8714e8bc820b489922
--
2.17.1

2021-06-22 13:09:01

by Alim Akhtar

Subject: [PATCH v2 2/2] arm64: dts: exynos5433: Add cpu cache information

This patch adds cpu caches information to its dt
nodes so that the same is available to userspace
via sysfs.
This SoC has 48/32 KB I/D cache for each A57 cores
with 2MB L2 cache.
And 32/32 KB I/D cache for each A53 cores with
256KB L2 cache.

Signed-off-by: Alim Akhtar <[email protected]>
---
-Changes since v1:
* addressed Krzysztof's review comments

arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 18a912eee360..73aa0fa9b778 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -62,6 +62,13 @@
clock-names = "apolloclk";
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
};

cpu1: cpu@101 {
@@ -72,6 +79,13 @@
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
};

cpu2: cpu@102 {
@@ -82,6 +96,13 @@
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
};

cpu3: cpu@103 {
@@ -92,6 +113,13 @@
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
};

cpu4: cpu@0 {
@@ -104,6 +132,13 @@
clock-names = "atlasclk";
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cluster_a57_l2>;
};

cpu5: cpu@1 {
@@ -114,6 +149,13 @@
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cluster_a57_l2>;
};

cpu6: cpu@2 {
@@ -124,6 +166,13 @@
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cluster_a57_l2>;
};

cpu7: cpu@3 {
@@ -134,6 +183,27 @@
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cluster_a57_l2>;
+ };
+
+ cluster_a57_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ cluster_a53_l2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};

--
2.17.1

2021-06-23 06:12:05

by Krzysztof Kozlowski

Subject: Re: [PATCH v2 1/2] arm64: dts: exynos7: Add cpu cache information

On 22/06/2021 15:05, Alim Akhtar wrote:
> This patch adds cpu caches information to its dt
> nodes so that the same is available to userspace
> via sysfs.
> This SoC has 48/32 KB I/D cache for each cores
> and 2MB of L2 cache.
>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> Changes since v1:
> * no change in this patch
> * changes as per Krzysztof's review comments in patch 2/2
>
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>

Thanks, patches look good. It's too late in the cycle, so I will take
these after the merge window.


Best regards,
Krzysztof

2021-07-15 18:50:23

by Krzysztof Kozlowski

Subject: Re: [PATCH v2 1/2] arm64: dts: exynos7: Add cpu cache information

On Tue, 22 Jun 2021 18:35:50 +0530, Alim Akhtar wrote:
> This patch adds cpu caches information to its dt
> nodes so that the same is available to userspace
> via sysfs.
> This SoC has 48/32 KB I/D cache for each cores
> and 2MB of L2 cache.

Applied, thanks!

[1/2] arm64: dts: exynos7: Add cpu cache information
commit: 43e7b8b864cc5319f323dfedf633071a434410f7
[2/2] arm64: dts: exynos5433: Add cpu cache information
commit: d5c65c4aa23c52226067d7882ba2ce2055c9315d

Best regards,
--
Krzysztof Kozlowski <[email protected]>

2021-07-15 18:54:08

by Krzysztof Kozlowski

Subject: Re: [PATCH v2 1/2] arm64: dts: exynos7: Add cpu cache information

On 22/06/2021 15:05, Alim Akhtar wrote:
> This patch adds cpu caches information to its dt
> nodes so that the same is available to userspace
> via sysfs.
> This SoC has 48/32 KB I/D cache for each cores
> and 2MB of L2 cache.
>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> Changes since v1:
> * no change in this patch
> * changes as per Krzysztof's review comments in patch 2/2
>
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>

Thanks applied with fixes:
1. Title prefix as exynos,
2. Proper wrapping length of commit message (please use wrapping as in
coding style),
3. "This patch" -> imperative mode as in coding style.


Best regards,
Krzysztof