First, clean up last-level-cache parameters so that it could not
require ifdef CONFIG_SMP. Then, consolidate cache-info-related
code for x86 into arch/x86/kernel/cpu/cacheinfo.c.
Finally, for AMD, introduce new logic to derive LLC ID from APIC ID.
Thanks,
Suravee
Borislav Petkov (2):
x86/CPU/AMD: Remove unnecessary check for CONFIG_SMP
x86/CPU: Rename intel_cacheinfo.c to cacheinfo.c
Suravee Suthikulpanit (2):
perf/x86/amd/uncore: Fix amd_uncore_llc ID to use pre-defined
cpu_llc_id
x86/CPU/AMD: Calculate LLC ID from number of sharing threads
arch/x86/events/amd/uncore.c | 21 ++----------
arch/x86/include/asm/cacheinfo.h | 7 ++++
arch/x86/include/asm/smp.h | 1 -
arch/x86/kernel/cpu/Makefile | 2 +-
arch/x86/kernel/cpu/amd.c | 25 ++-------------
.../kernel/cpu/{intel_cacheinfo.c => cacheinfo.c} | 37 ++++++++++++++++++++++
arch/x86/kernel/cpu/common.c | 7 ++++
arch/x86/kernel/smpboot.c | 7 ----
8 files changed, 57 insertions(+), 50 deletions(-)
create mode 100644 arch/x86/include/asm/cacheinfo.h
rename arch/x86/kernel/cpu/{intel_cacheinfo.c => cacheinfo.c} (96%)
--
2.7.4
Last-Level-Cache ID can be calculated from the number of threads sharing
the cache, which is available from CPUID Fn0x8000001D (Cache Properties).
This is used to left-shift the APIC ID to derive LLC ID.
Therefore, default to this method unless the APIC ID enumeration does not
follow the scheme.
Signed-off-by: Suravee Suthikulpanit <[email protected]>
---
arch/x86/include/asm/cacheinfo.h | 7 +++++++
arch/x86/kernel/cpu/amd.c | 19 +++----------------
arch/x86/kernel/cpu/cacheinfo.c | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 47 insertions(+), 16 deletions(-)
create mode 100644 arch/x86/include/asm/cacheinfo.h
diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h
new file mode 100644
index 0000000..e958e28
--- /dev/null
+++ b/arch/x86/include/asm/cacheinfo.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_X86_CACHEINFO_H
+#define _ASM_X86_CACHEINFO_H
+
+void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
+
+#endif /* _ASM_X86_CACHEINFO_H */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 922f43c..2c1a9f2 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -9,6 +9,7 @@
#include <linux/random.h>
#include <asm/processor.h>
#include <asm/apic.h>
+#include <asm/cacheinfo.h>
#include <asm/cpu.h>
#include <asm/smp.h>
#include <asm/pci-direct.h>
@@ -343,22 +344,8 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
c->x86_max_cores /= smp_num_siblings;
}
- /*
- * We may have multiple LLCs if L3 caches exist, so check if we
- * have an L3 cache by looking at the L3 cache CPUID leaf.
- */
- if (cpuid_edx(0x80000006)) {
- if (c->x86 == 0x17) {
- /*
- * LLC is at the core complex level.
- * Core complex id is ApicId[3].
- */
- per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
- } else {
- /* LLC is at the node level. */
- per_cpu(cpu_llc_id, cpu) = node_id;
- }
- }
+ cacheinfo_amd_init_llc_id(c, cpu, node_id);
+
} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
u64 value;
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 54d04d5..67f4790 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -637,6 +637,43 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c)
return i;
}
+void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
+{
+ /*
+ * We may have multiple LLCs if L3 caches exist, so check if we
+ * have an L3 cache by looking at the L3 cache CPUID leaf.
+ */
+ if (!cpuid_edx(0x80000006))
+ return;
+
+ if (c->x86 < 0x17) {
+ /* LLC is at the node level. */
+ per_cpu(cpu_llc_id, cpu) = node_id;
+ } else if (c->x86 == 0x17 &&
+ c->x86_model >= 0 && c->x86_model <= 0x1F) {
+ /*
+ * LLC is at the core complex level.
+ * Core complex id is ApicId[3] for these processors.
+ */
+ per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
+ } else {
+ /* LLC ID is calculated from the number of thread sharing. */
+ u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
+ u32 llc_index = find_num_cache_leaves(c) - 1;
+
+ cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
+ if (eax)
+ num_sharing_cache = ((eax >> 14) & 0xfff) + 1;
+
+ if (num_sharing_cache) {
+ int bits = get_count_order(num_sharing_cache) - 1;
+
+ per_cpu(cpu_llc_id, cpu) = c->apicid >> bits;
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(cacheinfo_amd_init_llc_id);
+
void init_amd_cacheinfo(struct cpuinfo_x86 *c)
{
--
2.7.4
From: Borislav Petkov <[email protected]>
Since this file contains general cache-related information for x86,
rename the file to a more appropriate name.
Signed-off-by: Borislav Petkov <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
---
arch/x86/kernel/cpu/Makefile | 2 +-
arch/x86/kernel/cpu/{intel_cacheinfo.c => cacheinfo.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/x86/kernel/cpu/{intel_cacheinfo.c => cacheinfo.c} (100%)
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 570e8bb..32591f2 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -17,7 +17,7 @@ KCOV_INSTRUMENT_perf_event.o := n
nostackp := $(call cc-option, -fno-stack-protector)
CFLAGS_common.o := $(nostackp)
-obj-y := intel_cacheinfo.o scattered.o topology.o
+obj-y := cacheinfo.o scattered.o topology.o
obj-y += common.o
obj-y += rdrand.o
obj-y += match.o
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
similarity index 100%
rename from arch/x86/kernel/cpu/intel_cacheinfo.c
rename to arch/x86/kernel/cpu/cacheinfo.c
--
2.7.4
From: Borislav Petkov <[email protected]>
Move smp_num_siblings and cpu_llc_id to cpu/common.c so that they're
always present as symbols and not only in the CONFIG_SMP case. Then,
other code using them doesn't need ugly ifdeffery anymore.
Signed-off-by: Borislav Petkov <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
---
arch/x86/include/asm/smp.h | 1 -
arch/x86/kernel/cpu/amd.c | 6 ------
arch/x86/kernel/cpu/common.c | 7 +++++++
arch/x86/kernel/smpboot.c | 7 -------
4 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index a418976..59a01f6 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -171,7 +171,6 @@ static inline int wbinvd_on_all_cpus(void)
wbinvd();
return 0;
}
-#define smp_num_siblings 1
#endif /* CONFIG_SMP */
extern unsigned disabled_cpus;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f0e6456..922f43c 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -297,7 +297,6 @@ static int nearby_node(int apicid)
}
#endif
-#ifdef CONFIG_SMP
/*
* Fix up cpu_core_id for pre-F17h systems to be in the
* [0 .. cores_per_node - 1] range. Not really needed but
@@ -375,7 +374,6 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
legacy_fixup_core_id(c);
}
}
-#endif
/*
* On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
@@ -383,7 +381,6 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
*/
static void amd_detect_cmp(struct cpuinfo_x86 *c)
{
-#ifdef CONFIG_SMP
unsigned bits;
int cpu = smp_processor_id();
@@ -395,15 +392,12 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
/* use socket ID also for last level cache */
per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
amd_get_topology(c);
-#endif
}
u16 amd_get_nb_id(int cpu)
{
u16 id = 0;
-#ifdef CONFIG_SMP
id = per_cpu(cpu_llc_id, cpu);
-#endif
return id;
}
EXPORT_SYMBOL_GPL(amd_get_nb_id);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 348cf48..2afd854 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -66,6 +66,13 @@ cpumask_var_t cpu_callin_mask;
/* representing cpus for which sibling maps can be computed */
cpumask_var_t cpu_sibling_setup_mask;
+/* Number of siblings per CPU package */
+int smp_num_siblings = 1;
+EXPORT_SYMBOL(smp_num_siblings);
+
+/* Last level cache ID of each logical CPU */
+DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
+
/* correctly size the local cpu masks */
void __init setup_cpu_local_masks(void)
{
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index ff99e2b..91d48f3 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -78,13 +78,6 @@
#include <asm/misc.h>
#include <asm/qspinlock.h>
-/* Number of siblings per CPU package */
-int smp_num_siblings = 1;
-EXPORT_SYMBOL(smp_num_siblings);
-
-/* Last level cache ID of each logical CPU */
-DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
-
/* representing HT siblings of each logical CPU */
DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
--
2.7.4
Current logic iterates over CPUID Fn8000001d leafs (Cache Properties)
to detect the last level cache, and derive the last-level cache ID.
However, this information is already available in the cpu_llc_id.
Therefore, make use of it instead.
Reviewed-by: Borislav Petkov <[email protected]>
Cc: Janakarajan Natarajan <[email protected]>
Signed-off-by: Suravee Suthikulpanit <[email protected]>
---
arch/x86/events/amd/uncore.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index f5cbbba..981ba5e 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -19,6 +19,7 @@
#include <asm/cpufeature.h>
#include <asm/perf_event.h>
#include <asm/msr.h>
+#include <asm/smp.h>
#define NUM_COUNTERS_NB 4
#define NUM_COUNTERS_L2 4
@@ -399,26 +400,8 @@ static int amd_uncore_cpu_starting(unsigned int cpu)
}
if (amd_uncore_llc) {
- unsigned int apicid = cpu_data(cpu).apicid;
- unsigned int nshared, subleaf, prev_eax = 0;
-
uncore = *per_cpu_ptr(amd_uncore_llc, cpu);
- /*
- * Iterate over Cache Topology Definition leaves until no
- * more cache descriptions are available.
- */
- for (subleaf = 0; subleaf < 5; subleaf++) {
- cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx);
-
- /* EAX[0:4] gives type of cache */
- if (!(eax & 0x1f))
- break;
-
- prev_eax = eax;
- }
- nshared = ((prev_eax >> 14) & 0xfff) + 1;
-
- uncore->id = apicid - (apicid % nshared);
+ uncore->id = per_cpu(cpu_llc_id, cpu);
uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);
*per_cpu_ptr(amd_uncore_llc, cpu) = uncore;
--
2.7.4
On Mon, Mar 26, 2018 at 01:35:16AM -0500, Suravee Suthikulpanit wrote:
> diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
> index 54d04d5..67f4790 100644
> --- a/arch/x86/kernel/cpu/cacheinfo.c
> +++ b/arch/x86/kernel/cpu/cacheinfo.c
> @@ -637,6 +637,43 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c)
> return i;
> }
>
> +void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
> +{
> + /*
> + * We may have multiple LLCs if L3 caches exist, so check if we
> + * have an L3 cache by looking at the L3 cache CPUID leaf.
> + */
> + if (!cpuid_edx(0x80000006))
> + return;
> +
> + if (c->x86 < 0x17) {
> + /* LLC is at the node level. */
> + per_cpu(cpu_llc_id, cpu) = node_id;
> + } else if (c->x86 == 0x17 &&
> + c->x86_model >= 0 && c->x86_model <= 0x1F) {
> + /*
> + * LLC is at the core complex level.
> + * Core complex id is ApicId[3] for these processors.
> + */
> + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
> + } else {
> + /* LLC ID is calculated from the number of thread sharing. */
> + u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
> + u32 llc_index = find_num_cache_leaves(c) - 1;
> +
> + cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
> + if (eax)
> + num_sharing_cache = ((eax >> 14) & 0xfff) + 1;
> +
> + if (num_sharing_cache) {
> + int bits = get_count_order(num_sharing_cache) - 1;
> +
> + per_cpu(cpu_llc_id, cpu) = c->apicid >> bits;
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(cacheinfo_amd_init_llc_id);
That function needs to be exported to modules because...?
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--
Boris,
On 4/17/18 3:28 AM, Borislav Petkov wrote:
>> +EXPORT_SYMBOL_GPL(cacheinfo_amd_init_llc_id);
> That function needs to be exported to modules because...?
I missed this part. I'll send out V2.
Thanks,
Suravee