Some accumulated updates for lx2160/lx2162 SoC and boards with two
missing binding updates being used already.
v2 updates:
- Dropped duplicated "arm64: dts: lx2160a-qds: enable sata nodes"
- Removed binding patches which are applied in fsl-soc tree
- Enables optee-tz in the missing lx2162a-qds board
- added new patches "arm64: dts: lx2162a-qds: add interrupt line for RTC node"
- added new patches "arm64: dts: lx2162a-qds: enable CAN nodes"
Biwen Li (1):
arm64: dts: lx2162a-qds: add interrupt line for RTC node
Ioana Radulescu (1):
arm64: dts: lx2160a-rdb: Add Inphi PHY node
Kuldeep Singh (1):
arm64: dts: lx2162a-qds: enable CAN nodes
Li Yang (1):
arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon
Pankaj Bansal (1):
arm64: dts: lx2160a-qds: Add mdio mux nodes
Pankaj Gupta (1):
arm64: dts: lx2160a: add optee-tz node
Ran Wang (1):
arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodes
Xiaowei Bao (1):
arm64: dts: lx2160a: add pcie EP mode nodes
Yangbo Lu (1):
arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modes
Zhang Ying-22455 (1):
arm64: dts: lx2160a: fix scl-gpios property name
.../boot/dts/freescale/fsl-lx2160a-qds.dts | 149 +++++++++++++++
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 21 +++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 170 ++++++++++++------
.../boot/dts/freescale/fsl-lx2162a-qds.dts | 21 +++
4 files changed, 311 insertions(+), 50 deletions(-)
--
2.25.1
From: Ioana Radulescu <[email protected]>
DPMAC5 and DPMAC6 are connected to 25G Inphi PHY
Signed-off-by: Vicentiu Galanopulo <[email protected]>
Signed-off-by: Florin Chiculita <[email protected]>
Signed-off-by: Ioana Radulescu <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 028ff8074b9d..0ec41838e54e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -49,6 +49,14 @@ &dpmac4 {
managed = "in-band-status";
};
+&dpmac5 {
+ phy-handle = <&inphi_phy>;
+};
+
+&dpmac6 {
+ phy-handle = <&inphi_phy>;
+};
+
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
@@ -109,6 +117,15 @@ can-transceiver {
};
};
+&emdio2 {
+ status = "okay";
+
+ inphi_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0210.7440";
+ reg = <0x0>;
+ };
+};
+
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
--
2.25.1
From: Zhang Ying-22455 <[email protected]>
Fix the typo in the property name.
Signed-off-by: Zhang Ying <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index dc8661ebd1f6..2433e6f2eda8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -719,7 +719,7 @@ i2c0: i2c@2000000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
- scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -768,7 +768,7 @@ i2c4: i2c@2040000 {
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
- scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
--
2.25.1
From: Pankaj Gupta <[email protected]>
Disabled by default in SoC dtsi and enables in board dts files.
Signed-off-by: Pankaj Gupta <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 4 ++++
4 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index d858d9c8b583..8354af0b31e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -156,6 +156,10 @@ rtc@51 {
};
};
+&optee {
+ status = "okay";
+};
+
&sata0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 0ec41838e54e..0c44b3cbef77 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -219,6 +219,10 @@ rtc@51 {
};
};
+&optee {
+ status = "okay";
+};
+
&pcs_mdio3 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 2433e6f2eda8..fcde09f36018 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1751,4 +1751,12 @@ dpmac18: ethernet@12 {
};
};
};
+
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ status = "disabled";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index e1defee1ad27..8e1b7bff64a5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -307,6 +307,10 @@ rtc@51 {
};
};
+&optee {
+ status = "okay";
+};
+
&sata0 {
status = "okay";
};
--
2.25.1
From: Biwen Li <[email protected]>
Add interrupt line for RTC node on lx2162a-qds
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index a2452efd2532..a657835794e2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -309,6 +309,8 @@ temperature-sensor@4c {
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */
+ interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
--
2.25.1
From: Kuldeep Singh <[email protected]>
Enable CAN support for LX2162A-QDS in board dts.
Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index a657835794e2..a1644ceed154 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -167,6 +167,14 @@ mdio@7 { /* Slot #8 (secondary EMI) */
};
};
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
&crypto {
status = "okay";
};
--
2.25.1
From: Pankaj Bansal <[email protected]>
The two external MDIO buses used to communicate with phy devices that
are external to SOC are muxed in LX2160AQDS board. These buses can be
routed to any one of the eight IO slots on LX2160AQDS board depending on
value in fpga register 0x54. Additionally the external MDIO1 is used to
communicate to the onboard RGMII phy devices. The mdio1 is controlled
by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga
register.
Signed-off-by: Pankaj Bansal <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 8354af0b31e3..2ecfa90f5e28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -31,6 +31,130 @@ sb_3v3: regulator-sb3v3 {
regulator-boot-on;
regulator-always-on;
};
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* On-board PHY #1 RGMI1*/
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 { /* On-board PHY #2 RGMI2*/
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@18 { /* Slot #1 */
+ reg = <0x18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@19 { /* Slot #2 */
+ reg = <0x19>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1a { /* Slot #3 */
+ reg = <0x1a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1b { /* Slot #4 */
+ reg = <0x1b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1c { /* Slot #5 */
+ reg = <0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1d { /* Slot #6 */
+ reg = <0x1d>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1e { /* Slot #7 */
+ reg = <0x1e>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1f { /* Slot #8 */
+ reg = <0x1f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells=<1>;
+ #size-cells = <0>;
+
+ mdio@0 { /* Slot #1 (secondary EMI) */
+ reg = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 { /* Slot #2 (secondary EMI) */
+ reg = <0x01>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@2 { /* Slot #3 (secondary EMI) */
+ reg = <0x02>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@3 { /* Slot #4 (secondary EMI) */
+ reg = <0x03>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@4 { /* Slot #5 (secondary EMI) */
+ reg = <0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@5 { /* Slot #6 (secondary EMI) */
+ reg = <0x05>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@6 { /* Slot #7 (secondary EMI) */
+ reg = <0x06>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@7 { /* Slot #8 (secondary EMI) */
+ reg = <0x07>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
&can0 {
@@ -81,6 +205,14 @@ dflash2: flash@0 {
};
};
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
&esdhc0 {
status = "okay";
};
@@ -107,6 +239,19 @@ mt35xu512aba0: flash@0 {
&i2c0 {
status = "okay";
+ fpga@66 {
+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
+ "simple-mfd";
+ reg = <0x66>;
+
+ mux: mux-controller {
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
+ };
+ };
+
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
--
2.25.1
The original dts was created based on the non-production rev1 silicon
which was only used for evaluation. Update the PCIe nodes to align with
the different controller used in production rev2 silicon.
Signed-off-by: Li Yang <[email protected]>
Reviewed-by: Hou Zhiqiang <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 96 +++++++++----------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fcde09f36018..de680521e1d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1088,10 +1088,10 @@ sata3: sata@3230000 {
};
pcie1: pcie@3400000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
- <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1100,26 +1100,26 @@ pcie1: pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie2: pcie@3500000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
- <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1128,26 +1128,26 @@ pcie2: pcie@3500000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie3: pcie@3600000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
- <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1156,26 +1156,26 @@ pcie3: pcie@3600000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <256>;
- ppio-wins = <24>;
+ num-viewport = <256>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie4: pcie@3700000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
- <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1184,26 +1184,26 @@ pcie4: pcie@3700000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie5: pcie@3800000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
- <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
+ 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1212,26 +1212,26 @@ pcie5: pcie@3800000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <256>;
- ppio-wins = <24>;
+ num-viewport = <256>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
pcie6: pcie@3900000 {
- compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
- <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "csr_axi_slave", "config_axi_slave";
+ compatible = "fsl,ls2088a-pcie";
+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
+ 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1240,18 +1240,18 @@ pcie6: pcie@3900000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- apio-wins = <8>;
- ppio-wins = <8>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
+ 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
--
2.25.1
From: Yangbo Lu <[email protected]>
The default NXP SDHC adapter cards for LX2162AQDS are SD 2.0/3.0
adapter card for eSDHC1, and eMMC 5.1 adapter card for eSDHC2.
Add speed modes properties supported by the two adapters in device
tree node.
Signed-off-by: Yangbo Lu <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index 8e1b7bff64a5..a2452efd2532 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -226,10 +226,17 @@ &emdio2 {
};
&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
status = "okay";
};
--
2.25.1
From: Xiaowei Bao <[email protected]>
The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Li Yang <[email protected]>
Reviewed-by: Hou Zhiqiang <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index de680521e1d1..593c5a498ae3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1115,6 +1115,16 @@ pcie1: pcie@3400000 {
status = "disabled";
};
+ pcie_ep1: pcie_ep@3400000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie2: pcie@3500000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -1143,6 +1153,16 @@ pcie2: pcie@3500000 {
status = "disabled";
};
+ pcie_ep2: pcie_ep@3500000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie3: pcie@3600000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -1171,6 +1191,16 @@ pcie3: pcie@3600000 {
status = "disabled";
};
+ pcie_ep3: pcie_ep@3600000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
pcie4: pcie@3700000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
@@ -1199,6 +1229,16 @@ pcie4: pcie@3700000 {
status = "disabled";
};
+ pcie_ep4: pcie_ep@3700000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie5: pcie@3800000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
@@ -1227,6 +1267,16 @@ pcie5: pcie@3800000 {
status = "disabled";
};
+ pcie_ep5: pcie_ep@3800000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
pcie6: pcie@3900000 {
compatible = "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
@@ -1255,6 +1305,16 @@ pcie6: pcie@3900000 {
status = "disabled";
};
+ pcie_ep6: pcie_ep@3900000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.25.1
From: Ran Wang <[email protected]>
Enable USB3 HW LPM feature for lx2160a.
Signed-off-by: Ran Wang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 593c5a498ae3..c6f61a6f49bb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1023,6 +1023,7 @@ usb0: usb@3100000 {
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ usb3-lpm-capable;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
@@ -1034,6 +1035,7 @@ usb1: usb@3110000 {
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
+ usb3-lpm-capable;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
--
2.25.1
Hi Leo,
> -----Original Message-----
> From: Li Yang <[email protected]>
> Sent: Saturday, December 4, 2021 5:25 AM
> To: Shawn Guo <[email protected]>; [email protected];
> [email protected]
> Cc: Kuldeep Singh <[email protected]>; Leo Li <[email protected]>
> Subject: [PATCH v2 10/10] arm64: dts: lx2162a-qds: enable CAN nodes
>
> From: Kuldeep Singh <[email protected]>
>
> Enable CAN support for LX2162A-QDS in board dts.
This patch was sent to mailing list before and has been applied by Shawn. Please see[1].
Regards
Kuldeep
[1] https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/commit/?h=for-next&id=4172986a64dae744abe625075533ce38f6670019
On Fri, Dec 03, 2021 at 05:54:37PM -0600, Li Yang wrote:
> From: Zhang Ying-22455 <[email protected]>
>
> Fix the typo in the property name.
>
> Signed-off-by: Zhang Ying <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
Shouldn't we have a Fixes tag?
Shawn
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index dc8661ebd1f6..2433e6f2eda8 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -719,7 +719,7 @@ i2c0: i2c@2000000 {
> clock-names = "i2c";
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> - scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
> + scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
> status = "disabled";
> };
>
> @@ -768,7 +768,7 @@ i2c4: i2c@2040000 {
> clock-names = "i2c";
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> - scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
> + scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
> status = "disabled";
> };
>
> --
> 2.25.1
>
On Fri, Dec 03, 2021 at 05:54:41PM -0600, Li Yang wrote:
> The original dts was created based on the non-production rev1 silicon
> which was only used for evaluation. Update the PCIe nodes to align with
> the different controller used in production rev2 silicon.
>
> Signed-off-by: Li Yang <[email protected]>
> Reviewed-by: Hou Zhiqiang <[email protected]>
> ---
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 96 +++++++++----------
> 1 file changed, 48 insertions(+), 48 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index fcde09f36018..de680521e1d1 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -1088,10 +1088,10 @@ sata3: sata@3230000 {
> };
>
> pcie1: pcie@3400000 {
> - compatible = "fsl,lx2160a-pcie";
Drop lx2160a specific compatible for lx2160a SoC?
Shawn
> - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
> - <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "csr_axi_slave", "config_axi_slave";
> + compatible = "fsl,ls2088a-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
> + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> @@ -1100,26 +1100,26 @@ pcie1: pcie@3400000 {
> #size-cells = <2>;
> device_type = "pci";
> dma-coherent;
> - apio-wins = <8>;
> - ppio-wins = <8>;
> + num-viewport = <8>;
> bus-range = <0x0 0xff>;
> - ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
> + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> msi-parent = <&its>;
> + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> status = "disabled";
> };
>
> pcie2: pcie@3500000 {
> - compatible = "fsl,lx2160a-pcie";
> - reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
> - <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "csr_axi_slave", "config_axi_slave";
> + compatible = "fsl,ls2088a-pcie";
> + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> @@ -1128,26 +1128,26 @@ pcie2: pcie@3500000 {
> #size-cells = <2>;
> device_type = "pci";
> dma-coherent;
> - apio-wins = <8>;
> - ppio-wins = <8>;
> + num-viewport = <8>;
> bus-range = <0x0 0xff>;
> - ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
> + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> msi-parent = <&its>;
> + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> status = "disabled";
> };
>
> pcie3: pcie@3600000 {
> - compatible = "fsl,lx2160a-pcie";
> - reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
> - <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "csr_axi_slave", "config_axi_slave";
> + compatible = "fsl,ls2088a-pcie";
> + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> @@ -1156,26 +1156,26 @@ pcie3: pcie@3600000 {
> #size-cells = <2>;
> device_type = "pci";
> dma-coherent;
> - apio-wins = <256>;
> - ppio-wins = <24>;
> + num-viewport = <256>;
> bus-range = <0x0 0xff>;
> - ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
> + 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> msi-parent = <&its>;
> + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> status = "disabled";
> };
>
> pcie4: pcie@3700000 {
> - compatible = "fsl,lx2160a-pcie";
> - reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
> - <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "csr_axi_slave", "config_axi_slave";
> + compatible = "fsl,ls2088a-pcie";
> + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
> + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> @@ -1184,26 +1184,26 @@ pcie4: pcie@3700000 {
> #size-cells = <2>;
> device_type = "pci";
> dma-coherent;
> - apio-wins = <8>;
> - ppio-wins = <8>;
> + num-viewport = <8>;
> bus-range = <0x0 0xff>;
> - ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
> + 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> msi-parent = <&its>;
> + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> status = "disabled";
> };
>
> pcie5: pcie@3800000 {
> - compatible = "fsl,lx2160a-pcie";
> - reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
> - <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "csr_axi_slave", "config_axi_slave";
> + compatible = "fsl,ls2088a-pcie";
> + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
> + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> @@ -1212,26 +1212,26 @@ pcie5: pcie@3800000 {
> #size-cells = <2>;
> device_type = "pci";
> dma-coherent;
> - apio-wins = <256>;
> - ppio-wins = <24>;
> + num-viewport = <256>;
> bus-range = <0x0 0xff>;
> - ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
> + 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> msi-parent = <&its>;
> + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> status = "disabled";
> };
>
> pcie6: pcie@3900000 {
> - compatible = "fsl,lx2160a-pcie";
> - reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
> - <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
> - reg-names = "csr_axi_slave", "config_axi_slave";
> + compatible = "fsl,ls2088a-pcie";
> + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
> + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> @@ -1240,18 +1240,18 @@ pcie6: pcie@3900000 {
> #size-cells = <2>;
> device_type = "pci";
> dma-coherent;
> - apio-wins = <8>;
> - ppio-wins = <8>;
> + num-viewport = <8>;
> bus-range = <0x0 0xff>;
> - ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
> + 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> msi-parent = <&its>;
> + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> status = "disabled";
> };
>
> --
> 2.25.1
>
On Fri, Dec 03, 2021 at 05:54:42PM -0600, Li Yang wrote:
> From: Xiaowei Bao <[email protected]>
>
> The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2.
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> Reviewed-by: Hou Zhiqiang <[email protected]>
> ---
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index de680521e1d1..593c5a498ae3 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -1115,6 +1115,16 @@ pcie1: pcie@3400000 {
> status = "disabled";
> };
>
> + pcie_ep1: pcie_ep@3400000 {
Hyphen is more recommended than underscore for node name.
Shawn
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x80 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie2: pcie@3500000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> @@ -1143,6 +1153,16 @@ pcie2: pcie@3500000 {
> status = "disabled";
> };
>
> + pcie_ep2: pcie_ep@3500000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03500000 0x0 0x00100000
> + 0x88 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie3: pcie@3600000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> @@ -1171,6 +1191,16 @@ pcie3: pcie@3600000 {
> status = "disabled";
> };
>
> + pcie_ep3: pcie_ep@3600000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03600000 0x0 0x00100000
> + 0x90 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <256>;
> + num-ib-windows = <24>;
> + status = "disabled";
> + };
> +
> pcie4: pcie@3700000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
> @@ -1199,6 +1229,16 @@ pcie4: pcie@3700000 {
> status = "disabled";
> };
>
> + pcie_ep4: pcie_ep@3700000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03700000 0x0 0x00100000
> + 0x98 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie5: pcie@3800000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
> @@ -1227,6 +1267,16 @@ pcie5: pcie@3800000 {
> status = "disabled";
> };
>
> + pcie_ep5: pcie_ep@3800000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03800000 0x0 0x00100000
> + 0xa0 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <256>;
> + num-ib-windows = <24>;
> + status = "disabled";
> + };
> +
> pcie6: pcie@3900000 {
> compatible = "fsl,ls2088a-pcie";
> reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
> @@ -1255,6 +1305,16 @@ pcie6: pcie@3900000 {
> status = "disabled";
> };
>
> + pcie_ep6: pcie_ep@3900000 {
> + compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
> + reg = <0x00 0x03900000 0x0 0x00100000
> + 0xa8 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ob-windows = <8>;
> + num-ib-windows = <8>;
> + status = "disabled";
> + };
> +
> smmu: iommu@5000000 {
> compatible = "arm,mmu-500";
> reg = <0 0x5000000 0 0x800000>;
> --
> 2.25.1
>
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: Tuesday, December 14, 2021 1:40 PM
> To: Leo Li <[email protected]>
> Cc: [email protected]; [email protected]; Z.Q.
> Hou <[email protected]>
> Subject: Re: [PATCH v2 05/10] arm64: dts: lx2160a: update PCIe nodes to
> match rev2 silicon
>
> On Fri, Dec 03, 2021 at 05:54:41PM -0600, Li Yang wrote:
> > The original dts was created based on the non-production rev1 silicon
> > which was only used for evaluation. Update the PCIe nodes to align
> > with the different controller used in production rev2 silicon.
> >
> > Signed-off-by: Li Yang <[email protected]>
> > Reviewed-by: Hou Zhiqiang <[email protected]>
> > ---
> > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 96
> > +++++++++----------
> > 1 file changed, 48 insertions(+), 48 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index fcde09f36018..de680521e1d1 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -1088,10 +1088,10 @@ sata3: sata@3230000 {
> > };
> >
> > pcie1: pcie@3400000 {
> > - compatible = "fsl,lx2160a-pcie";
>
> Drop lx2160a specific compatible for lx2160a SoC?
The lx2160a compatible was defined with the rev1. We will need to create a new rev2 compatible if we want to keep the soc specific compatible.
>
> Shawn
>
> > - reg = <0x00 0x03400000 0x0 0x00100000>, /*
> controller registers */
> > - <0x80 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > - reg-names = "csr_axi_slave", "config_axi_slave";
> > + compatible = "fsl,ls2088a-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller
> registers */
> > + 0x80 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> /* AER interrupt */
> > <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /*
> PME interrupt */
> > <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt
> > */ @@ -1100,26 +1100,26 @@ pcie1: pcie@3400000 {
> > #size-cells = <2>;
> > device_type = "pci";
> > dma-coherent;
> > - apio-wins = <8>;
> > - ppio-wins = <8>;
> > + num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > - ranges = <0x82000000 0x0 0x40000000 0x80
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + ranges = <0x81000000 0x0 0x00000000 0x80
> 0x00010000 0x0 0x00010000
> > + 0x82000000 0x0 0x40000000 0x80 0x40000000
> 0x0 0x40000000>; /*
> > +non-prefetchable memory */
> > msi-parent = <&its>;
> > + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by
> u-boot */
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 2 &gic 0 0 GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 3 &gic 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 4 &gic 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> > - iommu-map = <0 &smmu 0 1>; /* Fixed-up by
> bootloader */
> > status = "disabled";
> > };
> >
> > pcie2: pcie@3500000 {
> > - compatible = "fsl,lx2160a-pcie";
> > - reg = <0x00 0x03500000 0x0 0x00100000>, /*
> controller registers */
> > - <0x88 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > - reg-names = "csr_axi_slave", "config_axi_slave";
> > + compatible = "fsl,ls2088a-pcie";
> > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller
> registers */
> > + 0x88 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> /* AER interrupt */
> > <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /*
> PME interrupt */
> > <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt
> > */ @@ -1128,26 +1128,26 @@ pcie2: pcie@3500000 {
> > #size-cells = <2>;
> > device_type = "pci";
> > dma-coherent;
> > - apio-wins = <8>;
> > - ppio-wins = <8>;
> > + num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > - ranges = <0x82000000 0x0 0x40000000 0x88
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + ranges = <0x81000000 0x0 0x00000000 0x88
> 0x00010000 0x0 0x00010000
> > + 0x82000000 0x0 0x40000000 0x88 0x40000000
> 0x0 0x40000000>; /*
> > +non-prefetchable memory */
> > msi-parent = <&its>;
> > + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by
> u-boot */
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 2 &gic 0 0 GIC_SPI 115
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 3 &gic 0 0 GIC_SPI 116
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 4 &gic 0 0 GIC_SPI 117
> IRQ_TYPE_LEVEL_HIGH>;
> > - iommu-map = <0 &smmu 0 1>; /* Fixed-up by
> bootloader */
> > status = "disabled";
> > };
> >
> > pcie3: pcie@3600000 {
> > - compatible = "fsl,lx2160a-pcie";
> > - reg = <0x00 0x03600000 0x0 0x00100000>, /*
> controller registers */
> > - <0x90 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > - reg-names = "csr_axi_slave", "config_axi_slave";
> > + compatible = "fsl,ls2088a-pcie";
> > + reg = <0x00 0x03600000 0x0 0x00100000 /* controller
> registers */
> > + 0x90 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> /* AER interrupt */
> > <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /*
> PME interrupt */
> > <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt
> > */ @@ -1156,26 +1156,26 @@ pcie3: pcie@3600000 {
> > #size-cells = <2>;
> > device_type = "pci";
> > dma-coherent;
> > - apio-wins = <256>;
> > - ppio-wins = <24>;
> > + num-viewport = <256>;
> > bus-range = <0x0 0xff>;
> > - ranges = <0x82000000 0x0 0x40000000 0x90
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + ranges = <0x81000000 0x0 0x00000000 0x90
> 0x00010000 0x0 0x00010000
> > + 0x82000000 0x0 0x40000000 0x90 0x40000000
> 0x0 0x40000000>; /*
> > +non-prefetchable memory */
> > msi-parent = <&its>;
> > + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by
> u-boot */
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 2 &gic 0 0 GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 3 &gic 0 0 GIC_SPI 121
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 4 &gic 0 0 GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>;
> > - iommu-map = <0 &smmu 0 1>; /* Fixed-up by
> bootloader */
> > status = "disabled";
> > };
> >
> > pcie4: pcie@3700000 {
> > - compatible = "fsl,lx2160a-pcie";
> > - reg = <0x00 0x03700000 0x0 0x00100000>, /*
> controller registers */
> > - <0x98 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > - reg-names = "csr_axi_slave", "config_axi_slave";
> > + compatible = "fsl,ls2088a-pcie";
> > + reg = <0x00 0x03700000 0x0 0x00100000 /* controller
> registers */
> > + 0x98 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> /* AER interrupt */
> > <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /*
> PME interrupt */
> > <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt
> > */ @@ -1184,26 +1184,26 @@ pcie4: pcie@3700000 {
> > #size-cells = <2>;
> > device_type = "pci";
> > dma-coherent;
> > - apio-wins = <8>;
> > - ppio-wins = <8>;
> > + num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > - ranges = <0x82000000 0x0 0x40000000 0x98
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + ranges = <0x81000000 0x0 0x00000000 0x98
> 0x00010000 0x0 0x00010000
> > + 0x82000000 0x0 0x40000000 0x98 0x40000000
> 0x0 0x40000000>; /*
> > +non-prefetchable memory */
> > msi-parent = <&its>;
> > + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by
> u-boot */
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 2 &gic 0 0 GIC_SPI 125
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 3 &gic 0 0 GIC_SPI 126
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 4 &gic 0 0 GIC_SPI 127
> IRQ_TYPE_LEVEL_HIGH>;
> > - iommu-map = <0 &smmu 0 1>; /* Fixed-up by
> bootloader */
> > status = "disabled";
> > };
> >
> > pcie5: pcie@3800000 {
> > - compatible = "fsl,lx2160a-pcie";
> > - reg = <0x00 0x03800000 0x0 0x00100000>, /*
> controller registers */
> > - <0xa0 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > - reg-names = "csr_axi_slave", "config_axi_slave";
> > + compatible = "fsl,ls2088a-pcie";
> > + reg = <0x00 0x03800000 0x0 0x00100000 /* controller
> registers */
> > + 0xa0 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> /* AER interrupt */
> > <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /*
> PME interrupt */
> > <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt
> > */ @@ -1212,26 +1212,26 @@ pcie5: pcie@3800000 {
> > #size-cells = <2>;
> > device_type = "pci";
> > dma-coherent;
> > - apio-wins = <256>;
> > - ppio-wins = <24>;
> > + num-viewport = <256>;
> > bus-range = <0x0 0xff>;
> > - ranges = <0x82000000 0x0 0x40000000 0xa0
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + ranges = <0x81000000 0x0 0x00000000 0xa0
> 0x00010000 0x0 0x00010000
> > + 0x82000000 0x0 0x40000000 0xa0 0x40000000
> 0x0 0x40000000>; /*
> > +non-prefetchable memory */
> > msi-parent = <&its>;
> > + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by
> u-boot */
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 2 &gic 0 0 GIC_SPI 130
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 3 &gic 0 0 GIC_SPI 131
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 4 &gic 0 0 GIC_SPI 132
> IRQ_TYPE_LEVEL_HIGH>;
> > - iommu-map = <0 &smmu 0 1>; /* Fixed-up by
> bootloader */
> > status = "disabled";
> > };
> >
> > pcie6: pcie@3900000 {
> > - compatible = "fsl,lx2160a-pcie";
> > - reg = <0x00 0x03900000 0x0 0x00100000>, /*
> controller registers */
> > - <0xa8 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > - reg-names = "csr_axi_slave", "config_axi_slave";
> > + compatible = "fsl,ls2088a-pcie";
> > + reg = <0x00 0x03900000 0x0 0x00100000 /* controller
> registers */
> > + 0xa8 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> /* AER interrupt */
> > <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /*
> PME interrupt */
> > <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt
> > */ @@ -1240,18 +1240,18 @@ pcie6: pcie@3900000 {
> > #size-cells = <2>;
> > device_type = "pci";
> > dma-coherent;
> > - apio-wins = <8>;
> > - ppio-wins = <8>;
> > + num-viewport = <8>;
> > bus-range = <0x0 0xff>;
> > - ranges = <0x82000000 0x0 0x40000000 0xa8
> 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> > + ranges = <0x81000000 0x0 0x00000000 0xa8
> 0x00010000 0x0 0x00010000
> > + 0x82000000 0x0 0x40000000 0xa8 0x40000000
> 0x0 0x40000000>; /*
> > +non-prefetchable memory */
> > msi-parent = <&its>;
> > + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by
> u-boot */
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 2 &gic 0 0 GIC_SPI 105
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 3 &gic 0 0 GIC_SPI 106
> IRQ_TYPE_LEVEL_HIGH>,
> > <0000 0 0 4 &gic 0 0 GIC_SPI 107
> IRQ_TYPE_LEVEL_HIGH>;
> > - iommu-map = <0 &smmu 0 1>; /* Fixed-up by
> bootloader */
> > status = "disabled";
> > };
> >
> > --
> > 2.25.1
> >