Hi All,
This patch set adds initial board support for R8A7742 SoC,
enabling R8A7742 arch in defconfigs with initial dtsi.
Cheers,
--Prabhakar
Lad Prabhakar (18):
soc: renesas: Add Renesas R8A7742 config option
ARM: shmobile: defconfig: Enable r8a7742 SoC
ARM: multi_v7_defconfig: Enable r8a7742 SoC
ARM: debug-ll: Add support for r8a7742
dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support
pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support
ARM: dts: r8a7742: Initial SoC device tree
dt-bindings: irqchip: renesas-irqc: Document r8a7742 bindings
ARM: dts: r8a7742: Add IRQC support
dt-bindings: rcar-dmac: Document r8a7742 support
ARM: dts: r8a7742: Add SYS-DMAC support
dt-bindings: serial: renesas,scif: Document r8a7742 bindings
dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
dt-bindings: serial: renesas,scifb: Document r8a7742 bindings
dt-bindings: serial: renesas,hscif: Document r8a7742 bindings
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
dt-bindings: gpio: rcar: Add r8a7742 (RZ/G1H) support
ARM: dts: r8a7742: Add GPIO support
.../devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
.../interrupt-controller/renesas,irqc.yaml | 1 +
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
.../devicetree/bindings/serial/renesas,hscif.yaml | 1 +
.../devicetree/bindings/serial/renesas,scif.yaml | 1 +
.../devicetree/bindings/serial/renesas,scifa.yaml | 1 +
.../devicetree/bindings/serial/renesas,scifb.yaml | 1 +
arch/arm/Kconfig.debug | 10 +
arch/arm/boot/dts/r8a7742.dtsi | 939 +++++++++++++++++++++
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/shmobile_defconfig | 1 +
drivers/pinctrl/sh-pfc/Kconfig | 4 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 6 +
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 24 +
drivers/pinctrl/sh-pfc/sh_pfc.h | 1 +
drivers/soc/renesas/Kconfig | 7 +
18 files changed, 1002 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742.dtsi
--
2.7.4
Add configuration option for the RZ/G1H (R8A77420) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
drivers/soc/renesas/Kconfig | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 1eff82c..53cd8d2 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -83,6 +83,13 @@ config ARCH_R8A7740
select ARM_ERRATA_754322
select RENESAS_INTC_IRQPIN
+config ARCH_R8A7742
+ bool "RZ/G1H (R8A77420)"
+ select ARCH_RCAR_GEN2
+ select ARM_ERRATA_798181 if SMP
+ select ARM_ERRATA_814220
+ select SYSC_R8A7742
+
config ARCH_R8A7743
bool "RZ/G1M (R8A77430)"
select ARCH_RCAR_GEN2
--
2.7.4
Enable recently added r8a7742 (RZ/G1H) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/configs/shmobile_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 361e8ff..643525d 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -181,6 +181,7 @@ CONFIG_ARCH_R7S72100=y
CONFIG_ARCH_R7S9210=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7742=y
CONFIG_ARCH_R8A7743=y
CONFIG_ARCH_R8A7744=y
CONFIG_ARCH_R8A7745=y
--
2.7.4
Enable low-level debugging support for RZ/G1H (R8A7742). RZ/G1H uses
SCIFA2 for the debug console.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f46e18a..d0631e2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -976,6 +976,13 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/G1E (R8A7745).
+ config DEBUG_RCAR_GEN2_SCIFA2
+ bool "Kernel low-level debugging messages via SCIFA2 on ARCH_R8A7742"
+ depends on ARCH_R8A7742
+ help
+ Say Y here if you want kernel low-level debugging support
+ via SCIFA2 on Renesas RZ/G1H (R8A7742).
+
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
@@ -1577,6 +1584,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
+ default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIFA2
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@@ -1701,6 +1709,7 @@ config DEBUG_UART_PHYS
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
+ default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2
default 0xe8008000 if DEBUG_R7S72100_SCIF2 || DEBUG_R7S9210_SCIF2
default 0xe8009000 if DEBUG_R7S9210_SCIF4
default 0xf0000000 if DEBUG_DIGICOLOR_UA0
@@ -1737,6 +1746,7 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
+ DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
--
2.7.4
Document PFC support for the RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 6eada23..b686131 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -13,6 +13,7 @@ Required Properties:
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+ - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
--
2.7.4
Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790).
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
drivers/pinctrl/sh-pfc/Kconfig | 4 ++++
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 6 ++++++
drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 24 ++++++++++++++++++++++++
drivers/pinctrl/sh-pfc/sh_pfc.h | 1 +
5 files changed, 36 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 9552851..c461a2f 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -12,6 +12,7 @@ config PINCTRL_SH_PFC
select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
+ select PINCTRL_PFC_R8A7742 if ARCH_R8A7742
select PINCTRL_PFC_R8A7743 if ARCH_R8A7743
select PINCTRL_PFC_R8A7744 if ARCH_R8A7744
select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
@@ -74,6 +75,9 @@ config PINCTRL_PFC_R8A7740
bool "R-Mobile A1 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
+config PINCTRL_PFC_R8A7742
+ bool "RZ/G1H pin control support" if COMPILE_TEST
+
config PINCTRL_PFC_R8A7743
bool "RZ/G1M pin control support" if COMPILE_TEST
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 9ebe321..3855d82 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index a2e19ef..f368383 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -485,6 +485,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7740_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7742
+ {
+ .compatible = "renesas,pfc-r8a7742",
+ .data = &r8a7742_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7743
{
.compatible = "renesas,pfc-r8a7743",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 3366ed5..11cbcff 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -5736,6 +5736,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
.ops = &r8a7790_pinmux_ops,
@@ -5755,3 +5756,26 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7742
+const struct sh_pfc_soc_info r8a7742_pinmux_info = {
+ .name = "r8a77420_pfc",
+ .ops = &r8a7790_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index d57e633..0f01382 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -304,6 +304,7 @@ struct sh_pfc_soc_info {
extern const struct sh_pfc_soc_info emev2_pinmux_info;
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
--
2.7.4
Basic support for the RZ/G1H (R8A7742) SoC. Added placeholders
for the peripherals supported by the SoC which will be filled up
by incremental patches.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/boot/dts/r8a7742.dtsi | 715 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 715 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742.dtsi
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
new file mode 100644
index 0000000..a2c858e
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -0,0 +1,715 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7742 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
+#include <dt-bindings/power/r8a7742-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7742";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7742_PD_CA15_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA7: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7742_PD_CA7_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ pmu-0 {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ pmu-1 {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ /* placeholder */
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7742";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7742-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7742-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7742-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x100>;
+ };
+ };
+
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
+ };
+
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6508000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6518000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6530000 0 0x40>;
+ /* placeholder */
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6540000 0 0x40>;
+ /* placeholder */
+ };
+
+ iic0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6500000 0 0x425>;
+ /* placeholder */
+ };
+
+ iic1: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6510000 0 0x425>;
+ /* placeholder */
+ };
+
+ iic2: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe6520000 0 0x425>;
+ /* placeholder */
+ };
+
+ iic3: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xe60b0000 0 0x425>;
+ /* placeholder */
+ };
+
+ hsusb: usb@e6590000 {
+ reg = <0 0xe6590000 0 0x100>;
+ /* placeholder */
+ };
+
+ usbphy: usb-phy@e6590100 {
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* placeholder */
+ };
+
+ avb: ethernet@e6800000 {
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* placeholder */
+ };
+
+ scifa0: serial@e6c40000 {
+ reg = <0 0xe6c40000 0 0x40>;
+ /* placeholder */
+ };
+
+ scifa1: serial@e6c50000 {
+ reg = <0 0xe6c50000 0 0x40>;
+ /* placeholder */
+ };
+
+ scifa2: serial@e6c60000 {
+ reg = <0 0xe6c60000 0 0x40>;
+ /* placeholder */
+ };
+
+ scifb0: serial@e6c20000 {
+ reg = <0 0xe6c20000 0 0x100>;
+ /* placeholder */
+ };
+
+ scifb1: serial@e6c30000 {
+ reg = <0 0xe6c30000 0 0x100>;
+ /* placeholder */
+ };
+
+ scifb2: serial@e6ce0000 {
+ reg = <0 0xe6ce0000 0 0x100>;
+ /* placeholder */
+ };
+
+ scif0: serial@e6e60000 {
+ reg = <0 0xe6e60000 0 0x40>;
+ /* placeholder */
+ };
+
+ scif1: serial@e6e68000 {
+ reg = <0 0xe6e68000 0 0x40>;
+ /* placeholder */
+ };
+
+ hscif0: serial@e62c0000 {
+ reg = <0 0xe62c0000 0 0x60>;
+ /* placeholder */
+ };
+
+ hscif1: serial@e62c8000 {
+ reg = <0 0xe62c8000 0 0x60>;
+ /* placeholder */
+ };
+
+ can0: can@e6e80000 {
+ reg = <0 0xe6e80000 0 0x1000>;
+ /* placeholder */
+ };
+
+ can1: can@e6e88000 {
+ reg = <0 0xe6e88000 0 0x1000>;
+ /* placeholder */
+ };
+
+ rcar_sound: sound@ec500000 {
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>; /* SSI */
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {};
+ dvc1: dvc-1 {};
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {};
+ src1: src-1 {};
+ src2: src-2 {};
+ src3: src-3 {};
+ src4: src-4 {};
+ src5: src-5 {};
+ src6: src-6 {};
+ src7: src-7 {};
+ src8: src-8 {};
+ src9: src-9 {};
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {};
+ ssi1: ssi-1 {};
+ ssi2: ssi-2 {};
+ ssi3: ssi-3 {};
+ ssi4: ssi-4 {};
+ ssi5: ssi-5 {};
+ ssi6: ssi-6 {};
+ ssi7: ssi-7 {};
+ ssi8: ssi-8 {};
+ ssi9: ssi-9 {};
+ };
+ /* placeholder */
+ };
+
+ pci0: pci@ee090000 {
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ /* placeholder */
+ };
+
+ pci1: pci@ee0b0000 {
+ reg = <0 0xee0b0000 0 0xc00>,
+ <0 0xee0a0000 0 0x1100>;
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ /* placeholder */
+ };
+
+ pci2: pci@ee0d0000 {
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ bus-range = <2 2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ /* placeholder */
+ };
+
+ pciec: pcie@fe000000 {
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ #interrupt-cells = <1>;
+ /* placeholder */
+ };
+
+ sdhi0: sd@ee100000 {
+ reg = <0 0xee100000 0 0x328>;
+ /* placeholder */
+ };
+
+ sdhi1: sd@ee120000 {
+ reg = <0 0xee120000 0 0x328>;
+ /* placeholder */
+ };
+
+ sdhi2: sd@ee140000 {
+ reg = <0 0xee140000 0 0x100>;
+ /* placeholder */
+ };
+
+ sdhi3: sd@ee160000 {
+ reg = <0 0xee160000 0 0x100>;
+ /* placeholder */
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ du: display@feb00000 {
+ reg = <0 0xfeb00000 0 0x70000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ };
+ };
+ /* placeholder */
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ reg = <0 0xfeb90000 0 0x1c>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ /* placeholder */
+ };
+
+ lvds1: lvds@feb94000 {
+ reg = <0 0xfeb94000 0 0x1c>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds1_in: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds1_out: endpoint {
+ };
+ };
+ };
+ /* placeholder */
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+};
--
2.7.4
Describe the IRQC interrupt controller in the r8a7742 device tree.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/boot/dts/r8a7742.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index a2c858e..4c7baf2 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -337,6 +337,20 @@
#power-domain-cells = <1>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7742", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
--
2.7.4
Document SoC specific bindings for RZ/G1H (r8a7742) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
index ee5273b..1bd741d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
@@ -14,6 +14,7 @@ properties:
items:
- enum:
- renesas,irqc-r8a73a4 # R-Mobile APE6
+ - renesas,irqc-r8a7742 # RZ/G1H
- renesas,irqc-r8a7743 # RZ/G1M
- renesas,irqc-r8a7744 # RZ/G1N
- renesas,irqc-r8a7745 # RZ/G1E
--
2.7.4
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFB ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/serial/renesas,scifb.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml
index 57205cb..b083970 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- enum:
+ - renesas,scifb-r8a7742 # RZ/G1H
- renesas,scifb-r8a7743 # RZ/G1M
- renesas,scifb-r8a7744 # RZ/G1N
- renesas,scifb-r8a7745 # RZ/G1E
--
2.7.4
Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
Document RZ/G1H (also known as R8A7742) SoC bindings.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index b7f81c6..1168cd5 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -16,6 +16,7 @@ Required Properties:
- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
Examples with soctypes are:
+ - "renesas,dmac-r8a7742" (RZ/G1H)
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7744" (RZ/G1N)
- "renesas,dmac-r8a7745" (RZ/G1E)
--
2.7.4
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/serial/renesas,scifa.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml
index b28bcb2..97ddd76 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- enum:
+ - renesas,scifa-r8a7742 # R8A7742 RZ/G1H
- renesas,scifa-r8a7743 # R8A7743 RZ/G1M
- renesas,scifa-r8a7744 # R8A7744 RZ/G1N
- renesas,scifa-r8a7745 # R8A7745 RZ/G1E
--
2.7.4
Enable recently added r8a7742 (RZ/G1H) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index f8e4535..e94699f 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -979,6 +979,7 @@ CONFIG_ARCH_R7S72100=y
CONFIG_ARCH_R7S9210=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7742=y
CONFIG_ARCH_R8A7743=y
CONFIG_ARCH_R8A7744=y
CONFIG_ARCH_R8A7745=y
--
2.7.4
On Wed, Apr 29, 2020 at 10:56:41PM +0100, Lad Prabhakar wrote:
> @@ -1701,6 +1709,7 @@ config DEBUG_UART_PHYS
> default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
> default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
> default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
> + default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2
Hi,
This is ordered by address. Please keep it so.
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up
Describe SYS-DMAC0/1 in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/boot/dts/r8a7742.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 4c7baf2..0febd74 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -448,6 +448,72 @@
/* placeholder */
};
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
avb: ethernet@e6800000 {
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
#address-cells = <1>;
--
2.7.4
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIF ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 70392b9..570b379 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -33,6 +33,7 @@ properties:
- items:
- enum:
+ - renesas,scif-r8a7742 # RZ/G1H
- renesas,scif-r8a7743 # RZ/G1M
- renesas,scif-r8a7744 # RZ/G1N
- renesas,scif-r8a7745 # RZ/G1E
--
2.7.4
RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible HSCIF ports,
so document the SoC specific bindings.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/serial/renesas,hscif.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
index 9110152..6b04c04 100644
--- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- enum:
+ - renesas,hscif-r8a7742 # RZ/G1H
- renesas,hscif-r8a7743 # RZ/G1M
- renesas,hscif-r8a7744 # RZ/G1N
- renesas,hscif-r8a7745 # RZ/G1E
--
2.7.4
Describe [H]SCIF{|A|B} ports in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/boot/dts/r8a7742.dtsi | 140 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 130 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 0febd74..5305214 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -522,53 +522,173 @@
};
scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c40000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
};
scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c50000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
};
scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
reg = <0 0xe6c60000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
};
scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7742",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6c20000 0 0x100>;
- /* placeholder */
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
};
scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7742",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6c30000 0 0x100>;
- /* placeholder */
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
};
scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7742",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
reg = <0 0xe6ce0000 0 0x100>;
- /* placeholder */
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
};
scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7742",
+ "renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
};
scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7742",
+ "renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e56000 {
+ compatible = "renesas,scif-r8a7742",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e56000 0 0x40>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
};
hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7742",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c0000 0 0x60>;
- /* placeholder */
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
};
hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7742",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c8000 0 0x60>;
- /* placeholder */
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
};
can0: can@e6e80000 {
--
2.7.4
Describe GPIO blocks in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/boot/dts/r8a7742.dtsi | 36 ++++++++++++++++++++++++++++++------
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 5305214..3901c63 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -249,66 +249,90 @@
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 32 30>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 64 30>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
#interrupt-cells = <2>;
interrupt-controller;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
};
pfc: pin-controller@e6060000 {
--
2.7.4
Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
family. Add support for its GPIO controllers.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 10dce84..11d18cc 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -3,6 +3,7 @@
Required Properties:
- compatible: should contain one or more of the following:
+ - "renesas,gpio-r8a7742": for R8A7742 (RZ/G1H) compatible GPIO controller.
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
- "renesas,gpio-r8a7744": for R8A7744 (RZ/G1N) compatible GPIO controller.
- "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
--
2.7.4
Hi,
Thank you for the review.
On Wed, Apr 29, 2020 at 11:00 PM Russell King - ARM Linux admin
<[email protected]> wrote:
>
> On Wed, Apr 29, 2020 at 10:56:41PM +0100, Lad Prabhakar wrote:
> > @@ -1701,6 +1709,7 @@ config DEBUG_UART_PHYS
> > default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
> > default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
> > default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
> > + default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2
>
> Hi,
>
> This is ordered by address. Please keep it so.
>
Sure will do that.
Cheers,
--Prabhakar
> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line in suburbia: sync at 10.2Mbps down 587kbps up
On Wed, Apr 29, 2020 at 11:57 PM Lad Prabhakar
<[email protected]> wrote:
> Add configuration option for the RZ/G1H (R8A77420) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:57 PM Lad Prabhakar
<[email protected]> wrote:
> Enable recently added r8a7742 (RZ/G1H) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:57 PM Lad Prabhakar
<[email protected]> wrote:
> Enable recently added r8a7742 (RZ/G1H) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Enable low-level debugging support for RZ/G1H (R8A7742). RZ/G1H uses
> SCIFA2 for the debug console.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Thanks for your patch!
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -976,6 +976,13 @@ choice
> Say Y here if you want kernel low-level debugging support
> via SCIF4 on Renesas RZ/G1E (R8A7745).
>
> + config DEBUG_RCAR_GEN2_SCIFA2
> + bool "Kernel low-level debugging messages via SCIFA2 on ARCH_R8A7742"
R8A7742 (without "ARCH_"-prefix)
I can fix that (and the sorting issue) while applying, so
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Document PFC support for the RZ/G1H (R8A7742) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in sh-pfc-for-v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
Thanks for your patch!
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790).
but lacks several automotive-specific peripherals.
So please split the pinmux groups and functions in common and automotive
parts. From a quick look, for now the latter is limited to MLB
groups/functions.
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
Thanks for your patch!
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Basic support for the RZ/G1H (R8A7742) SoC. Added placeholders
> for the peripherals supported by the SoC which will be filled up
> by incremental patches.
Please remove the placeholders, as there is nothing that depends on their
presence.
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7742.dtsi
> @@ -0,0 +1,715 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the r8a7742 SoC
> + *
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
> +#include <dt-bindings/power/r8a7742-sysc.h>
> +
> +/ {
> + compatible = "renesas,r8a7742";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + /*
> + * The external audio clocks are configured as 0 Hz fixed frequency
> + * clocks by default.
> + * Boards that provide audio clocks should override them.
> + */
> + audio_clk_a: audio_clk_a {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + audio_clk_b: audio_clk_b {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + audio_clk_c: audio_clk_c {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + /* External CAN clock */
> + can_clk: can {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board. */
> + clock-frequency = <0>;
> + };
Please drop the audio and CAN clocks for now, as they are not used.
> + /* External root clock */
> + extal_clk: extal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board. */
> + clock-frequency = <0>;
> + };
> +
> + /* External PCIe clock - can be overridden by the board */
> + pcie_bus_clk: pcie_bus {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
Please drop the PCI clock for now, as it is not used.
> +
> + /* External SCIF clock */
> + scif_clk: scif {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board. */
> + clock-frequency = <0>;
> + };
This should be used (see below).
> +
> + /* External USB clock - can be overridden by the board */
> + usb_extal_clk: usb_extal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> + };
> +
> + cpus {
Please sort nodes by unit-address (if present) per type, or alphabetically.
> + soc {
> + scifa2: serial@e6c60000 {
> + reg = <0 0xe6c60000 0 0x40>;
> + /* placeholder */
> + };
I prefer to see a real node for the serial console, so the system can at
least be boot tested to a console prompt.
Note that this requires adding a minimal board DTS, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Document SoC specific bindings for RZ/G1H (r8a7742) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
> Document RZ/G1H (also known as R8A7742) SoC bindings.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
> +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
This file has been replaced by renesas,rcar-dmac.yaml.
> @@ -16,6 +16,7 @@ Required Properties:
>
> - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
> Examples with soctypes are:
> + - "renesas,dmac-r8a7742" (RZ/G1H)
> - "renesas,dmac-r8a7743" (RZ/G1M)
> - "renesas,dmac-r8a7744" (RZ/G1N)
> - "renesas,dmac-r8a7745" (RZ/G1E)
For the logical change:
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Describe the IRQC interrupt controller in the r8a7742 device tree.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 2020-04-30 14:54, Geert Uytterhoeven wrote:
> On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
> <[email protected]> wrote:
>> Describe the IRQC interrupt controller in the r8a7742 device tree.
>>
>> Signed-off-by: Lad Prabhakar <[email protected]>
>> Reviewed-by: Marian-Cristian Rotariu
>> <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
Can I safely assume that the irqchip DT updates will be routed via
the arm-soc tree? If so, feel free to add my
Acked-by: Marc Zyngier <[email protected]>
to these patches.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIF ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Describe SYS-DMAC0/1 in the R8A7742 device tree.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible HSCIF ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFB ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Marc,
On Thu, Apr 30, 2020 at 4:01 PM Marc Zyngier <[email protected]> wrote:
> On 2020-04-30 14:54, Geert Uytterhoeven wrote:
> > On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
> > <[email protected]> wrote:
> >> Describe the IRQC interrupt controller in the r8a7742 device tree.
> >>
> >> Signed-off-by: Lad Prabhakar <[email protected]>
> >> Reviewed-by: Marian-Cristian Rotariu
> >> <[email protected]>
> >
> > Reviewed-by: Geert Uytterhoeven <[email protected]>
>
> Can I safely assume that the irqchip DT updates will be routed via
> the arm-soc tree? If so, feel free to add my
Yes they will, eventually.
> Acked-by: Marc Zyngier <[email protected]>
>
> to these patches.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
<[email protected]> wrote:
> Describe [H]SCIF{|A|B} ports in the R8A7742 device tree.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:59 PM Lad Prabhakar
<[email protected]> wrote:
> Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
> family. Add support for its GPIO controllers.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Apr 29, 2020 at 11:59 PM Lad Prabhakar
<[email protected]> wrote:
> Describe GPIO blocks in the R8A7742 device tree.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Thu, Apr 30, 2020 at 2:17 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
> <[email protected]> wrote:
> > Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790).
>
> but lacks several automotive-specific peripherals.
> So please split the pinmux groups and functions in common and automotive
> parts. From a quick look, for now the latter is limited to MLB
> groups/functions.
>
Yes I can confirm its just limited to MLBP, Ill split up into common
and automotive parts and send v2.
Cheers,
--Prabhakar
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
>
> The rest looks good to me.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Hi Geert,
Thank you for the review.
On Thu, Apr 30, 2020 at 2:49 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
> <[email protected]> wrote:
> > Basic support for the RZ/G1H (R8A7742) SoC. Added placeholders
> > for the peripherals supported by the SoC which will be filled up
> > by incremental patches.
>
> Please remove the placeholders, as there is nothing that depends on their
> presence.
>
Sure will drop that.
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7742.dtsi
> > @@ -0,0 +1,715 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the r8a7742 SoC
> > + *
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
> > +#include <dt-bindings/power/r8a7742-sysc.h>
> > +
> > +/ {
> > + compatible = "renesas,r8a7742";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + /*
> > + * The external audio clocks are configured as 0 Hz fixed frequency
> > + * clocks by default.
> > + * Boards that provide audio clocks should override them.
> > + */
> > + audio_clk_a: audio_clk_a {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <0>;
> > + };
> > +
> > + audio_clk_b: audio_clk_b {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <0>;
> > + };
> > +
> > + audio_clk_c: audio_clk_c {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <0>;
> > + };
> > +
> > + /* External CAN clock */
> > + can_clk: can {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
>
> Please drop the audio and CAN clocks for now, as they are not used.
>
OK.
> > + /* External root clock */
> > + extal_clk: extal {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
> > +
> > + /* External PCIe clock - can be overridden by the board */
> > + pcie_bus_clk: pcie_bus {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <0>;
> > + };
>
> Please drop the PCI clock for now, as it is not used.
>
OK
> > +
> > + /* External SCIF clock */
> > + scif_clk: scif {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
>
> This should be used (see below).
>
> > +
> > + /* External USB clock - can be overridden by the board */
> > + usb_extal_clk: usb_extal {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <48000000>;
> > + };
> > +
> > + cpus {
>
> Please sort nodes by unit-address (if present) per type, or alphabetically.
>
Sure will take care of it.
> > + soc {
>
> > + scifa2: serial@e6c60000 {
> > + reg = <0 0xe6c60000 0 0x40>;
> > + /* placeholder */
> > + };
>
> I prefer to see a real node for the serial console, so the system can at
> least be boot tested to a console prompt.
> Note that this requires adding a minimal board DTS, too.
>
OK so in that case Ill enable scifa2 and SDHI interface so it can be bootable.
Cheers,
--Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Hi Geert,
On Thu, Apr 30, 2020 at 2:03 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar
> <[email protected]> wrote:
> > Enable low-level debugging support for RZ/G1H (R8A7742). RZ/G1H uses
> > SCIFA2 for the debug console.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
>
> Thanks for your patch!
>
> > --- a/arch/arm/Kconfig.debug
> > +++ b/arch/arm/Kconfig.debug
> > @@ -976,6 +976,13 @@ choice
> > Say Y here if you want kernel low-level debugging support
> > via SCIF4 on Renesas RZ/G1E (R8A7745).
> >
> > + config DEBUG_RCAR_GEN2_SCIFA2
> > + bool "Kernel low-level debugging messages via SCIFA2 on ARCH_R8A7742"
>
> R8A7742 (without "ARCH_"-prefix)
>
> I can fix that (and the sorting issue) while applying, so
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> i.e. will queue in renesas-devel for v5.8.
>
Thank you for taking care of that.
Cheers,
--Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Hi Geert,
On Wed, Apr 29, 2020 at 10:57 PM Lad Prabhakar
<[email protected]> wrote:
>
> Hi All,
>
> This patch set adds initial board support for R8A7742 SoC,
> enabling R8A7742 arch in defconfigs with initial dtsi.
>
> Cheers,
> --Prabhakar
>
> Lad Prabhakar (18):
> soc: renesas: Add Renesas R8A7742 config option
> ARM: shmobile: defconfig: Enable r8a7742 SoC
> ARM: multi_v7_defconfig: Enable r8a7742 SoC
> ARM: debug-ll: Add support for r8a7742
> dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support
> pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support
> ARM: dts: r8a7742: Initial SoC device tree
> dt-bindings: irqchip: renesas-irqc: Document r8a7742 bindings
> ARM: dts: r8a7742: Add IRQC support
> dt-bindings: rcar-dmac: Document r8a7742 support
> ARM: dts: r8a7742: Add SYS-DMAC support
> dt-bindings: serial: renesas,scif: Document r8a7742 bindings
> dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
> dt-bindings: serial: renesas,scifb: Document r8a7742 bindings
> dt-bindings: serial: renesas,hscif: Document r8a7742 bindings
> ARM: dts: r8a7742: Add [H]SCIF{A|B} support
> dt-bindings: gpio: rcar: Add r8a7742 (RZ/G1H) support
> ARM: dts: r8a7742: Add GPIO support
>
Thank you for the review.
For v2 ill post patches from 6-18 fixing your review comments and
including the Acks, as patches 1-5 have been queued.
Cheers,
--Prabhakar
> .../devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
> .../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
> .../interrupt-controller/renesas,irqc.yaml | 1 +
> .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
> .../devicetree/bindings/serial/renesas,hscif.yaml | 1 +
> .../devicetree/bindings/serial/renesas,scif.yaml | 1 +
> .../devicetree/bindings/serial/renesas,scifa.yaml | 1 +
> .../devicetree/bindings/serial/renesas,scifb.yaml | 1 +
> arch/arm/Kconfig.debug | 10 +
> arch/arm/boot/dts/r8a7742.dtsi | 939 +++++++++++++++++++++
> arch/arm/configs/multi_v7_defconfig | 1 +
> arch/arm/configs/shmobile_defconfig | 1 +
> drivers/pinctrl/sh-pfc/Kconfig | 4 +
> drivers/pinctrl/sh-pfc/Makefile | 1 +
> drivers/pinctrl/sh-pfc/core.c | 6 +
> drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 24 +
> drivers/pinctrl/sh-pfc/sh_pfc.h | 1 +
> drivers/soc/renesas/Kconfig | 7 +
> 18 files changed, 1002 insertions(+)
> create mode 100644 arch/arm/boot/dts/r8a7742.dtsi
>
> --
> 2.7.4
>
On Wed, 29 Apr 2020 22:56:54 +0100, Lad Prabhakar wrote:
> Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
> family. Add support for its GPIO controllers.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
> ---
> Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
Hi Rob,
On Tue, May 12, 2020 at 4:53 PM Rob Herring <[email protected]> wrote:
> On Wed, 29 Apr 2020 22:56:54 +0100, Lad Prabhakar wrote:
> > Renesas RZ/G1H (R8A7742) SoC GPIO blocks are identical to the R-Car Gen2
> > family. Add support for its GPIO controllers.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
>
> Acked-by: Rob Herring <[email protected]>
Note that you've just applied 7f7d408e5a00d515 ("dt-bindings: gpio: rcar:
Convert to json-schema"), so this no longer applies.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds