This patch series aims to add support for Renesas RZ/G1H (r8a7742) SoC.
RZ/G1H SoC is similar to R-Car Gen2 H2 SoC.
This patch set is based on renesas-drivers/master-v5.7-rc1.
Lad Prabhakar (10):
dt-bindings: power: rcar-sysc: Document r8a7742 SYSC binding
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
soc: renesas: rcar-sysc: add R8A7742 support
dt-bindings: reset: rcar-rst: Document r8a7742 reset module
soc: renesas: rcar-rst: Add support for RZ/G1H
dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
clk: renesas: Add r8a7742 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add R8A7742 support
ARM: shmobile: r8a7742: Basic SoC support
cpufreq: dt: Add support for r8a7742
.../bindings/clock/renesas,cpg-mssr.yaml | 1 +
.../bindings/power/renesas,rcar-sysc.yaml | 1 +
.../devicetree/bindings/reset/renesas,rst.yaml | 1 +
arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 +
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7742-cpg-mssr.c | 289 +++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/soc/renesas/Kconfig | 4 +
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a7742-sysc.c | 42 +++
drivers/soc/renesas/rcar-rst.c | 1 +
drivers/soc/renesas/rcar-sysc.c | 3 +
drivers/soc/renesas/rcar-sysc.h | 1 +
include/dt-bindings/clock/r8a7742-cpg-mssr.h | 42 +++
include/dt-bindings/power/r8a7742-sysc.h | 29 +++
18 files changed, 431 insertions(+)
create mode 100644 drivers/clk/renesas/r8a7742-cpg-mssr.c
create mode 100644 drivers/soc/renesas/r8a7742-sysc.c
create mode 100644 include/dt-bindings/clock/r8a7742-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a7742-sysc.h
--
2.7.4
Add binding documentation for the RZ/G1H (R8A7742) SYSC block.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
index e59331e1..55b6ab2 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
@@ -17,6 +17,7 @@ description:
properties:
compatible:
enum:
+ - renesas,r8a7742-sysc # RZ/G1H
- renesas,r8a7743-sysc # RZ/G1M
- renesas,r8a7744-sysc # RZ/G1N
- renesas,r8a7745-sysc # RZ/G1E
--
2.7.4
Add support for RZ/G1H (R8A7742) SoC power areas to the R-Car SYSC driver.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
drivers/soc/renesas/Kconfig | 4 ++++
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a7742-sysc.c | 42 ++++++++++++++++++++++++++++++++++++++
drivers/soc/renesas/rcar-sysc.c | 3 +++
drivers/soc/renesas/rcar-sysc.h | 1 +
5 files changed, 51 insertions(+)
create mode 100644 drivers/soc/renesas/r8a7742-sysc.c
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 1982c7f..1eff82c 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -261,6 +261,10 @@ config ARCH_R8A77995
endif # ARM64
# SoC
+config SYSC_R8A7742
+ bool "RZ/G1H System Controller support" if COMPILE_TEST
+ select SYSC_RCAR
+
config SYSC_R8A7743
bool "RZ/G1M System Controller support" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index e595c3c..08296d7 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
# SoC
+obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
diff --git a/drivers/soc/renesas/r8a7742-sysc.c b/drivers/soc/renesas/r8a7742-sysc.c
new file mode 100644
index 0000000..219a675
--- /dev/null
+++ b/drivers/soc/renesas/r8a7742-sysc.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G1H System Controller
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a7742-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
+ { "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ { "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
+ PD_CPU_NOCR },
+ { "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
+ PD_CPU_NOCR },
+ { "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
+ PD_CPU_NOCR },
+ { "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
+ PD_CPU_NOCR },
+ { "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
+ PD_CPU_NOCR },
+ { "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
+ PD_CPU_NOCR },
+ { "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
+ PD_CPU_NOCR },
+ { "ca7-cpu3", 0x1c0, 3, R8A7742_PD_CA7_CPU3, R8A7742_PD_CA7_SCU,
+ PD_CPU_NOCR },
+ { "rgx", 0xc0, 0, R8A7742_PD_RGX, R8A7742_PD_ALWAYS_ON },
+};
+
+const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
+ .areas = r8a7742_areas,
+ .num_areas = ARRAY_SIZE(r8a7742_areas),
+};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index f0b291e..04ea87a 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -273,6 +273,9 @@ static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
}
static const struct of_device_id rcar_sysc_matches[] __initconst = {
+#ifdef CONFIG_SYSC_R8A7742
+ { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
+#endif
#ifdef CONFIG_SYSC_R8A7743
{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
/* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index 0fc3b11..e417f26 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -49,6 +49,7 @@ struct rcar_sysc_info {
u32 extmask_val; /* SYSCEXTMASK register mask value */
};
+extern const struct rcar_sysc_info r8a7742_sysc_info;
extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;
--
2.7.4
Document bindings for the RZ/G1H (R8A7742) reset module.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
index b5de1d1..4c2b429 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
@@ -23,6 +23,7 @@ description: |
properties:
compatible:
enum:
+ - renesas,r8a7742-rst # RZ/G1H
- renesas,r8a7743-rst # RZ/G1M
- renesas,r8a7744-rst # RZ/G1N
- renesas,r8a7745-rst # RZ/G1E
--
2.7.4
Add support for RZ/G1H (R8A7742) to the R-Car RST driver.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
drivers/soc/renesas/rcar-rst.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 2af2e0d..a2b2b17 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -39,6 +39,7 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
static const struct of_device_id rcar_rst_matches[] __initconst = {
/* RZ/G1 is handled like R-Car Gen2 */
+ { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
--
2.7.4
Add binding documentation for the RZ/G1H (R8A7742) Clock Pulse Generator
driver.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 9cd102e..c745bd6 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -25,6 +25,7 @@ properties:
compatible:
enum:
- renesas,r7s9210-cpg-mssr # RZ/A2
+ - renesas,r8a7742-cpg-mssr # RZ/G1H
- renesas,r8a7743-cpg-mssr # RZ/G1M
- renesas,r8a7744-cpg-mssr # RZ/G1N
- renesas,r8a7745-cpg-mssr # RZ/G1E
--
2.7.4
Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
include/dt-bindings/clock/r8a7742-cpg-mssr.h | 42 ++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7742-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a7742-cpg-mssr.h b/include/dt-bindings/clock/r8a7742-cpg-mssr.h
new file mode 100644
index 0000000..e68191c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7742-cpg-mssr.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7742 CPG Core Clocks */
+#define R8A7742_CLK_Z 0
+#define R8A7742_CLK_Z2 1
+#define R8A7742_CLK_ZG 2
+#define R8A7742_CLK_ZTR 3
+#define R8A7742_CLK_ZTRD2 4
+#define R8A7742_CLK_ZT 5
+#define R8A7742_CLK_ZX 6
+#define R8A7742_CLK_ZS 7
+#define R8A7742_CLK_HP 8
+#define R8A7742_CLK_B 9
+#define R8A7742_CLK_LB 10
+#define R8A7742_CLK_P 11
+#define R8A7742_CLK_CL 12
+#define R8A7742_CLK_M2 13
+#define R8A7742_CLK_ZB3 14
+#define R8A7742_CLK_ZB3D2 15
+#define R8A7742_CLK_DDR 16
+#define R8A7742_CLK_SDH 17
+#define R8A7742_CLK_SD0 18
+#define R8A7742_CLK_SD1 19
+#define R8A7742_CLK_SD2 20
+#define R8A7742_CLK_SD3 21
+#define R8A7742_CLK_MMC0 22
+#define R8A7742_CLK_MMC1 23
+#define R8A7742_CLK_MP 24
+#define R8A7742_CLK_QSPI 25
+#define R8A7742_CLK_CP 26
+#define R8A7742_CLK_RCAN 27
+#define R8A7742_CLK_R 28
+#define R8A7742_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
--
2.7.4
Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7742-cpg-mssr.c | 289 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 302 insertions(+)
create mode 100644 drivers/clk/renesas/r8a7742-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ac2dd92..149787b 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -8,6 +8,7 @@ config CLK_RENESAS
select CLK_R7S9210 if ARCH_R7S9210
select CLK_R8A73A4 if ARCH_R8A73A4
select CLK_R8A7740 if ARCH_R8A7740
+ select CLK_R8A7742 if ARCH_R8A7742
select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
select CLK_R8A7745 if ARCH_R8A7745
select CLK_R8A77470 if ARCH_R8A77470
@@ -55,6 +56,10 @@ config CLK_R8A7740
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
+config CLK_R8A7742
+ bool "RZ/G1H clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN2_CPG
+
config CLK_R8A7743
bool "RZ/G1M clock support" if COMPILE_TEST
select CLK_RCAR_GEN2_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 4a722bc..a4066f9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_CLK_RZA1) += clk-rz.o
obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
+obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a7742-cpg-mssr.c b/drivers/clk/renesas/r8a7742-cpg-mssr.c
new file mode 100644
index 0000000..2cae2cb
--- /dev/null
+++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a7742 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7742_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static struct cpg_core_clk r8a7742_core_clks[] __initdata = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
+ DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
+ DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1),
+ DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
+ DEF_FIXED("zt", R8A7742_CLK_ZT, CLK_PLL1, 5, 1),
+ DEF_FIXED("ztr", R8A7742_CLK_ZTR, CLK_PLL1, 4, 1),
+ DEF_FIXED("ztrd2", R8A7742_CLK_ZTRD2, CLK_PLL1, 12, 1),
+ DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("lb", R8A7742_CLK_LB, CLK_PLL1, 24, 1),
+ DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+ DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
+};
+
+static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
+ DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
+ DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
+ DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
+ DEF_MOD("tmu1", 111, R8A7742_CLK_P),
+ DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
+ DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
+ DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7742_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7742_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7742_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7742_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7742_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7742_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7742_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7742_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7742_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7742_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
+ DEF_MOD("msiof3", 215, R8A7742_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7742_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS),
+ DEF_MOD("iic2", 300, R8A7742_CLK_CP),
+ DEF_MOD("tpu0", 304, R8A7742_CLK_CP),
+ DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1),
+ DEF_MOD("scif2", 310, R8A7742_CLK_CP),
+ DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2),
+ DEF_MOD("sdhi1", 313, R8A7742_CLK_SD2),
+ DEF_MOD("sdhi0", 314, R8A7742_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7742_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7742_CLK_HP),
+ DEF_MOD("pciec", 319, R8A7742_CLK_MP),
+ DEF_MOD("iic1", 323, R8A7742_CLK_HP),
+ DEF_MOD("usb3.0", 328, R8A7742_CLK_MP),
+ DEF_MOD("cmt1", 329, R8A7742_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7742_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7742_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7742_CLK_R),
+ DEF_MOD("irqc", 407, R8A7742_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7742_CLK_ZS),
+ DEF_MOD("audio-dmac1", 501, R8A7742_CLK_HP),
+ DEF_MOD("audio-dmac0", 502, R8A7742_CLK_HP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7742_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7742_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7742_CLK_HP),
+ DEF_MOD("hscif1", 716, R8A7742_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7742_CLK_ZS),
+ DEF_MOD("scif1", 720, R8A7742_CLK_P),
+ DEF_MOD("scif0", 721, R8A7742_CLK_P),
+ DEF_MOD("du2", 722, R8A7742_CLK_ZX),
+ DEF_MOD("du1", 723, R8A7742_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7742_CLK_ZX),
+ DEF_MOD("lvds1", 725, R8A7742_CLK_ZX),
+ DEF_MOD("lvds0", 726, R8A7742_CLK_ZX),
+ DEF_MOD("r-gp2d", 807, R8A7742_CLK_ZX),
+ DEF_MOD("vin3", 808, R8A7742_CLK_ZG),
+ DEF_MOD("vin2", 809, R8A7742_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7742_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7742_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7742_CLK_HP),
+ DEF_MOD("ether", 813, R8A7742_CLK_P),
+ DEF_MOD("sata1", 814, R8A7742_CLK_ZS),
+ DEF_MOD("sata0", 815, R8A7742_CLK_ZS),
+ DEF_MOD("imr-x2-1", 820, R8A7742_CLK_ZG),
+ DEF_MOD("imr-x2-0", 821, R8A7742_CLK_HP),
+ DEF_MOD("imr-lsx2-1", 822, R8A7742_CLK_P),
+ DEF_MOD("imr-lsx2-0", 823, R8A7742_CLK_ZS),
+ DEF_MOD("gpio5", 907, R8A7742_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7742_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7742_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7742_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7742_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7742_CLK_CP),
+ DEF_MOD("can1", 915, R8A7742_CLK_P),
+ DEF_MOD("can0", 916, R8A7742_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7742_CLK_QSPI),
+ DEF_MOD("iicdvfs", 926, R8A7742_CLK_CP),
+ DEF_MOD("i2c3", 928, R8A7742_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7742_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7742_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7742_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7742_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7742_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a7742_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(402), /* RWDT */
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *1
+ *---------------------------------------------------
+ * 0 0 0 15 x172/2 x208/2 x106
+ * 0 0 1 15 x172/2 x208/2 x88
+ * 0 1 0 20 x130/2 x156/2 x80
+ * 0 1 1 20 x130/2 x156/2 x66
+ * 1 0 0 26 / 2 x200/2 x240/2 x122
+ * 1 0 1 26 / 2 x200/2 x240/2 x102
+ * 1 1 0 30 / 2 x172/2 x208/2 x106
+ * 1 1 1 30 / 2 x172/2 x208/2 x88
+ *
+ * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ /* EXTAL div PLL1 mult PLL3 mult */
+ { 1, 208, 106, },
+ { 1, 208, 88, },
+ { 1, 156, 80, },
+ { 1, 156, 66, },
+ { 2, 240, 122, },
+ { 2, 240, 102, },
+ { 2, 208, 106, },
+ { 2, 208, 88, },
+};
+
+static int __init r8a7742_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+ struct device_node *np = dev->of_node;
+ unsigned int i;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ if (of_device_is_compatible(np, "renesas,r8a7742-cpg-mssr")) {
+ /* RZ/G1H uses a 1/3 divider for ZG */
+ for (i = 0; i < ARRAY_SIZE(r8a7742_core_clks); i++)
+ if (r8a7742_core_clks[i].id == R8A7742_CLK_ZG) {
+ r8a7742_core_clks[i].div = 3;
+ break;
+ }
+ }
+ return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a7742_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a7742_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a7742_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a7742_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a7742_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a7742_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a7742_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a7742_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index a2663fb..8f6dff3 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -673,6 +673,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r7s9210_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A7742
+ {
+ .compatible = "renesas,r8a7742-cpg-mssr",
+ .data = &r8a7742_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A7743
{
.compatible = "renesas,r8a7743-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 3b852ba..55a18ef 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -155,6 +155,7 @@ struct cpg_mssr_info {
};
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
--
2.7.4
Add minimal support for the RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 1ee5cd2..c42ff8c 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -24,6 +24,7 @@
#include "rcar-gen2.h"
static const struct of_device_id cpg_matches[] __initconst = {
+ { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
@@ -209,6 +210,7 @@ DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
+ "renesas,r8a7742",
"renesas,r8a7743",
"renesas,r8a7744",
"renesas,r8a7745",
--
2.7.4
Add the compatible strings for supporting the generic cpufreq driver on
the Renesas RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index cb9db16..148aa66 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -53,6 +53,7 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "renesas,r7s72100", },
{ .compatible = "renesas,r8a73a4", },
{ .compatible = "renesas,r8a7740", },
+ { .compatible = "renesas,r8a7742", },
{ .compatible = "renesas,r8a7743", },
{ .compatible = "renesas,r8a7744", },
{ .compatible = "renesas,r8a7745", },
--
2.7.4
Add power domain indices for RZ/G1H (R8A7742) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
---
include/dt-bindings/power/r8a7742-sysc.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 include/dt-bindings/power/r8a7742-sysc.h
diff --git a/include/dt-bindings/power/r8a7742-sysc.h b/include/dt-bindings/power/r8a7742-sysc.h
new file mode 100644
index 0000000..1b1bd3c
--- /dev/null
+++ b/include/dt-bindings/power/r8a7742-sysc.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7742_PD_CA15_CPU0 0
+#define R8A7742_PD_CA15_CPU1 1
+#define R8A7742_PD_CA15_CPU2 2
+#define R8A7742_PD_CA15_CPU3 3
+#define R8A7742_PD_CA7_CPU0 5
+#define R8A7742_PD_CA7_CPU1 6
+#define R8A7742_PD_CA7_CPU2 7
+#define R8A7742_PD_CA7_CPU3 8
+#define R8A7742_PD_CA15_SCU 12
+#define R8A7742_PD_RGX 20
+#define R8A7742_PD_CA7_SCU 21
+
+/* Always-on power area */
+#define R8A7742_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */
--
2.7.4
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add binding documentation for the RZ/G1H (R8A7742) SYSC block.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
>
> Add power domain indices for RZ/G1H (R8A7742) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add support for RZ/G1H (R8A7742) SoC power areas to the R-Car SYSC driver.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Document bindings for the RZ/G1H (R8A7742) reset module.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add support for RZ/G1H (R8A7742) to the R-Car RST driver.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add binding documentation for the RZ/G1H (R8A7742) Clock Pulse Generator
> driver.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in clk-renesas-for-v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
> Manual.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in clk-renesas-for-v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
> +static struct cpg_core_clk r8a7742_core_clks[] __initdata = {
> + /* External Clock Inputs */
> + DEF_INPUT("extal", CLK_EXTAL),
> + DEF_INPUT("usb_extal", CLK_USB_EXTAL),
> +
> + /* Internal Core Clocks */
> + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
> + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
> + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
> + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
> +
> + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> +
> + /* Core Clock Outputs */
> + DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
> + DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
> + DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
> + DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
> + DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
> + DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
> +
> + DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1),
> + DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
> + DEF_FIXED("zt", R8A7742_CLK_ZT, CLK_PLL1, 5, 1),
> + DEF_FIXED("ztr", R8A7742_CLK_ZTR, CLK_PLL1, 4, 1),
> + DEF_FIXED("ztrd2", R8A7742_CLK_ZTRD2, CLK_PLL1, 12, 1),
The ZT* clocks are not fixed-factor clocks, but use programmable
dividers in FRQCRB.
So either you implement them correctly, or you drop them, like we did
for the other R-Car Gen2 and RZ/G1 SoCs (there are no users yet).
> + DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1),
> + DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1),
> + DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1),
> + DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1),
> + DEF_FIXED("lb", R8A7742_CLK_LB, CLK_PLL1, 24, 1),
Please use CLK_TYPE_GEN2_LB, as the LB divider depends on the state of
mode pin MD18.
> + DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1),
> + DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1),
> + DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1),
> + DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1),
> + DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1),
> + DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1),
> + DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1),
> + DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1),
> + DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1),
> + DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1),
> +
> + DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078),
> + DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
> + DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
> + DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
> +};
> +
> +static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
> + DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
> + DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
> + DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
> + DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
> + DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
> + DEF_MOD("tmu1", 111, R8A7742_CLK_P),
> + DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
> + DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
> + DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
> + DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
> + DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS),
> + DEF_MOD("tmu3", 121, R8A7742_CLK_P),
> + DEF_MOD("tmu2", 122, R8A7742_CLK_P),
> + DEF_MOD("cmt0", 124, R8A7742_CLK_R),
> + DEF_MOD("tmu0", 125, R8A7742_CLK_CP),
> + DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS),
> + DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS),
> + DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS),
> + DEF_MOD("scifa2", 202, R8A7742_CLK_MP),
> + DEF_MOD("scifa1", 203, R8A7742_CLK_MP),
> + DEF_MOD("scifa0", 204, R8A7742_CLK_MP),
> + DEF_MOD("msiof2", 205, R8A7742_CLK_MP),
> + DEF_MOD("scifb0", 206, R8A7742_CLK_MP),
> + DEF_MOD("scifb1", 207, R8A7742_CLK_MP),
> + DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
> + DEF_MOD("msiof3", 215, R8A7742_CLK_MP),
> + DEF_MOD("scifb2", 216, R8A7742_CLK_MP),
> + DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS),
> + DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS),
> + DEF_MOD("iic2", 300, R8A7742_CLK_CP),
Parent should be R8A7742_CLK_HP.
> + DEF_MOD("tpu0", 304, R8A7742_CLK_CP),
> + DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1),
> + DEF_MOD("scif2", 310, R8A7742_CLK_CP),
Parent should be R8A7742_CLK_P.
> + DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3),
> + DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2),
> + DEF_MOD("sdhi1", 313, R8A7742_CLK_SD2),
Parent should be R8A7742_CLK_SD1.
> +static int __init r8a7742_cpg_mssr_init(struct device *dev)
> +{
> + const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
> + struct device_node *np = dev->of_node;
> + unsigned int i;
> + u32 cpg_mode;
> + int error;
> +
> + error = rcar_rst_read_mode_pins(&cpg_mode);
> + if (error)
> + return error;
> +
> + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
> +
> + if (of_device_is_compatible(np, "renesas,r8a7742-cpg-mssr")) {
> + /* RZ/G1H uses a 1/3 divider for ZG */
> + for (i = 0; i < ARRAY_SIZE(r8a7742_core_clks); i++)
> + if (r8a7742_core_clks[i].id == R8A7742_CLK_ZG) {
> + r8a7742_core_clks[i].div = 3;
> + break;
> + }
> + }
Do you really need this part? (copied from r8a7743-cpg-mssr.c ;-)
If you remove it, r8a7742_core_clks[] can be const, and <linux/of.h> is
no longer needed,
> + return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
> +}
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add minimal support for the RZ/G1H (R8A7742) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
This patch should be merged through Viresh's cpufreq tree (CCed).
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> Add the compatible strings for supporting the generic cpufreq driver on
> the Renesas RZ/G1H (R8A7742) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -53,6 +53,7 @@ static const struct of_device_id whitelist[] __initconst = {
> { .compatible = "renesas,r7s72100", },
> { .compatible = "renesas,r8a73a4", },
> { .compatible = "renesas,r8a7740", },
> + { .compatible = "renesas,r8a7742", },
> { .compatible = "renesas,r8a7743", },
> { .compatible = "renesas,r8a7744", },
> { .compatible = "renesas,r8a7745", },
> --
> 2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 27-04-20, 11:22, Geert Uytterhoeven wrote:
> Hi Prabhakar,
>
> This patch should be merged through Viresh's cpufreq tree (CCed).
>
> On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> <[email protected]> wrote:
> > Add the compatible strings for supporting the generic cpufreq driver on
> > the Renesas RZ/G1H (R8A7742) SoC.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
Prabhakar,
Please resend the patch with all dependencies to me so I can apply it.
--
viresh
Hi Prabhakar,
On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
<[email protected]> wrote:
> This patch series aims to add support for Renesas RZ/G1H (r8a7742) SoC.
>
> RZ/G1H SoC is similar to R-Car Gen2 H2 SoC.
>
> This patch set is based on renesas-drivers/master-v5.7-rc1.
Thanks for your series!
Looks mostly OK to me.
The missing code part seems to be the introduction of the main
CONFIG_ARCH_R8A7742 symbol?
I assume you plan to submit the DTS for v5.8, too, so I'll have to be
careful and apply the binding definitions to a separate shared branch?
Thanks again!
> Lad Prabhakar (10):
> dt-bindings: power: rcar-sysc: Document r8a7742 SYSC binding
> dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
> soc: renesas: rcar-sysc: add R8A7742 support
> dt-bindings: reset: rcar-rst: Document r8a7742 reset module
> soc: renesas: rcar-rst: Add support for RZ/G1H
> dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
> clk: renesas: Add r8a7742 CPG Core Clock Definitions
> clk: renesas: cpg-mssr: Add R8A7742 support
> ARM: shmobile: r8a7742: Basic SoC support
> cpufreq: dt: Add support for r8a7742
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Mon, Apr 27, 2020 at 10:10 AM Geert Uytterhoeven
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> <[email protected]> wrote:
> > Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
> > Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> > (and RZ/G) code.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
>
> > +static struct cpg_core_clk r8a7742_core_clks[] __initdata = {
> > + /* External Clock Inputs */
> > + DEF_INPUT("extal", CLK_EXTAL),
> > + DEF_INPUT("usb_extal", CLK_USB_EXTAL),
> > +
> > + /* Internal Core Clocks */
> > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
> > + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
> > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
> > + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
> > +
> > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> > +
> > + /* Core Clock Outputs */
> > + DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
> > + DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
> > + DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
> > + DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
> > + DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
> > + DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
> > +
> > + DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1),
> > + DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
> > + DEF_FIXED("zt", R8A7742_CLK_ZT, CLK_PLL1, 5, 1),
> > + DEF_FIXED("ztr", R8A7742_CLK_ZTR, CLK_PLL1, 4, 1),
> > + DEF_FIXED("ztrd2", R8A7742_CLK_ZTRD2, CLK_PLL1, 12, 1),
>
> The ZT* clocks are not fixed-factor clocks, but use programmable
> dividers in FRQCRB.
> So either you implement them correctly, or you drop them, like we did
> for the other R-Car Gen2 and RZ/G1 SoCs (there are no users yet).
>
Since there are no users yet Ill drop them for now.
> > + DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1),
> > + DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1),
> > + DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1),
> > + DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1),
> > + DEF_FIXED("lb", R8A7742_CLK_LB, CLK_PLL1, 24, 1),
>
> Please use CLK_TYPE_GEN2_LB, as the LB divider depends on the state of
> mode pin MD18.
>
Agreed and looking further into it this needs to be a base clock I
shall replace this to:
DEF_BASE("lb", R8A7742_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
> > + DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1),
> > + DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1),
> > + DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1),
> > + DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1),
> > + DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1),
> > + DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1),
> > + DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1),
> > + DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1),
> > + DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1),
> > + DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1),
> > +
> > + DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078),
> > + DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
> > + DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
> > + DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
> > +};
> > +
> > +static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
> > + DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
> > + DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
> > + DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
> > + DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
> > + DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
> > + DEF_MOD("tmu1", 111, R8A7742_CLK_P),
> > + DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
> > + DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
> > + DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
> > + DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
> > + DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS),
> > + DEF_MOD("tmu3", 121, R8A7742_CLK_P),
> > + DEF_MOD("tmu2", 122, R8A7742_CLK_P),
> > + DEF_MOD("cmt0", 124, R8A7742_CLK_R),
> > + DEF_MOD("tmu0", 125, R8A7742_CLK_CP),
> > + DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS),
> > + DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS),
> > + DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS),
> > + DEF_MOD("scifa2", 202, R8A7742_CLK_MP),
> > + DEF_MOD("scifa1", 203, R8A7742_CLK_MP),
> > + DEF_MOD("scifa0", 204, R8A7742_CLK_MP),
> > + DEF_MOD("msiof2", 205, R8A7742_CLK_MP),
> > + DEF_MOD("scifb0", 206, R8A7742_CLK_MP),
> > + DEF_MOD("scifb1", 207, R8A7742_CLK_MP),
> > + DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
> > + DEF_MOD("msiof3", 215, R8A7742_CLK_MP),
> > + DEF_MOD("scifb2", 216, R8A7742_CLK_MP),
> > + DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS),
> > + DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS),
> > + DEF_MOD("iic2", 300, R8A7742_CLK_CP),
>
> Parent should be R8A7742_CLK_HP.
>
Agreed shall fix it.
> > + DEF_MOD("tpu0", 304, R8A7742_CLK_CP),
> > + DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1),
> > + DEF_MOD("scif2", 310, R8A7742_CLK_CP),
>
> Parent should be R8A7742_CLK_P.
>
Agreed shall fix it.
> > + DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3),
> > + DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2),
> > + DEF_MOD("sdhi1", 313, R8A7742_CLK_SD2),
>
> Parent should be R8A7742_CLK_SD1.
>
Agreed shall fix it.
> > +static int __init r8a7742_cpg_mssr_init(struct device *dev)
> > +{
> > + const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
> > + struct device_node *np = dev->of_node;
> > + unsigned int i;
> > + u32 cpg_mode;
> > + int error;
> > +
> > + error = rcar_rst_read_mode_pins(&cpg_mode);
> > + if (error)
> > + return error;
> > +
> > + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
> > +
> > + if (of_device_is_compatible(np, "renesas,r8a7742-cpg-mssr")) {
> > + /* RZ/G1H uses a 1/3 divider for ZG */
> > + for (i = 0; i < ARRAY_SIZE(r8a7742_core_clks); i++)
> > + if (r8a7742_core_clks[i].id == R8A7742_CLK_ZG) {
> > + r8a7742_core_clks[i].div = 3;
> > + break;
> > + }
> > + }
>
> Do you really need this part? (copied from r8a7743-cpg-mssr.c ;-)
> If you remove it, r8a7742_core_clks[] can be const, and <linux/of.h> is
> no longer needed,
>
I haven't come far enough to test the GPU yet, so Ill drop this for
now and add this later if needed.
Cheers,
--Prabhakar
> > + return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
> > +}
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Hi Prabhakar,
On Mon, Apr 27, 2020 at 12:07 PM Lad, Prabhakar
<[email protected]> wrote:
> On Mon, Apr 27, 2020 at 10:10 AM Geert Uytterhoeven
> <[email protected]> wrote:
> > On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> > <[email protected]> wrote:
> > > Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
> > > Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> > > (and RZ/G) code.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c
> >
> > > +static struct cpg_core_clk r8a7742_core_clks[] __initdata = {
> > > + DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
> > > +static int __init r8a7742_cpg_mssr_init(struct device *dev)
> > > +{
> > > + const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
> > > + struct device_node *np = dev->of_node;
> > > + unsigned int i;
> > > + u32 cpg_mode;
> > > + int error;
> > > +
> > > + error = rcar_rst_read_mode_pins(&cpg_mode);
> > > + if (error)
> > > + return error;
> > > +
> > > + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
> > > +
> > > + if (of_device_is_compatible(np, "renesas,r8a7742-cpg-mssr")) {
> > > + /* RZ/G1H uses a 1/3 divider for ZG */
> > > + for (i = 0; i < ARRAY_SIZE(r8a7742_core_clks); i++)
> > > + if (r8a7742_core_clks[i].id == R8A7742_CLK_ZG) {
> > > + r8a7742_core_clks[i].div = 3;
> > > + break;
> > > + }
> > > + }
> >
> > Do you really need this part? (copied from r8a7743-cpg-mssr.c ;-)
> > If you remove it, r8a7742_core_clks[] can be const, and <linux/of.h> is
> > no longer needed,
> >
> I haven't come far enough to test the GPU yet, so Ill drop this for
> now and add this later if needed.
The divider is already set to 3 in the table above.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Viresh,
On Mon, Apr 27, 2020 at 10:24 AM Viresh Kumar <[email protected]> wrote:
>
> On 27-04-20, 11:22, Geert Uytterhoeven wrote:
> > Hi Prabhakar,
> >
> > This patch should be merged through Viresh's cpufreq tree (CCed).
> >
> > On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> > <[email protected]> wrote:
> > > Add the compatible strings for supporting the generic cpufreq driver on
> > > the Renesas RZ/G1H (R8A7742) SoC.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
> >
> > Reviewed-by: Geert Uytterhoeven <[email protected]>
>
> Prabhakar,
>
> Please resend the patch with all dependencies to me so I can apply it.
>
This is the only patch which is needed for R8A7742 SoC which needs to
be applied for drivers/cpufreq. Shall I still repost it or you are
happy to pick this one up ?
Cheers,
--Prabhakar
> --
> viresh
On 27-04-20, 11:20, Lad, Prabhakar wrote:
> Hi Viresh,
>
> On Mon, Apr 27, 2020 at 10:24 AM Viresh Kumar <[email protected]> wrote:
> >
> > On 27-04-20, 11:22, Geert Uytterhoeven wrote:
> > > Hi Prabhakar,
> > >
> > > This patch should be merged through Viresh's cpufreq tree (CCed).
> > >
> > > On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> > > <[email protected]> wrote:
> > > > Add the compatible strings for supporting the generic cpufreq driver on
> > > > the Renesas RZ/G1H (R8A7742) SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
> > >
> > > Reviewed-by: Geert Uytterhoeven <[email protected]>
> >
> > Prabhakar,
> >
> > Please resend the patch with all dependencies to me so I can apply it.
> >
> This is the only patch which is needed for R8A7742 SoC which needs to
> be applied for drivers/cpufreq. Shall I still repost it or you are
> happy to pick this one up ?
would be easier for me if you repost it. I don't have it in my
mailbox.
--
viresh
Hi Geert,
On Mon, Apr 27, 2020 at 10:28 AM Geert Uytterhoeven
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> <[email protected]> wrote:
> > This patch series aims to add support for Renesas RZ/G1H (r8a7742) SoC.
> >
> > RZ/G1H SoC is similar to R-Car Gen2 H2 SoC.
> >
> > This patch set is based on renesas-drivers/master-v5.7-rc1.
>
> Thanks for your series!
>
> Looks mostly OK to me.
Thank you for the review. After fixing patch 8/10 shall I just post a
v2 with a single patch or the entire series ?
> The missing code part seems to be the introduction of the main
> CONFIG_ARCH_R8A7742 symbol?
>
I was planning to post them once these patches were reviewed, just
didn't wanted to flood with too many patches.
for enabling r8a7742 SoC in multi_v7_defconfig should this be only
sent out wen its accepted in shmobile_defconfig or can it be part of
same series as below ?
05ba50a4cf99 ARM: multi_v7_defconfig: Enable r8a7742 SoC
99b69d08729a ARM: shmobile: defconfig: Enable r8a7742 SoC
6b7bcd6635c7 ARM: debug-ll: Add support for r8a7742
1cf4e52e3a0e soc: renesas: Add Renesas R8A7742 config option
> I assume you plan to submit the DTS for v5.8, too, so I'll have to be
> careful and apply the binding definitions to a separate shared branch?
>
Yes I do plan to submit the DTS changes for v5.8.
Cheers,
--Prabhakar
> Thanks again!
>
> > Lad Prabhakar (10):
> > dt-bindings: power: rcar-sysc: Document r8a7742 SYSC binding
> > dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
> > soc: renesas: rcar-sysc: add R8A7742 support
> > dt-bindings: reset: rcar-rst: Document r8a7742 reset module
> > soc: renesas: rcar-rst: Add support for RZ/G1H
> > dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
> > clk: renesas: Add r8a7742 CPG Core Clock Definitions
> > clk: renesas: cpg-mssr: Add R8A7742 support
> > ARM: shmobile: r8a7742: Basic SoC support
> > cpufreq: dt: Add support for r8a7742
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
On Mon, Apr 27, 2020 at 11:22 AM Viresh Kumar <[email protected]> wrote:
>
> On 27-04-20, 11:20, Lad, Prabhakar wrote:
> > Hi Viresh,
> >
> > On Mon, Apr 27, 2020 at 10:24 AM Viresh Kumar <[email protected]> wrote:
> > >
> > > On 27-04-20, 11:22, Geert Uytterhoeven wrote:
> > > > Hi Prabhakar,
> > > >
> > > > This patch should be merged through Viresh's cpufreq tree (CCed).
> > > >
> > > > On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> > > > <[email protected]> wrote:
> > > > > Add the compatible strings for supporting the generic cpufreq driver on
> > > > > the Renesas RZ/G1H (R8A7742) SoC.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > > > Reviewed-by: Marian-Cristian Rotariu <[email protected]>
> > > >
> > > > Reviewed-by: Geert Uytterhoeven <[email protected]>
> > >
> > > Prabhakar,
> > >
> > > Please resend the patch with all dependencies to me so I can apply it.
> > >
> > This is the only patch which is needed for R8A7742 SoC which needs to
> > be applied for drivers/cpufreq. Shall I still repost it or you are
> > happy to pick this one up ?
>
> would be easier for me if you repost it. I don't have it in my
> mailbox.
>
Sure will post that in a bit.
Cheers,
--Prabhakar
> --
> viresh
Hi Prabhakar,
On Mon, Apr 27, 2020 at 12:31 PM Lad, Prabhakar
<[email protected]> wrote:
> On Mon, Apr 27, 2020 at 10:28 AM Geert Uytterhoeven
> <[email protected]> wrote:
> > On Thu, Apr 23, 2020 at 11:41 PM Lad Prabhakar
> > <[email protected]> wrote:
> > > This patch series aims to add support for Renesas RZ/G1H (r8a7742) SoC.
> > >
> > > RZ/G1H SoC is similar to R-Car Gen2 H2 SoC.
> > >
> > > This patch set is based on renesas-drivers/master-v5.7-rc1.
> >
> > Thanks for your series!
> >
> > Looks mostly OK to me.
> Thank you for the review. After fixing patch 8/10 shall I just post a
> v2 with a single patch or the entire series ?
A single v2 patch is fine. The clock driver goes in through a different
tree anyway/
> > The missing code part seems to be the introduction of the main
> > CONFIG_ARCH_R8A7742 symbol?
> >
> I was planning to post them once these patches were reviewed, just
> didn't wanted to flood with too many patches.
>
> for enabling r8a7742 SoC in multi_v7_defconfig should this be only
> sent out wen its accepted in shmobile_defconfig or can it be part of
> same series as below ?
>
> 05ba50a4cf99 ARM: multi_v7_defconfig: Enable r8a7742 SoC
> 99b69d08729a ARM: shmobile: defconfig: Enable r8a7742 SoC
> 6b7bcd6635c7 ARM: debug-ll: Add support for r8a7742
> 1cf4e52e3a0e soc: renesas: Add Renesas R8A7742 config option
It can be part of the same series.
> > I assume you plan to submit the DTS for v5.8, too, so I'll have to be
> > careful and apply the binding definitions to a separate shared branch?
> >
> Yes I do plan to submit the DTS changes for v5.8.
Thanks. Looking forward to it!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds