This patch set extends support of new IPROC PCIe host controller features
- Add CRS check using controller register status flags
- Add outbound window mapping configuration for 32-bit I/O region
This patch set is based on Linux-5.0-rc2.
Changes from v2:
- Based on Lorenzo Pieralisi comments, commit logs are expanded.
Changes from v1:
- Addressed Bjorn Helgaas comments.
- Removed set order mode patch from patchset.
Srinath Mannam (2):
PCI: iproc: Add CRS check in config read
PCI: iproc: Add outbound configuration for 32-bit I/O region
drivers/pci/controller/pcie-iproc.c | 44 +++++++++++++++++++++++++++++++++----
1 file changed, 40 insertions(+), 4 deletions(-)
--
2.7.4
In the present driver outbound window configuration is done to map above
32-bit address I/O regions with corresponding PCI memory range given in
ranges DT property.
This patch add outbound window configuration to map below 32-bit I/O range
with corresponding PCI memory, which helps to access I/O region in IA32
and one to one mapping of I/O region to PCI memory.
Ex:
1. ranges DT property given for current driver is,
ranges = <0x83000000 0x0 0x40000000 0x4 0x00000000 0 0x40000000>;
I/O region address is 0x400000000
2. ranges DT property can be given after this patch,
ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>;
I/O region address is 0x42000000
Signed-off-by: Srinath Mannam <[email protected]>
Signed-off-by: Abhishek Shah <[email protected]>
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
Reviewed-by: Vikram Prakash <[email protected]>
---
drivers/pci/controller/pcie-iproc.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
index b882255..080f142 100644
--- a/drivers/pci/controller/pcie-iproc.c
+++ b/drivers/pci/controller/pcie-iproc.c
@@ -955,8 +955,25 @@ static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
resource_size_t window_size =
ob_map->window_sizes[size_idx] * SZ_1M;
- if (size < window_size)
- continue;
+ /*
+ * Keep iterating until we reach the last window and
+ * with the minimal window size at index zero. In this
+ * case, we take a compromise by mapping it using the
+ * minimum window size that can be supported
+ */
+ if (size < window_size) {
+ if (size_idx > 0 || window_idx > 0)
+ continue;
+
+ /*
+ * For the corner case of reaching the minimal
+ * window size that can be supported on the
+ * last window
+ */
+ axi_addr = ALIGN_DOWN(axi_addr, window_size);
+ pci_addr = ALIGN_DOWN(pci_addr, window_size);
+ size = window_size;
+ }
if (!IS_ALIGNED(axi_addr, window_size) ||
!IS_ALIGNED(pci_addr, window_size)) {
--
2.7.4
In the current implementation, config read output data 0xffff0001 is
assumed as CRS completion. But sometimes 0xffff0001 can be a valid data.
IPROC PCIe host controller PAXB v2 has a register to show config read
status flags like SC, UR, CRS and CA. So that extra check is added to
confirm the CRS using status flags before reissue config read.
Signed-off-by: Srinath Mannam <[email protected]>
Reviewed-by: Ray Jui <[email protected]>
---
drivers/pci/controller/pcie-iproc.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
index c20fd6b..b882255 100644
--- a/drivers/pci/controller/pcie-iproc.c
+++ b/drivers/pci/controller/pcie-iproc.c
@@ -60,6 +60,10 @@
#define APB_ERR_EN_SHIFT 0
#define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
+#define CFG_RD_SUCCESS 0
+#define CFG_RD_UR 1
+#define CFG_RD_CRS 2
+#define CFG_RD_CA 3
#define CFG_RETRY_STATUS 0xffff0001
#define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */
@@ -289,6 +293,9 @@ enum iproc_pcie_reg {
IPROC_PCIE_IARR4,
IPROC_PCIE_IMAP4,
+ /* config read status */
+ IPROC_PCIE_CFG_RD_STATUS,
+
/* link status */
IPROC_PCIE_LINK_STATUS,
@@ -350,6 +357,7 @@ static const u16 iproc_pcie_reg_paxb_v2[] = {
[IPROC_PCIE_IMAP3] = 0xe08,
[IPROC_PCIE_IARR4] = 0xe68,
[IPROC_PCIE_IMAP4] = 0xe70,
+ [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
[IPROC_PCIE_LINK_STATUS] = 0xf0c,
[IPROC_PCIE_APB_ERR_EN] = 0xf40,
};
@@ -474,10 +482,12 @@ static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
return (pcie->base + offset);
}
-static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
+static unsigned int iproc_pcie_cfg_retry(struct iproc_pcie *pcie,
+ void __iomem *cfg_data_p)
{
int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
unsigned int data;
+ u32 status;
/*
* As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only
@@ -498,6 +508,15 @@ static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
*/
data = readl(cfg_data_p);
while (data == CFG_RETRY_STATUS && timeout--) {
+ /*
+ * CRS state is set in CFG_RD status register
+ * This will handle the case where CFG_RETRY_STATUS is
+ * valid config data.
+ */
+ status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS);
+ if (status != CFG_RD_CRS)
+ return data;
+
udelay(1);
data = readl(cfg_data_p);
}
@@ -576,7 +595,7 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
if (!cfg_data_p)
return PCIBIOS_DEVICE_NOT_FOUND;
- data = iproc_pcie_cfg_retry(cfg_data_p);
+ data = iproc_pcie_cfg_retry(pcie, cfg_data_p);
*val = data;
if (size <= 2)
--
2.7.4
On Wed, Feb 20, 2019 at 10:03:55PM +0530, Srinath Mannam wrote:
> In the present driver outbound window configuration is done to map above
> 32-bit address I/O regions with corresponding PCI memory range given in
> ranges DT property.
>
> This patch add outbound window configuration to map below 32-bit I/O range
> with corresponding PCI memory, which helps to access I/O region in IA32
I think you mean ARM 32-bit here, not IA32.
> and one to one mapping of I/O region to PCI memory.
>
> Ex:
> 1. ranges DT property given for current driver is,
> ranges = <0x83000000 0x0 0x40000000 0x4 0x00000000 0 0x40000000>;
> I/O region address is 0x400000000
> 2. ranges DT property can be given after this patch,
> ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>;
> I/O region address is 0x42000000
>
> Signed-off-by: Srinath Mannam <[email protected]>
> Signed-off-by: Abhishek Shah <[email protected]>
> Signed-off-by: Ray Jui <[email protected]>
> Reviewed-by: Scott Branden <[email protected]>
> Reviewed-by: Vikram Prakash <[email protected]>
I asked you before, please point me at mailing list discussions where
these review tags were given, v1 was already carrying them but that's
not how the process works, they have to be given on mailing lists.
Lorenzo
> ---
> drivers/pci/controller/pcie-iproc.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
> index b882255..080f142 100644
> --- a/drivers/pci/controller/pcie-iproc.c
> +++ b/drivers/pci/controller/pcie-iproc.c
> @@ -955,8 +955,25 @@ static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
> resource_size_t window_size =
> ob_map->window_sizes[size_idx] * SZ_1M;
>
> - if (size < window_size)
> - continue;
> + /*
> + * Keep iterating until we reach the last window and
> + * with the minimal window size at index zero. In this
> + * case, we take a compromise by mapping it using the
> + * minimum window size that can be supported
> + */
> + if (size < window_size) {
> + if (size_idx > 0 || window_idx > 0)
> + continue;
> +
> + /*
> + * For the corner case of reaching the minimal
> + * window size that can be supported on the
> + * last window
> + */
> + axi_addr = ALIGN_DOWN(axi_addr, window_size);
> + pci_addr = ALIGN_DOWN(pci_addr, window_size);
> + size = window_size;
> + }
>
> if (!IS_ALIGNED(axi_addr, window_size) ||
> !IS_ALIGNED(pci_addr, window_size)) {
> --
> 2.7.4
>
Hi Lorenzo,
Thanks for the review.. Please see my comments below in line..
Regards,
Srinath.
On Thu, Feb 28, 2019 at 9:43 PM Lorenzo Pieralisi
<[email protected]> wrote:
>
> On Wed, Feb 20, 2019 at 10:03:55PM +0530, Srinath Mannam wrote:
> > In the present driver outbound window configuration is done to map above
> > 32-bit address I/O regions with corresponding PCI memory range given in
> > ranges DT property.
> >
> > This patch add outbound window configuration to map below 32-bit I/O range
> > with corresponding PCI memory, which helps to access I/O region in IA32
>
> I think you mean ARM 32-bit here, not IA32.
Yes ARM 32 bit.. Thank you.
>
> > and one to one mapping of I/O region to PCI memory.
> >
> > Ex:
> > 1. ranges DT property given for current driver is,
> > ranges = <0x83000000 0x0 0x40000000 0x4 0x00000000 0 0x40000000>;
> > I/O region address is 0x400000000
> > 2. ranges DT property can be given after this patch,
> > ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>;
> > I/O region address is 0x42000000
> >
> > Signed-off-by: Srinath Mannam <[email protected]>
> > Signed-off-by: Abhishek Shah <[email protected]>
> > Signed-off-by: Ray Jui <[email protected]>
> > Reviewed-by: Scott Branden <[email protected]>
> > Reviewed-by: Vikram Prakash <[email protected]>
>
> I asked you before, please point me at mailing list discussions where
> these review tags were given, v1 was already carrying them but that's
> not how the process works, they have to be given on mailing lists.
Sorry I missed your comment. These tags are our internal review list.
Many Thanks for sharing knowledge.
I will follow the process from next time onward. I will modify and
send next patch set.
>
> Lorenzo
>
> > ---
> > drivers/pci/controller/pcie-iproc.c | 21 +++++++++++++++++++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
> > index b882255..080f142 100644
> > --- a/drivers/pci/controller/pcie-iproc.c
> > +++ b/drivers/pci/controller/pcie-iproc.c
> > @@ -955,8 +955,25 @@ static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
> > resource_size_t window_size =
> > ob_map->window_sizes[size_idx] * SZ_1M;
> >
> > - if (size < window_size)
> > - continue;
> > + /*
> > + * Keep iterating until we reach the last window and
> > + * with the minimal window size at index zero. In this
> > + * case, we take a compromise by mapping it using the
> > + * minimum window size that can be supported
> > + */
> > + if (size < window_size) {
> > + if (size_idx > 0 || window_idx > 0)
> > + continue;
> > +
> > + /*
> > + * For the corner case of reaching the minimal
> > + * window size that can be supported on the
> > + * last window
> > + */
> > + axi_addr = ALIGN_DOWN(axi_addr, window_size);
> > + pci_addr = ALIGN_DOWN(pci_addr, window_size);
> > + size = window_size;
> > + }
> >
> > if (!IS_ALIGNED(axi_addr, window_size) ||
> > !IS_ALIGNED(pci_addr, window_size)) {
> > --
> > 2.7.4
> >