The Amlogic G12A SoCs embeds an Analog MIPI D-PHY to communicate with DSI
panels, this adds the bindings.
This Analog D-PHY works with a separate Digital MIPI D-PHY.
This serie adds the Bindings and the PHY driver.
Changes from v2 at [2]:
- Bindings example fix
Changes from v1 at [1]:
- Bindings fixes
[1] https://lore.kernel.org/r/[email protected]
[2] https://lore.kernel.org/r/[email protected]
Neil Armstrong (2):
dt-bindings: phy: add Amlogic G12A Analog MIPI D-PHY bindings
phy: amlogic: Add G12A Analog MIPI D-PHY driver
.../phy/amlogic,g12a-mipi-dphy-analog.yaml | 35 ++++
drivers/phy/amlogic/Kconfig | 12 ++
drivers/phy/amlogic/Makefile | 1 +
.../amlogic/phy-meson-g12a-mipi-dphy-analog.c | 177 ++++++++++++++++++
4 files changed, 225 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
create mode 100644 drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
--
2.25.1
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY to communicate with DSI
panels, this adds the bindings.
This Analog D-PHY works with a separate Digital MIPI D-PHY.
Signed-off-by: Neil Armstrong <[email protected]>
---
.../phy/amlogic,g12a-mipi-dphy-analog.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
diff --git a/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
new file mode 100644
index 000000000000..7aa0c05d6ce4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic G12A MIPI analog PHY
+
+maintainers:
+ - Neil Armstrong <[email protected]>
+
+properties:
+ compatible:
+ const: amlogic,g12a-mipi-dphy-analog
+
+ "#phy-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@0 {
+ compatible = "amlogic,g12a-mipi-dphy-analog";
+ reg = <0x0 0xc>;
+ #phy-cells = <0>;
+ };
--
2.25.1
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY used to communicate with DSI
panels.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/phy/amlogic/Kconfig | 12 ++
drivers/phy/amlogic/Makefile | 1 +
.../amlogic/phy-meson-g12a-mipi-dphy-analog.c | 177 ++++++++++++++++++
3 files changed, 190 insertions(+)
create mode 100644 drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
index db5d0cd757e3..ac898a102bcc 100644
--- a/drivers/phy/amlogic/Kconfig
+++ b/drivers/phy/amlogic/Kconfig
@@ -49,6 +49,18 @@ config PHY_MESON_G12A_USB3_PCIE
in Meson G12A SoCs.
If unsure, say N.
+config PHY_MESON_G12A_MIPI_DPHY_ANALOG
+ tristate "Meson G12A MIPI Analog DPHY driver"
+ default ARCH_MESON
+ depends on OF && (ARCH_MESON || COMPILE_TEST)
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ select GENERIC_PHY_MIPI_DPHY
+ help
+ Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
+ SoCs.
+ If unsure, say N.
+
config PHY_MESON_AXG_PCIE
tristate "Meson AXG PCIE PHY driver"
default ARCH_MESON
diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
index 8fa07fbd0d92..2eada0a683ca 100644
--- a/drivers/phy/amlogic/Makefile
+++ b/drivers/phy/amlogic/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
+obj-$(CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG) += phy-meson-g12a-mipi-dphy-analog.o
obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o
obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY) += phy-meson-axg-mipi-dphy.o
diff --git a/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c b/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
new file mode 100644
index 000000000000..6e9d416c0552
--- /dev/null
+++ b/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Meson G12A MIPI DSI Analog PHY
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <[email protected]>
+ */
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/phy/phy.h>
+
+#define HHI_MIPI_CNTL0 0x00
+#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
+#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
+
+#define HHI_MIPI_CNTL1 0x04
+#define HHI_MIPI_CNTL1_BANDGAP BIT(16)
+#define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)
+
+#define HHI_MIPI_CNTL2 0x08
+#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
+#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
+#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
+
+#define DSI_LANE_0 BIT(4)
+#define DSI_LANE_1 BIT(3)
+#define DSI_LANE_CLK BIT(2)
+#define DSI_LANE_2 BIT(1)
+#define DSI_LANE_3 BIT(0)
+
+struct phy_g12a_mipi_dphy_analog_priv {
+ struct phy *phy;
+ struct regmap *regmap;
+ struct phy_configure_opts_mipi_dphy config;
+};
+
+static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy,
+ union phy_configure_opts *opts)
+{
+ struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
+ if (ret)
+ return ret;
+
+ memcpy(&priv->config, opts, sizeof(priv->config));
+
+ return 0;
+}
+
+static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
+{
+ struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
+ unsigned int reg;
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL0,
+ FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) |
+ FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487));
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL1,
+ FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) |
+ HHI_MIPI_CNTL1_BANDGAP);
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL2,
+ FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) |
+ FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
+
+ reg = DSI_LANE_CLK;
+ switch (priv->config.lanes) {
+ case 4:
+ reg |= DSI_LANE_3;
+ fallthrough;
+ case 3:
+ reg |= DSI_LANE_2;
+ fallthrough;
+ case 2:
+ reg |= DSI_LANE_1;
+ fallthrough;
+ case 1:
+ reg |= DSI_LANE_0;
+ break;
+ default:
+ reg = 0;
+ }
+
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
+ HHI_MIPI_CNTL2_CH_EN,
+ FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
+
+ return 0;
+}
+
+static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy)
+{
+ struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
+
+ regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0);
+ regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0);
+ regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0);
+
+ return 0;
+}
+
+static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = {
+ .configure = phy_g12a_mipi_dphy_analog_configure,
+ .power_on = phy_g12a_mipi_dphy_analog_power_on,
+ .power_off = phy_g12a_mipi_dphy_analog_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_g12a_mipi_dphy_analog_priv *priv;
+ struct device_node *np = dev->of_node;
+ struct regmap *map;
+ int ret;
+
+ priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ /* Get the hhi system controller node */
+ map = syscon_node_to_regmap(of_get_parent(dev->of_node));
+ if (IS_ERR(map)) {
+ dev_err(dev,
+ "failed to get HHI regmap\n");
+ return PTR_ERR(map);
+ }
+
+ priv->regmap = map;
+
+ priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops);
+ if (IS_ERR(priv->phy)) {
+ ret = PTR_ERR(priv->phy);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to create PHY\n");
+ return ret;
+ }
+
+ phy_set_drvdata(priv->phy, priv);
+ dev_set_drvdata(dev, priv);
+
+ phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy);
+}
+
+static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
+ {
+ .compatible = "amlogic,g12a-mipi-dphy-analog",
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match);
+
+static struct platform_driver phy_g12a_mipi_dphy_analog_driver = {
+ .probe = phy_g12a_mipi_dphy_analog_probe,
+ .driver = {
+ .name = "phy-meson-g12a-mipi-dphy-analog",
+ .of_match_table = phy_g12a_mipi_dphy_analog_of_match,
+ },
+};
+module_platform_driver(phy_g12a_mipi_dphy_analog_driver);
+
+MODULE_AUTHOR("Neil Armstrong <[email protected]>");
+MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
Hi Neil,
On Fri, Jan 7, 2022 at 4:06 PM Neil Armstrong <[email protected]> wrote:
[...]
> +#define HHI_MIPI_CNTL2 0x08
> +#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
> +#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
> +#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
> +
> +#define DSI_LANE_0 BIT(4)
> +#define DSI_LANE_1 BIT(3)
> +#define DSI_LANE_CLK BIT(2)
> +#define DSI_LANE_2 BIT(1)
> +#define DSI_LANE_3 BIT(0)
At first I thought that these should be named
HHI_MIPI_CNTL2_DSI_LANE_0 (and similar).
But then I understood that they aren't bits directly in HHI_MIPI_CNTL2
but they belong to HHI_MIPI_CNTL2_CH_EN.
Have you considered naming them for example
HHI_MIPI_CNTL2_CH_EN_DSI_LANE_0 to make this more clear?
[...]
> + if (IS_ERR(map)) {
> + dev_err(dev,
> + "failed to get HHI regmap\n");
> + return PTR_ERR(map);
I suggest using:
return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
to simplify the code
[...]
> + if (IS_ERR(priv->phy)) {
> + ret = PTR_ERR(priv->phy);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to create PHY\n");
> + return ret;
and similar here:
return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
[...]
> +static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
> + {
> + .compatible = "amlogic,g12a-mipi-dphy-analog",
> + },
> + { },
In the past I was suggested to use:
{ /* sentinel */ }
meaning: no trailing comma here so nobody can add entries after the
sentinel by accident.
I suggest doing the same here if you re-spin this series.
Thank you!
Martin
Hi Neil,
On Fri, Jan 7, 2022 at 4:05 PM Neil Armstrong <[email protected]> wrote:
[...]
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
I also found a "MIPI DSI PHY clock" and "MIPI DSI PHY interrupt" in
the datasheet.
I'm no expert on this and I'm just asking in case you have missed one of these:
Can you confirm that these belong to some other IP?
Best regards,
Martin
On 07/01/2022 23:13, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Fri, Jan 7, 2022 at 4:05 PM Neil Armstrong <[email protected]> wrote:
> [...]
>> +required:
>> + - compatible
>> + - reg
>> + - "#phy-cells"
> I also found a "MIPI DSI PHY clock" and "MIPI DSI PHY interrupt" in
> the datasheet.
> I'm no expert on this and I'm just asking in case you have missed one of these:
> Can you confirm that these belong to some other IP?
Indeed the name is misleading, both go to the DSI Transceiver IP (dw-mipi-dsi)
Neil
>
>
> Best regards,
> Martin
>
Hi,
On 07/01/2022 23:09, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Fri, Jan 7, 2022 at 4:06 PM Neil Armstrong <[email protected]> wrote:
> [...]
>> +#define HHI_MIPI_CNTL2 0x08
>> +#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
>> +#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
>> +#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
>> +
>> +#define DSI_LANE_0 BIT(4)
>> +#define DSI_LANE_1 BIT(3)
>> +#define DSI_LANE_CLK BIT(2)
>> +#define DSI_LANE_2 BIT(1)
>> +#define DSI_LANE_3 BIT(0)
> At first I thought that these should be named
> HHI_MIPI_CNTL2_DSI_LANE_0 (and similar).
> But then I understood that they aren't bits directly in HHI_MIPI_CNTL2
> but they belong to HHI_MIPI_CNTL2_CH_EN.
> Have you considered naming them for example
> HHI_MIPI_CNTL2_CH_EN_DSI_LANE_0 to make this more clear?
>
> [...]
>> + if (IS_ERR(map)) {
>> + dev_err(dev,
>> + "failed to get HHI regmap\n");
>> + return PTR_ERR(map);
> I suggest using:
> return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
> to simplify the code
>
> [...]
>> + if (IS_ERR(priv->phy)) {
>> + ret = PTR_ERR(priv->phy);
>> + if (ret != -EPROBE_DEFER)
>> + dev_err(dev, "failed to create PHY\n");
>> + return ret;
> and similar here:
> return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
>
> [...]
>> +static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
>> + {
>> + .compatible = "amlogic,g12a-mipi-dphy-analog",
>> + },
>> + { },
> In the past I was suggested to use:
> { /* sentinel */ }
> meaning: no trailing comma here so nobody can add entries after the
> sentinel by accident.
> I suggest doing the same here if you re-spin this series.
Yep, will do the changes,
Thanks,
Neil
>
>
> Thank you!
> Martin
>
Hi Neil,
On Mon, Jan 10, 2022 at 10:25 AM Neil Armstrong <[email protected]> wrote:
>
> On 07/01/2022 23:13, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Fri, Jan 7, 2022 at 4:05 PM Neil Armstrong <[email protected]> wrote:
> > [...]
> >> +required:
> >> + - compatible
> >> + - reg
> >> + - "#phy-cells"
> > I also found a "MIPI DSI PHY clock" and "MIPI DSI PHY interrupt" in
> > the datasheet.
> > I'm no expert on this and I'm just asking in case you have missed one of these:
> > Can you confirm that these belong to some other IP?
>
> Indeed the name is misleading, both go to the DSI Transceiver IP (dw-mipi-dsi)
Thank you for clarifying this!
I just found an old comment from Rob on v2 of this series: [0]
He mentions:
"If this is a child of something else, then put a $ref to this schema
and the example in the parent schema."
To be honest: I completely forgot about that comment until now.
If I had remembered it (and assuming that his comment is still valid)
then I would have had to NACK my own
Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml
For today it's already late so I'll look into this more tomorrow.
Best regards,
Martin
[0] https://lore.kernel.org/all/[email protected]/