Hi everyone,
This is v3 of the initial Allwinner A80 support series.
This patch series adds very basic support for Allwinner's A80 SoC,
a big.LITTLE architecture with 4 Cortex-A7s and 4 Cortex-A15s.
Development is done on the A80 Optimus Board, the defacto development
board for the A80, with the accompanying SDK as a reference.
So far I've been unable to get the board to boot from MMC, or
using Android fastboot. I'm using Allwinner's FEL mode to load
the bootloader and kernel+dtb image over USB. Notes on my attempts
can be found here: http://linux-sunxi.org/User:Wens#A80_Optimus
Patch 1 introduces the compatible string for the A80.
Patch 2 adds a barebone dtsi with just the cpu, memory and uart nodes.
Patch 3 adds a barebone dts for the A80 Optimus Board.
Patch 4 documents all the Allwinner SoCs we currently support.
Patch 5 updates the sunxi README with a link to the A80's datasheet.
Changes since v2:
- Dropped (unused) cpu topology map from dtsi
- Added comment on ranges usage in dtsi
- Corrected typo in bindings document
- Dropped "A80" from Kconfig sun9i machine label and DT machine
description
- Dropped 2 patches already queued:
ARM: sunxi: Add debug uart used by sun9i (Allwinner A80)
devicetree: bindings: Add vendor prefix for Merrii Technology Co.,
Ltd.
Changes since v1:
- Use skeleton64.dtsi as basis to support maximum of 8GB DRAM
- Dropped dependency on ARCH_SUNXI for DEBUG_SUN9I_UART0
- Added empty lines separating cores in the DT cpu-map node
- Added patch 7 to update sunxi README
Cheers
ChenYu
Chen-Yu Tsai (5):
ARM: sunxi: Introduce Allwinner A80 support
ARM: dts: sunxi: Add Allwinner A80 dtsi
ARM: dts: sun9i: Add A80 Optimus Board support
devicetree: bindings: Document supported Allwinner sunxi SoCs
Documentation: sunxi: Add A80 datasheet link
Documentation/arm/sunxi/README | 3 +-
Documentation/devicetree/bindings/arm/sunxi.txt | 12 ++
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun9i-a80-optimus.dts | 66 ++++++
arch/arm/boot/dts/sun9i-a80.dtsi | 257 ++++++++++++++++++++++++
arch/arm/mach-sunxi/Kconfig | 5 +
arch/arm/mach-sunxi/sunxi.c | 9 +
7 files changed, 353 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/sunxi.txt
create mode 100644 arch/arm/boot/dts/sun9i-a80-optimus.dts
create mode 100644 arch/arm/boot/dts/sun9i-a80.dtsi
--
2.1.1
This adds a list of supported Allwinner SoC bindings.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/sunxi.txt
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
new file mode 100644
index 0000000..42941fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -0,0 +1,12 @@
+Allwinner sunXi Platforms Device Tree Bindings
+
+Each device tree must specify which Allwinner SoC it uses,
+using one of the following compatible strings:
+
+ allwinner,sun4i-a10
+ allwinner,sun5i-a10s
+ allwinner,sun5i-a13
+ allwinner,sun6i-a31
+ allwinner,sun7i-a20
+ allwinner,sun8i-a23
+ allwinner,sun9i-a80
--
2.1.1
We now have initial support for the A80, as well a the datasheet.
Update the documents to reflect this.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
Documentation/arm/sunxi/README | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 57c4da6..e68d163 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -58,4 +58,5 @@ SunXi family
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
- + Not Supported
\ No newline at end of file
+ + Datasheet
+ http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf
--
2.1.1
The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC.
While it's processor cores and interconnecting bus are new, it
re-uses many peripherals found in earlier Allwinner SoCs.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/mach-sunxi/Kconfig | 5 +++++
arch/arm/mach-sunxi/sunxi.c | 9 +++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1aaa1e1..d04f84b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -42,4 +42,9 @@ config MACH_SUN8I
select MFD_SUN6I_PRCM
select RESET_CONTROLLER
+config MACH_SUN9I
+ bool "Allwinner (sun9i) SoCs support"
+ default ARCH_SUNXI
+ select ARM_GIC
+
endif
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 42d4753..ba926b5 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -139,3 +139,12 @@ static const char * const sun8i_board_dt_compat[] = {
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
.dt_compat = sun8i_board_dt_compat,
MACHINE_END
+
+static const char * const sun9i_board_dt_compat[] = {
+ "allwinner,sun9i-a80",
+ NULL,
+};
+
+DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
+ .dt_compat = sun9i_board_dt_compat,
+MACHINE_END
--
2.1.1
The A80 Optimus Board is was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.
This board has a UART port, a JTAG connector, USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND flash,
4G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
jack, IR receiver, and additional GPIO headers.
This patch adds only basic support.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun9i-a80-optimus.dts | 66 +++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
create mode 100644 arch/arm/boot/dts/sun9i-a80-optimus.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 14dbc6c..6e5474c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -426,6 +426,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb
+dtb-$(CONFIG_MACH_SUN9I) += \
+ sun9i-a80-optimus.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-medcom-wide.dtb \
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
new file mode 100644
index 0000000..f83abab
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <[email protected]>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun9i-a80.dtsi"
+
+/ {
+ model = "Merrii A80 Optimus Board";
+ compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200";
+ };
+
+ soc {
+ uart0: serial@07000000 {
+ status = "okay";
+ };
+ };
+};
--
2.1.1
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and
4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core
PowerVR G6230 GPU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 257 +++++++++++++++++++++++++++++++++++++++
1 file changed, 257 insertions(+)
create mode 100644 arch/arm/boot/dts/sun9i-a80.dtsi
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
new file mode 100644
index 0000000..5e2ec4b
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <[email protected]>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &r_uart;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x3>;
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x100>;
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x101>;
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x102>;
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x103>;
+ };
+ };
+
+ memory {
+ /* 8GB max. with LPAE */
+ reg = <0 0x20000000 0x02 0>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * map 64 bit address range down to 32 bits,
+ * as the peripherals are all under 512MB.
+ */
+ ranges = <0 0 0 0x20000000>;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * map 64 bit address range down to 32 bits,
+ * as the peripherals are all under 512MB.
+ */
+ ranges = <0 0 0 0x20000000>;
+
+ gic: interrupt-controller@01c41000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c41000 0x1000>,
+ <0x01c42000 0x1000>,
+ <0x01c44000 0x2000>,
+ <0x01c46000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ timer@06000c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x06000c00 0xa0>;
+ interrupts = <0 18 4>,
+ <0 19 4>,
+ <0 20 4>,
+ <0 21 4>,
+ <0 22 4>,
+ <0 23 4>;
+
+ clocks = <&osc24M>;
+ };
+
+ uart0: serial@07000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000000 0x400>;
+ interrupts = <0 0 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+
+ uart1: serial@07000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000400 0x400>;
+ interrupts = <0 1 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+
+ uart2: serial@07000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000800 0x400>;
+ interrupts = <0 2 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+
+ uart3: serial@07000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000c00 0x400>;
+ interrupts = <0 3 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+
+ uart4: serial@07001000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07001000 0x400>;
+ interrupts = <0 4 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+
+ uart5: serial@07001400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07001400 0x400>;
+ interrupts = <0 5 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+
+ r_wdt: watchdog@08001000 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x08001000 0x20>;
+ interrupts = <0 36 4>;
+ };
+
+ r_uart: serial@08002800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x08002800 0x400>;
+ interrupts = <0 38 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+ };
+};
--
2.1.1
On 10/8/14, 8:02 AM, Chen-Yu Tsai wrote:
> The A80 Optimus Board is was launched with the Allwinner A80 SoC.
> It was jointly developed by Allwinner and Merrii.
>
> This board has a UART port, a JTAG connector, USB host ports, a USB
> 3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND flash,
> 4G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
> jack, IR receiver, and additional GPIO headers.
>
> This patch adds only basic support.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/sun9i-a80-optimus.dts | 66 +++++++++++++++++++++++++++++++++
> 2 files changed, 68 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun9i-a80-optimus.dts
>
[...]
> +
> +/dts-v1/;
> +/include/ "sun9i-a80.dtsi"
> +
> +/ {
> + model = "Merrii A80 Optimus Board";
> + compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
"merrii" should be added to vendor-prefixes.txt
Dinh
On Wed, Oct 8, 2014 at 9:32 PM, Dinh Nguyen <[email protected]> wrote:
>
>
> On 10/8/14, 8:02 AM, Chen-Yu Tsai wrote:
>> The A80 Optimus Board is was launched with the Allwinner A80 SoC.
>> It was jointly developed by Allwinner and Merrii.
>>
>> This board has a UART port, a JTAG connector, USB host ports, a USB
>> 3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND flash,
>> 4G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
>> jack, IR receiver, and additional GPIO headers.
>>
>> This patch adds only basic support.
>>
>> Signed-off-by: Chen-Yu Tsai <[email protected]>
>> ---
>> arch/arm/boot/dts/Makefile | 2 +
>> arch/arm/boot/dts/sun9i-a80-optimus.dts | 66 +++++++++++++++++++++++++++++++++
>> 2 files changed, 68 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun9i-a80-optimus.dts
>>
> [...]
>> +
>> +/dts-v1/;
>> +/include/ "sun9i-a80.dtsi"
>> +
>> +/ {
>> + model = "Merrii A80 Optimus Board";
>> + compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
>
> "merrii" should be added to vendor-prefixes.txt
A patch for that was already queued by Maxime.
ChenYu
Hi,
Am 08.10.2014 um 15:02 schrieb Chen-Yu Tsai:
> This is v3 of the initial Allwinner A80 support series.
> This patch series adds very basic support for Allwinner's A80 SoC,
> a big.LITTLE architecture with 4 Cortex-A7s and 4 Cortex-A15s.
>
> Development is done on the A80 Optimus Board, the defacto development
> board for the A80, with the accompanying SDK as a reference.
>
> So far I've been unable to get the board to boot from MMC, or
> using Android fastboot. I'm using Allwinner's FEL mode to load
> the bootloader and kernel+dtb image over USB. Notes on my attempts
> can be found here: http://linux-sunxi.org/User:Wens#A80_Optimus
Tested-by: Andreas F?rber <[email protected]>
With this patch set on top of Maxime's sunxi-next branch, I get as far
as searching for the rootfs.
CPUs 1-7 fail to boot with -38, which I guess is due to the vendor
U-Boot not yet supporting PSCI.
Thanks a lot for your work and help, Chen-Yu!
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg
On Wed, Oct 08, 2014 at 09:02:51PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This is v3 of the initial Allwinner A80 support series.
> This patch series adds very basic support for Allwinner's A80 SoC,
> a big.LITTLE architecture with 4 Cortex-A7s and 4 Cortex-A15s.
>
> Development is done on the A80 Optimus Board, the defacto development
> board for the A80, with the accompanying SDK as a reference.
>
> So far I've been unable to get the board to boot from MMC, or
> using Android fastboot. I'm using Allwinner's FEL mode to load
> the bootloader and kernel+dtb image over USB. Notes on my attempts
> can be found here: http://linux-sunxi.org/User:Wens#A80_Optimus
>
>
> Patch 1 introduces the compatible string for the A80.
>
> Patch 2 adds a barebone dtsi with just the cpu, memory and uart nodes.
>
> Patch 3 adds a barebone dts for the A80 Optimus Board.
>
> Patch 4 documents all the Allwinner SoCs we currently support.
>
> Patch 5 updates the sunxi README with a link to the A80's datasheet.
Applied all of them, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hi,
On Thu, Oct 09, 2014 at 04:54:35AM +0200, Andreas F?rber wrote:
> Hi,
>
> Am 08.10.2014 um 15:02 schrieb Chen-Yu Tsai:
> > This is v3 of the initial Allwinner A80 support series.
> > This patch series adds very basic support for Allwinner's A80 SoC,
> > a big.LITTLE architecture with 4 Cortex-A7s and 4 Cortex-A15s.
> >
> > Development is done on the A80 Optimus Board, the defacto development
> > board for the A80, with the accompanying SDK as a reference.
> >
> > So far I've been unable to get the board to boot from MMC, or
> > using Android fastboot. I'm using Allwinner's FEL mode to load
> > the bootloader and kernel+dtb image over USB. Notes on my attempts
> > can be found here: http://linux-sunxi.org/User:Wens#A80_Optimus
>
> Tested-by: Andreas F?rber <[email protected]>
>
> With this patch set on top of Maxime's sunxi-next branch, I get as far
> as searching for the rootfs.
>
> CPUs 1-7 fail to boot with -38, which I guess is due to the vendor
> U-Boot not yet supporting PSCI.
That, and Linux not having some SMP bringup code either.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
When booting Linux 3.19-rc2 on a Merrii Optimusboard using
arch/arm/boot/dts/sun9i-a80-optimus.dts adn
arch/arm/boot/dts/sun9i-a80.dtsi I get errors
[ 0.061192] /cpus/cpu@0 missing clock-frequency property
[ 0.061209] /cpus/cpu@1 missing clock-frequency property
[ 0.061223] /cpus/cpu@2 missing clock-frequency property
[ 0.061237] /cpus/cpu@3 missing clock-frequency property
[ 0.061251] /cpus/cpu@100 missing clock-frequency property
[ 0.061266] /cpus/cpu@101 missing clock-frequency property
[ 0.061283] /cpus/cpu@102 missing clock-frequency property
[ 0.061300] /cpus/cpu@103 missing clock-frequency property
The dtsi was provided by patch
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=4ab328f06e305bf3ea254f4e3c94bb4d820998c1
According to file pack/chips/sun9iw1p1/optimus/sys_config.fex supplied
in the OptimusBoard SDK the big cluster can run at up to 1800 MHz, and
the LITTLE cluster can run at up to 1200 MHz,depending on the CPU voltage:
big
1.08V (1608Mhz, 1800Mhz]
1.00V (1536Mhz, 1608Mhz]
0.96V (1440Mhz, 1536Mhz]
0.90V (1296Mhz, 1440Mhz]
0.84V ( 0Mhz, 1296Mhz]
LITTLE
1.02V (1128Mhz, 1200Mhz]
0.96V (1008Mhz, 1128Mhz]
0.90V ( 864Mhz, 1008Mhz]
0.84V ( 0Mhz, 864Mhz]
I guess the proper way to specify the data is the one described in
Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
Other boards might run at other frequencies. Hence we might want to put
this information into the board file
arch/arm/boot/dts/sun9i-a80-optimus.dts.
Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt,
arch/arm/boot/dts/exynos5260.dtsi, and
arch/arm/boot/dts/exynos5420.dtsi, all assume that
cpu@0-cpu@3 are A15 (big) and cpu@101-cpu@103 are A7 (LITTLE).
Shouldn't arch/arm/boot/dts/sun9i-a80.dtsi stick to this convention?
The scripts to create the uImage and to reproduce the problem are in
https://github.com/xypron/kernel-optimusboard/tree/35d06c020f6584b5023e0e4bef67cc5a625f65bb
Best regards
Heinrich Schuchardt
On Wed, Dec 31, 2014 at 8:37 AM, Heinrich Schuchardt <[email protected]> wrote:
> When booting Linux 3.19-rc2 on a Merrii Optimusboard using
> arch/arm/boot/dts/sun9i-a80-optimus.dts adn arch/arm/boot/dts/sun9i-a80.dtsi
> I get errors
> [ 0.061192] /cpus/cpu@0 missing clock-frequency property
> [ 0.061209] /cpus/cpu@1 missing clock-frequency property
> [ 0.061223] /cpus/cpu@2 missing clock-frequency property
> [ 0.061237] /cpus/cpu@3 missing clock-frequency property
> [ 0.061251] /cpus/cpu@100 missing clock-frequency property
> [ 0.061266] /cpus/cpu@101 missing clock-frequency property
> [ 0.061283] /cpus/cpu@102 missing clock-frequency property
> [ 0.061300] /cpus/cpu@103 missing clock-frequency property
The clock-frequency property is in no way connected to clocks
or cpufreq on Linux. It is solely used to generate a topology
map for multi-cluster systems. Personally I prefer the
cpu-topology bindings on arm64, but this is what we have.
> The dtsi was provided by patch
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=4ab328f06e305bf3ea254f4e3c94bb4d820998c1
>
> According to file pack/chips/sun9iw1p1/optimus/sys_config.fex supplied in
> the OptimusBoard SDK the big cluster can run at up to 1800 MHz, and
> the LITTLE cluster can run at up to 1200 MHz,depending on the CPU voltage:
>
> big
> 1.08V (1608Mhz, 1800Mhz]
> 1.00V (1536Mhz, 1608Mhz]
> 0.96V (1440Mhz, 1536Mhz]
> 0.90V (1296Mhz, 1440Mhz]
> 0.84V ( 0Mhz, 1296Mhz]
>
> LITTLE
> 1.02V (1128Mhz, 1200Mhz]
> 0.96V (1008Mhz, 1128Mhz]
> 0.90V ( 864Mhz, 1008Mhz]
> 0.84V ( 0Mhz, 864Mhz]
>
> I guess the proper way to specify the data is the one described in
> Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
cpufreq requires a bit more than just specifying the operating
points. Moreover, SMP is not supported on sun9i yet. For DVFS
we also need support for the PMICs.
> Other boards might run at other frequencies. Hence we might want to put this
> information into the board file
> arch/arm/boot/dts/sun9i-a80-optimus.dts.
We can also give a default set of OPP in the dtsi, and any boards
having special voltage requirements can override them or use the
voltage-derivation property (not sure that's the name).
> Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt,
> arch/arm/boot/dts/exynos5260.dtsi, and
> arch/arm/boot/dts/exynos5420.dtsi, all assume that
> cpu@0-cpu@3 are A15 (big) and cpu@101-cpu@103 are A7 (LITTLE).
>
> Shouldn't arch/arm/boot/dts/sun9i-a80.dtsi stick to this convention?
This is not some convention. The values match what the hardware
says in the MPIDR.
ChenYu
> The scripts to create the uImage and to reproduce the problem are in
> https://github.com/xypron/kernel-optimusboard/tree/35d06c020f6584b5023e0e4bef67cc5a625f65bb
>
> Best regards
>
> Heinrich Schuchardt
>
>