Some flash chips which do not have a SFDP table supports Quad Input
Page Program. One of those chips is is25wp256, and this series has been
tested with that chip. If the spi controller supports quad mode then the
chip can use Quad Input Page Program to give a much better performance.
Sudip Mukherjee (3):
mtd: spi-nor: extend no_sfdp_flags to use u16
mtd: spi-nor: add support for Quad Page Program to no_sfdp_flags
mtd: spi-nor: issi: is25wp256: Enable Quad Input Page Program
drivers/mtd/spi-nor/core.c | 7 ++++++-
drivers/mtd/spi-nor/core.h | 4 +++-
drivers/mtd/spi-nor/issi.c | 3 ++-
3 files changed, 11 insertions(+), 3 deletions(-)
--
2.30.2
Some flash chips which does not have a SFDP table can support Quad
Input Page Program. Enable it in hwcaps if defined.
Signed-off-by: Sudip Mukherjee <[email protected]>
---
drivers/mtd/spi-nor/core.c | 5 +++++
drivers/mtd/spi-nor/core.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index e5f7691c5bd40..e299fc8fdd3d4 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2375,6 +2375,11 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
}
+ if (no_sfdp_flags & SPI_NOR_QUAD_PP) {
+ params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
+ spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
+ SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
+ }
/*
* Sector Erase settings. Sort Erase Types in ascending order, with the
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 58fbedc94080f..dde636bdb1a7c 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -462,6 +462,7 @@ struct spi_nor_fixups {
* SPI_NOR_OCTAL_READ: flash supports Octal Read.
* SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
* SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
+ * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
*
* @fixup_flags: flags that indicate support that can be discovered via SFDP
* ideally, but can not be discovered for this particular flash
@@ -509,6 +510,7 @@ struct flash_info {
#define SPI_NOR_OCTAL_READ BIT(5)
#define SPI_NOR_OCTAL_DTR_READ BIT(6)
#define SPI_NOR_OCTAL_DTR_PP BIT(7)
+#define SPI_NOR_QUAD_PP BIT(8)
u8 fixup_flags;
#define SPI_NOR_4B_OPCODES BIT(0)
--
2.30.2
Currently no_sfdp_flags is u8 and all the bits have been used. Extend
it to use u16 so that we can add more support.
Signed-off-by: Sudip Mukherjee <[email protected]>
---
drivers/mtd/spi-nor/core.c | 2 +-
drivers/mtd/spi-nor/core.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ce5d69317d46c..e5f7691c5bd40 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2335,7 +2335,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
struct spi_nor_erase_map *map = ¶ms->erase_map;
- const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
+ const u16 no_sfdp_flags = nor->info->no_sfdp_flags;
u8 i, erase_mask;
if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 61886868cd022..58fbedc94080f 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -501,7 +501,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(7)
#define SPI_NOR_NO_FR BIT(8)
- u8 no_sfdp_flags;
+ u16 no_sfdp_flags;
#define SPI_NOR_SKIP_SFDP BIT(0)
#define SECT_4K BIT(1)
#define SPI_NOR_DUAL_READ BIT(3)
--
2.30.2
The flash chip is25wp256 supports Quad Input Page Program. Enable it
in its no_sfdp_flags flags.
Signed-off-by: Sudip Mukherjee <[email protected]>
---
drivers/mtd/spi-nor/issi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 3c7d51d2b0509..9a04b03bebe0b 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -71,7 +71,8 @@ static const struct flash_info issi_nor_parts[] = {
{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512)
- NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_QUAD_PP)
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
.fixups = &is25lp256_fixups },
--
2.30.2
Am 2022-07-12 18:38, schrieb Sudip Mukherjee:
> The flash chip is25wp256 supports Quad Input Page Program. Enable it
> in its no_sfdp_flags flags.
Are you sure, that chip doesn't have SFDP? Even the oldest datasheet
I've found [1] mention SFDP.
[1] https://datasheetspdf.com/pdf-file/1303587/ISSI/IS25WP256/1
-michael
Hi Michael,
On Mon, Jul 18, 2022 at 8:39 AM Michael Walle <[email protected]> wrote:
>
> Am 2022-07-12 18:38, schrieb Sudip Mukherjee:
> > The flash chip is25wp256 supports Quad Input Page Program. Enable it
> > in its no_sfdp_flags flags.
>
> Are you sure, that chip doesn't have SFDP? Even the oldest datasheet
> I've found [1] mention SFDP.
Yes, that is what I expected from the datasheet. But from the driver code,
spi_nor_init_params() is calling spi_nor_init_params_deprecated() as
'parse_sfdp' is not true.
and looking at issi_nor_parts[], I can see is25wp256 is not marked
with 'PARSE_SFDP' so it
will skip parsing SFDP. The same datasheet also has is25lp256 which is
marked with 'PARSE_SFDP'
in the driver.
I tried to add 'PARSE_SFDP' to is25wp256, and I can see its mostly
working but its not using
Quad Input Page Program. I guess this support was not discovered from SFDP.
--
Regards
Sudip
On 7/12/22 19:38, Sudip Mukherjee wrote:
> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Currently no_sfdp_flags is u8 and all the bits have been used. Extend
> it to use u16 so that we can add more support.
>
> Signed-off-by: Sudip Mukherjee <[email protected]>
> ---
> drivers/mtd/spi-nor/core.c | 2 +-
> drivers/mtd/spi-nor/core.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index ce5d69317d46c..e5f7691c5bd40 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2335,7 +2335,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
> {
> struct spi_nor_flash_parameter *params = nor->params;
> struct spi_nor_erase_map *map = ¶ms->erase_map;
> - const u8 no_sfdp_flags = nor->info->no_sfdp_flags;
> + const u16 no_sfdp_flags = nor->info->no_sfdp_flags;
> u8 i, erase_mask;
>
> if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 61886868cd022..58fbedc94080f 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -501,7 +501,7 @@ struct flash_info {
> #define NO_CHIP_ERASE BIT(7)
> #define SPI_NOR_NO_FR BIT(8)
>
> - u8 no_sfdp_flags;
> + u16 no_sfdp_flags;
> #define SPI_NOR_SKIP_SFDP BIT(0)
> #define SECT_4K BIT(1)
> #define SPI_NOR_DUAL_READ BIT(3)
> --
> 2.30.2
>
you can extend this when introducing a new flag, if needed.
No need for a dedicated patch just for this.
On 7/12/22 19:38, Sudip Mukherjee wrote:
> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Some flash chips which does not have a SFDP table can support Quad
> Input Page Program. Enable it in hwcaps if defined.
>
> Signed-off-by: Sudip Mukherjee <[email protected]>
> ---
> drivers/mtd/spi-nor/core.c | 5 +++++
> drivers/mtd/spi-nor/core.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index e5f7691c5bd40..e299fc8fdd3d4 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2375,6 +2375,11 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
> spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
> SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
> }
> + if (no_sfdp_flags & SPI_NOR_QUAD_PP) {
> + params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
> + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
> + SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
> + }
>
> /*
> * Sector Erase settings. Sort Erase Types in ascending order, with the
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 58fbedc94080f..dde636bdb1a7c 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -462,6 +462,7 @@ struct spi_nor_fixups {
> * SPI_NOR_OCTAL_READ: flash supports Octal Read.
> * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
> * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
> + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
You don't need this flag if your flash supports the 4-byte Address
Instruction Table. Does you flash support it? Can you dump all the
SFDP tables, please?
Thanks,
ta
> *
> * @fixup_flags: flags that indicate support that can be discovered via SFDP
> * ideally, but can not be discovered for this particular flash
> @@ -509,6 +510,7 @@ struct flash_info {
> #define SPI_NOR_OCTAL_READ BIT(5)
> #define SPI_NOR_OCTAL_DTR_READ BIT(6)
> #define SPI_NOR_OCTAL_DTR_PP BIT(7)
> +#define SPI_NOR_QUAD_PP BIT(8)
>
> u8 fixup_flags;
> #define SPI_NOR_4B_OPCODES BIT(0)
> --
> 2.30.2
>
On Mon, Jul 18, 2022 at 6:02 PM <[email protected]> wrote:
>
> On 7/12/22 19:38, Sudip Mukherjee wrote:
> > [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Some flash chips which does not have a SFDP table can support Quad
> > Input Page Program. Enable it in hwcaps if defined.
> >
<snip>
> > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> > index 58fbedc94080f..dde636bdb1a7c 100644
> > --- a/drivers/mtd/spi-nor/core.h
> > +++ b/drivers/mtd/spi-nor/core.h
> > @@ -462,6 +462,7 @@ struct spi_nor_fixups {
> > * SPI_NOR_OCTAL_READ: flash supports Octal Read.
> > * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
> > * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
> > + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
>
> You don't need this flag if your flash supports the 4-byte Address
> Instruction Table. Does you flash support it? Can you dump all the
> SFDP tables, please?
Not sure what the correct way to dump sfdp is. I did this from sysfs.
# cat sfdp | xxd
00000000: 5346 4450 0601 01ff 0006 0110 3000 00ff SFDP........0...
00000010: 9d05 0103 8000 0002 ffff ffff ffff ffff ................
00000020: ffff ffff ffff ffff ffff ffff ffff ffff ................
00000030: e520 f9ff ffff ff0f 44eb 086b 083b 80bb . ......D..k.;..
00000040: feff ffff ffff 00ff ffff 44eb 0c20 0f52 ..........D.. .R
00000050: 10d8 00ff 234a c900 82d8 11ce cccd 6846 ....#J........hF
00000060: 7a75 7a75 f7ae d55c 4a42 2cff f030 faa9 zuzu...\JB,..0..
00000070: ffff ffff ffff ffff ffff ffff ffff ffff ................
00000080: 5019 5016 9ff9 c064 8fef ffff P.P....d....
--
Regards
Sudip
Hi Tudor,
On Mon, Jul 18, 2022 at 7:49 PM Sudip Mukherjee
<[email protected]> wrote:
>
> On Mon, Jul 18, 2022 at 6:02 PM <[email protected]> wrote:
> >
> > On 7/12/22 19:38, Sudip Mukherjee wrote:
> > > [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> > >
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > Some flash chips which does not have a SFDP table can support Quad
> > > Input Page Program. Enable it in hwcaps if defined.
> > >
>
> <snip>
>
> > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> > > index 58fbedc94080f..dde636bdb1a7c 100644
> > > --- a/drivers/mtd/spi-nor/core.h
> > > +++ b/drivers/mtd/spi-nor/core.h
> > > @@ -462,6 +462,7 @@ struct spi_nor_fixups {
> > > * SPI_NOR_OCTAL_READ: flash supports Octal Read.
> > > * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
> > > * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
> > > + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
> >
> > You don't need this flag if your flash supports the 4-byte Address
> > Instruction Table. Does you flash support it? Can you dump all the
> > SFDP tables, please?
>
> Not sure what the correct way to dump sfdp is. I did this from sysfs.
I tried decoding this SFDP table and I think the parameters table says
it has "3-Byte only addressing".
So, I guess that means it does not support 4-byte Address Instruction
Table. And the datasheet
says it supports "Quad Input Page Program (3-byte Address)".
My existing patchset works for Quad Input Page Program, and I can send
a v2 with the previous
patch and this merged together (as you suggested) or I can try
enabling sfdp for this chip and then use
a fixup_flags to enable "Quad Input Page Program" which I think will
be more complicated.
Which one will you suggest?
--
Regards
Sudip
On 7/18/22 21:49, Sudip Mukherjee wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Jul 18, 2022 at 6:02 PM <[email protected]> wrote:
>>
>> On 7/12/22 19:38, Sudip Mukherjee wrote:
>>> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Some flash chips which does not have a SFDP table can support Quad
>>> Input Page Program. Enable it in hwcaps if defined.
>>>
>
> <snip>
>
>>> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
>>> index 58fbedc94080f..dde636bdb1a7c 100644
>>> --- a/drivers/mtd/spi-nor/core.h
>>> +++ b/drivers/mtd/spi-nor/core.h
>>> @@ -462,6 +462,7 @@ struct spi_nor_fixups {
>>> * SPI_NOR_OCTAL_READ: flash supports Octal Read.
>>> * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
>>> * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
>>> + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
>>
>> You don't need this flag if your flash supports the 4-byte Address
>> Instruction Table. Does you flash support it? Can you dump all the
>> SFDP tables, please?
>
> Not sure what the correct way to dump sfdp is. I did this from sysfs.
>
> # cat sfdp | xxd
> 00000000: 5346 4450 0601 01ff 0006 0110 3000 00ff SFDP........0...
We really need a decoder for this :D.
5346 4450 - sfdp signature
0601 01ff - 2nd dword, 2 parameter tables
0006 0110 - BFPT of 16 dwords
3000 00ff - parameter header, 2nd dword
> 00000010: 9d05 0103 8000 0002 ffff ffff ffff ffff ................
9d05 0103 ID LSB = 0x9d, table with 3 dwords
8000 0002 ID MSB = 0x02 -> looks like a function specific vendor table
So the flash does not support the 4-byte Address Instruction table, we
can't retrieve the Quad PP from SFDP.
> 00000020: ffff ffff ffff ffff ffff ffff ffff ffff ................
> 00000030: e520 f9ff ffff ff0f 44eb 086b 083b 80bb . ......D..k.;..
> 00000040: feff ffff ffff 00ff ffff 44eb 0c20 0f52 ..........D.. .R
> 00000050: 10d8 00ff 234a c900 82d8 11ce cccd 6846 ....#J........hF
> 00000060: 7a75 7a75 f7ae d55c 4a42 2cff f030 faa9 zuzu...\JB,..0..
> 00000070: ffff ffff ffff ffff ffff ffff ffff ffff ................
> 00000080: 5019 5016 9ff9 c064 8fef ffff P.P....d....
>
>
> --
> Regards
> Sudip
--
Cheers,
ta
On 7/22/22 13:24, Sudip Mukherjee wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Tudor,
>
Hi!
> On Mon, Jul 18, 2022 at 7:49 PM Sudip Mukherjee
> <[email protected]> wrote:
>>
>> On Mon, Jul 18, 2022 at 6:02 PM <[email protected]> wrote:
>>>
>>> On 7/12/22 19:38, Sudip Mukherjee wrote:
>>>> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> Some flash chips which does not have a SFDP table can support Quad
>>>> Input Page Program. Enable it in hwcaps if defined.
>>>>
>>
>> <snip>
>>
>>>> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
>>>> index 58fbedc94080f..dde636bdb1a7c 100644
>>>> --- a/drivers/mtd/spi-nor/core.h
>>>> +++ b/drivers/mtd/spi-nor/core.h
>>>> @@ -462,6 +462,7 @@ struct spi_nor_fixups {
>>>> * SPI_NOR_OCTAL_READ: flash supports Octal Read.
>>>> * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
>>>> * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
>>>> + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
>>>
>>> You don't need this flag if your flash supports the 4-byte Address
>>> Instruction Table. Does you flash support it? Can you dump all the
>>> SFDP tables, please?
>>
>> Not sure what the correct way to dump sfdp is. I did this from sysfs.
>
> I tried decoding this SFDP table and I think the parameters table says
> it has "3-Byte only addressing".
> So, I guess that means it does not support 4-byte Address Instruction
> Table. And the datasheet
> says it supports "Quad Input Page Program (3-byte Address)".
> My existing patchset works for Quad Input Page Program, and I can send
> a v2 with the previous
> patch and this merged together (as you suggested) or I can try
> enabling sfdp for this chip and then use
You should definitely enable SFDP and get rid of the NO_SFDP_FLAGS flags,
regardless of the 1-1-4 PP outcome.
> a fixup_flags to enable "Quad Input Page Program" which I think will
> be more complicated.
> Which one will you suggest?
>
First I'd like to understand what "much better performance" means. Would
you run some speed tests please? mtd-utils should have a speedtest, otherwise
you can use the in kernel mtd_speedtest module. Page programs are slow anyway,
using 4 lines may not make any difference. But let's see.
About your question, it depends on how common is 1-1-4 pp. If it's common and
desirable we can introduce a flash info flag.
--
Cheers,
ta
On 29/07/2022 08:48, [email protected] wrote:
> On 7/22/22 13:24, Sudip Mukherjee wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi Tudor,
>>
>
> Hi!
>
>> On Mon, Jul 18, 2022 at 7:49 PM Sudip Mukherjee
>> <[email protected]> wrote:
>>>
>>> On Mon, Jul 18, 2022 at 6:02 PM <[email protected]> wrote:
>>>>
>>>> On 7/12/22 19:38, Sudip Mukherjee wrote:
>>>>> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> Some flash chips which does not have a SFDP table can support Quad
>>>>> Input Page Program. Enable it in hwcaps if defined.
>>>>>
>>>
>>> <snip>
>>>
>>>>> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
>>>>> index 58fbedc94080f..dde636bdb1a7c 100644
>>>>> --- a/drivers/mtd/spi-nor/core.h
>>>>> +++ b/drivers/mtd/spi-nor/core.h
>>>>> @@ -462,6 +462,7 @@ struct spi_nor_fixups {
>>>>> * SPI_NOR_OCTAL_READ: flash supports Octal Read.
>>>>> * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
>>>>> * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
>>>>> + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
>>>>
>>>> You don't need this flag if your flash supports the 4-byte Address
>>>> Instruction Table. Does you flash support it? Can you dump all the
>>>> SFDP tables, please?
>>>
>>> Not sure what the correct way to dump sfdp is. I did this from sysfs.
>>
>> I tried decoding this SFDP table and I think the parameters table says
>> it has "3-Byte only addressing".
>> So, I guess that means it does not support 4-byte Address Instruction
>> Table. And the datasheet
>> says it supports "Quad Input Page Program (3-byte Address)".
>> My existing patchset works for Quad Input Page Program, and I can send
>> a v2 with the previous
>> patch and this merged together (as you suggested) or I can try
>> enabling sfdp for this chip and then use
>
> You should definitely enable SFDP and get rid of the NO_SFDP_FLAGS flags,
> regardless of the 1-1-4 PP outcome.
>
>> a fixup_flags to enable "Quad Input Page Program" which I think will
>> be more complicated.
>> Which one will you suggest?
>>
>
> First I'd like to understand what "much better performance" means. Would
> you run some speed tests please? mtd-utils should have a speedtest, otherwise
> you can use the in kernel mtd_speedtest module. Page programs are slow anyway,
> using 4 lines may not make any difference. But let's see.
>
> About your question, it depends on how common is 1-1-4 pp. If it's common and
> desirable we can introduce a flash info flag.
We have an issue with the SPI controller where if it isn't in the above
1 bit modes it has to block the CPU as the feature to hold the clock is
not enabled in the 1bit "old" modes. In the old modes, if the FIFO gets
to the empty stage then the CS gets de-selected. If we can enable the
4bit mode, we can also set the clock-suspend flag which means the code
does not have to block the core it is running on to ensure it gets the
data out in time.
At the moment speed tests are not easy as we are on entirely emulated
hardware, we could try some but the results may not represent what the
real chip can perform.
--
Ben
On 7/29/22 11:10, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 29/07/2022 08:48, [email protected] wrote:
>> On 7/22/22 13:24, Sudip Mukherjee wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Hi Tudor,
>>>
>>
>> Hi!
>>
>>> On Mon, Jul 18, 2022 at 7:49 PM Sudip Mukherjee
>>> <[email protected]> wrote:
>>>>
>>>> On Mon, Jul 18, 2022 at 6:02 PM <[email protected]> wrote:
>>>>>
>>>>> On 7/12/22 19:38, Sudip Mukherjee wrote:
>>>>>> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>>
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> Some flash chips which does not have a SFDP table can support Quad
>>>>>> Input Page Program. Enable it in hwcaps if defined.
>>>>>>
>>>>
>>>> <snip>
>>>>
>>>>>> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
>>>>>> index 58fbedc94080f..dde636bdb1a7c 100644
>>>>>> --- a/drivers/mtd/spi-nor/core.h
>>>>>> +++ b/drivers/mtd/spi-nor/core.h
>>>>>> @@ -462,6 +462,7 @@ struct spi_nor_fixups {
>>>>>> * SPI_NOR_OCTAL_READ: flash supports Octal Read.
>>>>>> * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read.
>>>>>> * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program.
>>>>>> + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
>>>>>
>>>>> You don't need this flag if your flash supports the 4-byte Address
>>>>> Instruction Table. Does you flash support it? Can you dump all the
>>>>> SFDP tables, please?
>>>>
>>>> Not sure what the correct way to dump sfdp is. I did this from sysfs.
>>>
>>> I tried decoding this SFDP table and I think the parameters table says
>>> it has "3-Byte only addressing".
>>> So, I guess that means it does not support 4-byte Address Instruction
>>> Table. And the datasheet
>>> says it supports "Quad Input Page Program (3-byte Address)".
>>> My existing patchset works for Quad Input Page Program, and I can send
>>> a v2 with the previous
>>> patch and this merged together (as you suggested) or I can try
>>> enabling sfdp for this chip and then use
>>
>> You should definitely enable SFDP and get rid of the NO_SFDP_FLAGS flags,
>> regardless of the 1-1-4 PP outcome.
>>
>>> a fixup_flags to enable "Quad Input Page Program" which I think will
>>> be more complicated.
>>> Which one will you suggest?
>>>
>>
>> First I'd like to understand what "much better performance" means. Would
>> you run some speed tests please? mtd-utils should have a speedtest, otherwise
>> you can use the in kernel mtd_speedtest module. Page programs are slow anyway,
>> using 4 lines may not make any difference. But let's see.
>>
>> About your question, it depends on how common is 1-1-4 pp. If it's common and
>> desirable we can introduce a flash info flag.
>
> We have an issue with the SPI controller where if it isn't in the above
> 1 bit modes it has to block the CPU as the feature to hold the clock is
> not enabled in the 1bit "old" modes. In the old modes, if the FIFO gets
> to the empty stage then the CS gets de-selected. If we can enable the
> 4bit mode, we can also set the clock-suspend flag which means the code
> does not have to block the core it is running on to ensure it gets the
> data out in time.
I'm not sure I understood your SPI controller limitation, but shouldn't
matter from a flash point of view anyway.
>
> At the moment speed tests are not easy as we are on entirely emulated
> hardware, we could try some but the results may not represent what the
> real chip can perform.
Ok, then ignore the speed test suggestion. I've shuffled few vendor datasheets
and micron seems to use 1-1-4 PP too.
So I suggest to add SPI_NOR_QUAD_PP under nor->info->flags because 1-1-4 PP
is not SFDP discoverable. SPINOR_OP_PP_1_1_4_4B is and can be retrieved from
SFDP by parsing 4BAIT.
And please get rid of the no-sfdp-flags from the flash definition and use
instead PARSE_SFDP.
--
Cheers,
ta