From: Michael Clark <[email protected]>
Update the RISC-V port to use the generic qspinlock and qrwlock.
This patch requires support for xchg for short which are added by
a previous patch.
Guo fixed up compile error which made by below include sequence:
+#include <asm/qrwlock.h>
+#include <asm/qspinlock.h>
Signed-off-by: Michael Clark <[email protected]>
Co-developed-by: Guo Ren <[email protected]>
Tested-by: Guo Ren <[email protected]>
Link: https://lore.kernel.org/linux-riscv/[email protected]/
Cc: Peter Zijlstra <[email protected]>
Cc: Anup Patel <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
---
arch/riscv/Kconfig | 2 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
4 files changed, 10 insertions(+), 136 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 87d7b52f278f..c78b8b0ccf96 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -33,6 +33,8 @@ config RISCV
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
+ select ARCH_USE_QUEUED_RWLOCKS
+ select ARCH_USE_QUEUED_SPINLOCKS
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
index 445ccc97305a..750c1056b90f 100644
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
@@ -3,5 +3,8 @@ generic-y += early_ioremap.h
generic-y += extable.h
generic-y += flat.h
generic-y += kvm_para.h
+generic-y += mcs_spinlock.h
+generic-y += qrwlock.h
+generic-y += qspinlock.h
generic-y += user.h
generic-y += vmlinux.lds.h
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
index f4f7fa1b7ca8..a557de67a425 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/spinlock.h
@@ -7,129 +7,7 @@
#ifndef _ASM_RISCV_SPINLOCK_H
#define _ASM_RISCV_SPINLOCK_H
-#include <linux/kernel.h>
-#include <asm/current.h>
-#include <asm/fence.h>
-
-/*
- * Simple spin lock operations. These provide no fairness guarantees.
- */
-
-/* FIXME: Replace this with a ticket lock, like MIPS. */
-
-#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int tmp = 1, busy;
-
- __asm__ __volatile__ (
- " amoswap.w %0, %2, %1\n"
- RISCV_ACQUIRE_BARRIER
- : "=r" (busy), "+A" (lock->lock)
- : "r" (tmp)
- : "memory");
-
- return !busy;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- while (1) {
- if (arch_spin_is_locked(lock))
- continue;
-
- if (arch_spin_trylock(lock))
- break;
- }
-}
-
-/***********************************************************/
-
-static inline void arch_read_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1b\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline void arch_write_lock(arch_rwlock_t *lock)
-{
- int tmp;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1b\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- : "+A" (lock->lock), "=&r" (tmp)
- :: "memory");
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bltz %1, 1f\n"
- " addi %1, %1, 1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- int busy;
-
- __asm__ __volatile__(
- "1: lr.w %1, %0\n"
- " bnez %1, 1f\n"
- " li %1, -1\n"
- " sc.w %1, %1, %0\n"
- " bnez %1, 1b\n"
- RISCV_ACQUIRE_BARRIER
- "1:\n"
- : "+A" (lock->lock), "=&r" (busy)
- :: "memory");
-
- return !busy;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *lock)
-{
- __asm__ __volatile__(
- RISCV_RELEASE_BARRIER
- " amoadd.w x0, %1, %0\n"
- : "+A" (lock->lock)
- : "r" (-1)
- : "memory");
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *lock)
-{
- smp_store_release(&lock->lock, 0);
-}
+#include <asm/qspinlock.h>
+#include <asm/qrwlock.h>
#endif /* _ASM_RISCV_SPINLOCK_H */
diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h
index f398e7638dd6..d033a973f287 100644
--- a/arch/riscv/include/asm/spinlock_types.h
+++ b/arch/riscv/include/asm/spinlock_types.h
@@ -6,20 +6,11 @@
#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
#define _ASM_RISCV_SPINLOCK_TYPES_H
-#ifndef __LINUX_SPINLOCK_TYPES_H
+#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(_ASM_RISCV_SPINLOCK_H)
# error "please don't include this file directly"
#endif
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
+#include <asm-generic/qspinlock_types.h>
+#include <asm-generic/qrwlock_types.h>
#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
--
2.17.1
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/locking/core]
[also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
config: riscv-rv32_defconfig (attached as .config)
compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
kernel/locking/qspinlock.c: Assembler messages:
kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
>> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
>> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
>> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
vim +190 kernel/locking/qspinlock.c
69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
59fb586b4a07b4 Will Deacon 2018-04-26 193 */
59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
59fb586b4a07b4 Will Deacon 2018-04-26 195 {
59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
59fb586b4a07b4 Will Deacon 2018-04-26 197 }
59fb586b4a07b4 Will Deacon 2018-04-26 198
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
haha, I forgot RV32, it needs a
#ifdef RV32
srliw
#else
srli
#endif
On Thu, Mar 25, 2021 at 7:16 PM kernel test robot <[email protected]> wrote:
>
> Hi,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on tip/locking/core]
> [also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
> config: riscv-rv32_defconfig (attached as .config)
> compiler: riscv32-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <[email protected]>
>
> All errors (new ones prefixed by >>):
>
> kernel/locking/qspinlock.c: Assembler messages:
> kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
> kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
> >> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
> >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
> kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
> kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
> >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
>
>
> vim +190 kernel/locking/qspinlock.c
>
> 69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
> 59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
> 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
> 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
> 59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
> 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
> 59fb586b4a07b4 Will Deacon 2018-04-26 193 */
> 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
> 59fb586b4a07b4 Will Deacon 2018-04-26 195 {
> 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
> 59fb586b4a07b4 Will Deacon 2018-04-26 197 }
> 59fb586b4a07b4 Will Deacon 2018-04-26 198
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/[email protected]
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 5ca41152cf4b..894e170c503e 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -17,6 +17,14 @@
#define __local_release_fence()
\
__asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory")
+#ifdef CONFIG_32BIT
+#define __ASM_SLLIW "slli\t"
+#define __ASM_SRLIW "srli\t"
+#else
+#define __ASM_SLLIW "slliw\t"
+#define __ASM_SRLIW "srliw\t"
+#endif
+
#define __xchg_relaxed(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -31,14 +39,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " slliw %1, %1, 16 \n" \
- " srliw %1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
- " slliw %2, %2, 16 \n" \
+ __ASM_SLLIW "%2, %2, 16 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, (%4) \n" \
" bnez %2, 0b \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
@@ -46,14 +54,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " srliw %1, %1, 16 \n" \
- " slliw %1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, 0(%4) \n" \
" bnez %2, 0b \n" \
- " slliw %0, %0, 16 \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SLLIW "%0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
On Thu, Mar 25, 2021 at 7:34 PM Guo Ren <[email protected]> wrote:
>
> haha, I forgot RV32, it needs a
>
> #ifdef RV32
> srliw
> #else
> srli
> #endif
>
> On Thu, Mar 25, 2021 at 7:16 PM kernel test robot <[email protected]> wrote:
> >
> > Hi,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on tip/locking/core]
> > [also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
> >
> > url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
> > config: riscv-rv32_defconfig (attached as .config)
> > compiler: riscv32-linux-gcc (GCC) 9.3.0
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
> > git remote add linux-review https://github.com/0day-ci/linux
> > git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> > git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
> > # save the attached .config to linux build tree
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <[email protected]>
> >
> > All errors (new ones prefixed by >>):
> >
> > kernel/locking/qspinlock.c: Assembler messages:
> > kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
> > kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
> > >> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
> > >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> > kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
> > kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
> > kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
> > >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> >
> >
> > vim +190 kernel/locking/qspinlock.c
> >
> > 69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
> > 59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
> > 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
> > 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
> > 59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
> > 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
> > 59fb586b4a07b4 Will Deacon 2018-04-26 193 */
> > 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
> > 59fb586b4a07b4 Will Deacon 2018-04-26 195 {
> > 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
> > 59fb586b4a07b4 Will Deacon 2018-04-26 197 }
> > 59fb586b4a07b4 Will Deacon 2018-04-26 198
> >
> > ---
> > 0-DAY CI Kernel Test Service, Intel Corporation
> > https://lists.01.org/hyperkitty/list/[email protected]
>
>
>
> --
> Best Regards
> Guo Ren
>
> ML: https://lore.kernel.org/linux-csky/
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/