Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
are typically used to read/write from/to memory mapped registers
and can cause hangs or some undefined behaviour in following cases,
* If the access to the register space is unclocked, for example: if
there is an access to multimedia(MM) block registers without MM
clocks.
* If the register space is protected and not set to be accessible from
non-secure world, for example: only EL3 (EL: Exception level) access
is allowed and any EL2/EL1 access is forbidden.
* If xPU(memory/register protection units) is controlling access to
certain memory/register space for specific clients.
and more...
Such cases usually results in instant reboot/SErrors/NOC or interconnect
hangs and tracing these register accesses can be very helpful to debug
such issues during initial development stages and also in later stages.
So use ftrace trace events to log such MMIO register accesses which
provides rich feature set such as early enablement of trace events,
filtering capability, dumping ftrace logs on console and many more.
Sample output:
rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610
This series is a follow-up for the series [1] and a recent series [2] making use
of both.
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
Note in previous v4 version, Arnd suggested to benchmark and compare size with callback
based implementation, please see [3] for more details on that with brief comparison below.
**Inline version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
$ size vmlinux
text data bss dec hex filename
23884219 14284468 532568 38701255 24e88c7 vmlinux
**Callback version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
$ size vmlinux
text data bss dec hex filename
24108179 14279596 532568 38920343 251e097 vmlinux
$ ./scripts/bloat-o-meter inline-vmlinux callback-vmlinux
add/remove: 8/3 grow/shrink: 4889/89 up/down: 242244/-11564 (230680)
Total: Before=25812612, After=26043292, chg +0.89%
[3] https://lore.kernel.org/lkml/[email protected]/
Changes in v10:
* Use GENMASK(31, 0) for -Woverflow warning in irqchip tegra driver (Marc).
* Convert ETM4x ARM64 driver to use asm-generic IO memory barriers (Catalin).
* Collect ack from Catalin for arm64 change.
Changes in v9:
* Use TRACE_EVENT_CLASS for rwmmio_write and post_write (Steven Rostedt).
Changes in v8:
* Fix build error reported by kernel test robot.
Changes in v7:
* Use lib/ instead of kernel/trace/ based on review comment by Steven Rostedt.
Changes in v6:
* Implemented suggestions by Arnd Bergmann:
- Use arch independent IO barriers in arm64/asm
- Add ARCH_HAVE_TRACE_MMIO_ACCESS
- Add post read and post write logging support
- Remove tracepoint_active check
* Fix build error reported by kernel test robot.
Changes in v5:
* Move arm64 to use asm-generic provided high level MMIO accessors (Arnd).
* Add inline logging for MMIO relaxed and non-relaxed accessors.
* Move nVHE KVM comment to makefile (Marc).
* Fix overflow warning due to switch to inline accessors instead of macro.
* Modify trace event field to include caller and parent details for more detailed logs.
Changes in v4:
* Drop dynamic debug based filter support since that will be developed later with
the help from Steven (Ftrace maintainer).
* Drop value passed to writel as it is causing hangs when tracing is enabled.
* Code cleanup for trace event as suggested by Steven for earlier version.
* Fixed some build errors reported by 0-day bot.
Changes in v3:
* Create a generic mmio header for instrumented version (Earlier suggested in [1]
by Will Deacon and recently [2] by Greg to have a generic version first).
* Add dynamic debug support to filter out traces which can be very useful for targeted
debugging specific to subsystems or drivers.
* Few modifications to the rwmmio trace event fields to include the mmio width and print
addresses in hex.
* Rewrote commit msg to explain some more about usecases.
Prasad Sodagudi (1):
lib: Add register read/write tracing support
Sai Prakash Ranjan (5):
arm64: io: Use asm-generic high level MMIO accessors
coresight: etm4x: Use asm-generic IO memory barriers
irqchip/tegra: Fix overflow implicit truncation warnings
drm/meson: Fix overflow implicit truncation warnings
asm-generic/io: Add logging support for MMIO accessors
arch/Kconfig | 3 +
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/io.h | 41 ++------
arch/arm64/kvm/hyp/nvhe/Makefile | 7 +-
drivers/gpu/drm/meson/meson_viu.c | 22 ++---
.../coresight/coresight-etm4x-core.c | 8 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 8 +-
drivers/irqchip/irq-tegra.c | 10 +-
include/asm-generic/io.h | 82 +++++++++++++++-
include/trace/events/rwmmio.h | 97 +++++++++++++++++++
lib/Kconfig | 7 ++
lib/Makefile | 2 +
lib/trace_readwrite.c | 47 +++++++++
13 files changed, 273 insertions(+), 62 deletions(-)
create mode 100644 include/trace/events/rwmmio.h
create mode 100644 lib/trace_readwrite.c
base-commit: 754e0b0e35608ed5206d6a67a791563c631cec07
--
2.33.1
Add logging support for MMIO high level accessors such as read{b,w,l,q}
and their relaxed versions to aid in debugging unexpected crashes/hangs
caused by the corresponding MMIO operation. Also add a generic flag
(__DISABLE_TRACE_MMIO__) which is used to disable MMIO tracing in nVHE KVM
and if required can be used to disable MMIO tracing for specific drivers.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
arch/arm64/kvm/hyp/nvhe/Makefile | 7 ++-
include/asm-generic/io.h | 82 ++++++++++++++++++++++++++++++--
2 files changed, 84 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile
index 24b2c2425b38..228d1f8921c3 100644
--- a/arch/arm64/kvm/hyp/nvhe/Makefile
+++ b/arch/arm64/kvm/hyp/nvhe/Makefile
@@ -4,7 +4,12 @@
#
asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS
-ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS
+
+# Tracepoint and MMIO logging symbols should not be visible at nVHE KVM as
+# there is no way to execute them and any such MMIO access from nVHE KVM
+# will explode instantly (Words of Marc Zyngier). So introduce a generic flag
+# __DISABLE_TRACE_MMIO__ to disable MMIO tracing for nVHE KVM.
+ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__
hostprogs := gen-hyprel
HOST_EXTRACFLAGS += -I$(objtree)/include
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 7ce93aaf69f8..c9b428657760 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -10,6 +10,7 @@
#include <asm/page.h> /* I/O is all done through memory accesses */
#include <linux/string.h> /* for memset() and memcpy() */
#include <linux/types.h>
+#include <linux/instruction_pointer.h>
#ifdef CONFIG_GENERIC_IOMAP
#include <asm-generic/iomap.h>
@@ -61,6 +62,35 @@
#define __io_par(v) __io_ar(v)
#endif
+#if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRACE_MMIO__))
+#include <linux/tracepoint-defs.h>
+
+DECLARE_TRACEPOINT(rwmmio_write);
+DECLARE_TRACEPOINT(rwmmio_post_write);
+DECLARE_TRACEPOINT(rwmmio_read);
+DECLARE_TRACEPOINT(rwmmio_post_read);
+
+void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+ unsigned long caller_addr);
+void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+ unsigned long caller_addr);
+void log_read_mmio(u8 width, const volatile void __iomem *addr,
+ unsigned long caller_addr);
+void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
+ unsigned long caller_addr);
+
+#else
+
+static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+ unsigned long caller_addr) {}
+static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+ unsigned long caller_addr) {}
+static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,
+ unsigned long caller_addr) {}
+static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
+ unsigned long caller_addr) {}
+
+#endif /* CONFIG_TRACE_MMIO_ACCESS */
/*
* __raw_{read,write}{b,w,l,q}() access memory in native endianness.
@@ -149,9 +179,11 @@ static inline u8 readb(const volatile void __iomem *addr)
{
u8 val;
+ log_read_mmio(8, addr, _THIS_IP_);
__io_br();
val = __raw_readb(addr);
__io_ar(val);
+ log_post_read_mmio(val, 8, addr, _THIS_IP_);
return val;
}
#endif
@@ -162,9 +194,11 @@ static inline u16 readw(const volatile void __iomem *addr)
{
u16 val;
+ log_read_mmio(16, addr, _THIS_IP_);
__io_br();
val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
__io_ar(val);
+ log_post_read_mmio(val, 16, addr, _THIS_IP_);
return val;
}
#endif
@@ -175,9 +209,11 @@ static inline u32 readl(const volatile void __iomem *addr)
{
u32 val;
+ log_read_mmio(32, addr, _THIS_IP_);
__io_br();
val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
__io_ar(val);
+ log_post_read_mmio(val, 32, addr, _THIS_IP_);
return val;
}
#endif
@@ -189,9 +225,11 @@ static inline u64 readq(const volatile void __iomem *addr)
{
u64 val;
+ log_read_mmio(64, addr, _THIS_IP_);
__io_br();
val = __le64_to_cpu(__raw_readq(addr));
__io_ar(val);
+ log_post_read_mmio(val, 64, addr, _THIS_IP_);
return val;
}
#endif
@@ -201,9 +239,11 @@ static inline u64 readq(const volatile void __iomem *addr)
#define writeb writeb
static inline void writeb(u8 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 8, addr, _THIS_IP_);
__io_bw();
__raw_writeb(value, addr);
__io_aw();
+ log_post_write_mmio(value, 8, addr, _THIS_IP_);
}
#endif
@@ -211,9 +251,11 @@ static inline void writeb(u8 value, volatile void __iomem *addr)
#define writew writew
static inline void writew(u16 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 16, addr, _THIS_IP_);
__io_bw();
__raw_writew((u16 __force)cpu_to_le16(value), addr);
__io_aw();
+ log_post_write_mmio(value, 16, addr, _THIS_IP_);
}
#endif
@@ -221,9 +263,11 @@ static inline void writew(u16 value, volatile void __iomem *addr)
#define writel writel
static inline void writel(u32 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 32, addr, _THIS_IP_);
__io_bw();
__raw_writel((u32 __force)__cpu_to_le32(value), addr);
__io_aw();
+ log_post_write_mmio(value, 32, addr, _THIS_IP_);
}
#endif
@@ -232,9 +276,11 @@ static inline void writel(u32 value, volatile void __iomem *addr)
#define writeq writeq
static inline void writeq(u64 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 64, addr, _THIS_IP_);
__io_bw();
__raw_writeq(__cpu_to_le64(value), addr);
__io_aw();
+ log_post_write_mmio(value, 64, addr, _THIS_IP_);
}
#endif
#endif /* CONFIG_64BIT */
@@ -248,7 +294,12 @@ static inline void writeq(u64 value, volatile void __iomem *addr)
#define readb_relaxed readb_relaxed
static inline u8 readb_relaxed(const volatile void __iomem *addr)
{
- return __raw_readb(addr);
+ u8 val;
+
+ log_read_mmio(8, addr, _THIS_IP_);
+ val = __raw_readb(addr);
+ log_post_read_mmio(val, 8, addr, _THIS_IP_);
+ return val;
}
#endif
@@ -256,7 +307,12 @@ static inline u8 readb_relaxed(const volatile void __iomem *addr)
#define readw_relaxed readw_relaxed
static inline u16 readw_relaxed(const volatile void __iomem *addr)
{
- return __le16_to_cpu(__raw_readw(addr));
+ u16 val;
+
+ log_read_mmio(16, addr, _THIS_IP_);
+ val = __le16_to_cpu(__raw_readw(addr));
+ log_post_read_mmio(val, 16, addr, _THIS_IP_);
+ return val;
}
#endif
@@ -264,7 +320,12 @@ static inline u16 readw_relaxed(const volatile void __iomem *addr)
#define readl_relaxed readl_relaxed
static inline u32 readl_relaxed(const volatile void __iomem *addr)
{
- return __le32_to_cpu(__raw_readl(addr));
+ u32 val;
+
+ log_read_mmio(32, addr, _THIS_IP_);
+ val = __le32_to_cpu(__raw_readl(addr));
+ log_post_read_mmio(val, 32, addr, _THIS_IP_);
+ return val;
}
#endif
@@ -272,7 +333,12 @@ static inline u32 readl_relaxed(const volatile void __iomem *addr)
#define readq_relaxed readq_relaxed
static inline u64 readq_relaxed(const volatile void __iomem *addr)
{
- return __le64_to_cpu(__raw_readq(addr));
+ u64 val;
+
+ log_read_mmio(64, addr, _THIS_IP_);
+ val = __le64_to_cpu(__raw_readq(addr));
+ log_post_read_mmio(val, 64, addr, _THIS_IP_);
+ return val;
}
#endif
@@ -280,7 +346,9 @@ static inline u64 readq_relaxed(const volatile void __iomem *addr)
#define writeb_relaxed writeb_relaxed
static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 8, addr, _THIS_IP_);
__raw_writeb(value, addr);
+ log_post_write_mmio(value, 8, addr, _THIS_IP_);
}
#endif
@@ -288,7 +356,9 @@ static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
#define writew_relaxed writew_relaxed
static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 16, addr, _THIS_IP_);
__raw_writew(cpu_to_le16(value), addr);
+ log_post_write_mmio(value, 16, addr, _THIS_IP_);
}
#endif
@@ -296,7 +366,9 @@ static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
#define writel_relaxed writel_relaxed
static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 32, addr, _THIS_IP_);
__raw_writel(__cpu_to_le32(value), addr);
+ log_post_write_mmio(value, 32, addr, _THIS_IP_);
}
#endif
@@ -304,7 +376,9 @@ static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
#define writeq_relaxed writeq_relaxed
static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
{
+ log_write_mmio(value, 64, addr, _THIS_IP_);
__raw_writeq(__cpu_to_le64(value), addr);
+ log_post_write_mmio(value, 64, addr, _THIS_IP_);
}
#endif
--
2.33.1
From: Prasad Sodagudi <[email protected]>
Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
are typically used to read/write from/to memory mapped registers
and can cause hangs or some undefined behaviour in following few
cases,
* If the access to the register space is unclocked, for example: if
there is an access to multimedia(MM) block registers without MM
clocks.
* If the register space is protected and not set to be accessible from
non-secure world, for example: only EL3 (EL: Exception level) access
is allowed and any EL2/EL1 access is forbidden.
* If xPU(memory/register protection units) is controlling access to
certain memory/register space for specific clients.
and more...
Such cases usually results in instant reboot/SErrors/NOC or interconnect
hangs and tracing these register accesses can be very helpful to debug
such issues during initial development stages and also in later stages.
So use ftrace trace events to log such MMIO register accesses which
provides rich feature set such as early enablement of trace events,
filtering capability, dumping ftrace logs on console and many more.
Sample output:
rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610
Signed-off-by: Prasad Sodagudi <[email protected]>
Co-developed-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
arch/Kconfig | 3 ++
arch/arm64/Kconfig | 1 +
include/trace/events/rwmmio.h | 97 +++++++++++++++++++++++++++++++++++
lib/Kconfig | 7 +++
lib/Makefile | 2 +
lib/trace_readwrite.c | 47 +++++++++++++++++
6 files changed, 157 insertions(+)
create mode 100644 include/trace/events/rwmmio.h
create mode 100644 lib/trace_readwrite.c
diff --git a/arch/Kconfig b/arch/Kconfig
index 678a80713b21..efbbc36658dc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1315,6 +1315,9 @@ config ARCH_HAS_ELFCORE_COMPAT
config ARCH_HAS_PARANOID_L1D_FLUSH
bool
+config ARCH_HAVE_TRACE_MMIO_ACCESS
+ bool
+
config DYNAMIC_SIGFRAME
bool
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 09b885cc4db5..321ae97df987 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -46,6 +46,7 @@ config ARM64
select ARCH_HAS_ZONE_DMA_SET if EXPERT
select ARCH_HAVE_ELF_PROT
select ARCH_HAVE_NMI_SAFE_CMPXCHG
+ select ARCH_HAVE_TRACE_MMIO_ACCESS
select ARCH_INLINE_READ_LOCK if !PREEMPTION
select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
diff --git a/include/trace/events/rwmmio.h b/include/trace/events/rwmmio.h
new file mode 100644
index 000000000000..3c3fefbef87d
--- /dev/null
+++ b/include/trace/events/rwmmio.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM rwmmio
+
+#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_RWMMIO_H
+
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(rwmmio_rw_template,
+
+ TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+
+ TP_ARGS(caller, val, width, addr),
+
+ TP_STRUCT__entry(
+ __field(u64, caller)
+ __field(u64, val)
+ __field(u64, addr)
+ __field(u8, width)
+ ),
+
+ TP_fast_assign(
+ __entry->caller = caller;
+ __entry->val = val;
+ __entry->addr = (unsigned long)(void *)addr;
+ __entry->width = width;
+ ),
+
+ TP_printk("%pS width=%d val=%#llx addr=%#llx",
+ (void *)(unsigned long)__entry->caller, __entry->width,
+ __entry->val, __entry->addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
+ TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+ TP_ARGS(caller, val, width, addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
+ TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+ TP_ARGS(caller, val, width, addr)
+);
+
+TRACE_EVENT(rwmmio_read,
+
+ TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
+
+ TP_ARGS(caller, width, addr),
+
+ TP_STRUCT__entry(
+ __field(u64, caller)
+ __field(u64, addr)
+ __field(u8, width)
+ ),
+
+ TP_fast_assign(
+ __entry->caller = caller;
+ __entry->addr = (unsigned long)(void *)addr;
+ __entry->width = width;
+ ),
+
+ TP_printk("%pS width=%d addr=%#llx",
+ (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)
+);
+
+TRACE_EVENT(rwmmio_post_read,
+
+ TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
+
+ TP_ARGS(caller, val, width, addr),
+
+ TP_STRUCT__entry(
+ __field(u64, caller)
+ __field(u64, val)
+ __field(u64, addr)
+ __field(u8, width)
+ ),
+
+ TP_fast_assign(
+ __entry->caller = caller;
+ __entry->val = val;
+ __entry->addr = (unsigned long)(void *)addr;
+ __entry->width = width;
+ ),
+
+ TP_printk("%pS width=%d val=%#llx addr=%#llx",
+ (void *)(unsigned long)__entry->caller, __entry->width,
+ __entry->val, __entry->addr)
+);
+
+#endif /* _TRACE_RWMMIO_H */
+
+#include <trace/define_trace.h>
diff --git a/lib/Kconfig b/lib/Kconfig
index c80fde816a7e..ea520c315c0f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -119,6 +119,13 @@ config INDIRECT_IOMEM_FALLBACK
mmio accesses when the IO memory address is not a registered
emulated region.
+config TRACE_MMIO_ACCESS
+ bool "Register read/write tracing"
+ depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
+ help
+ Create tracepoints for MMIO read/write operations. These trace events
+ can be used for logging all MMIO read/write operations.
+
source "lib/crypto/Kconfig"
config CRC_CCITT
diff --git a/lib/Makefile b/lib/Makefile
index 300f569c626b..43813b0061cd 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -152,6 +152,8 @@ lib-y += logic_pio.o
lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
+obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
+
obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
obj-$(CONFIG_BTREE) += btree.o
diff --git a/lib/trace_readwrite.c b/lib/trace_readwrite.c
new file mode 100644
index 000000000000..88637038b30c
--- /dev/null
+++ b/lib/trace_readwrite.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Register read and write tracepoints
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/ftrace.h>
+#include <linux/module.h>
+#include <asm-generic/io.h>
+
+#define CREATE_TRACE_POINTS
+#include <trace/events/rwmmio.h>
+
+#ifdef CONFIG_TRACE_MMIO_ACCESS
+void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+ unsigned long caller_addr)
+{
+ trace_rwmmio_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
+
+void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+ unsigned long caller_addr)
+{
+ trace_rwmmio_post_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
+
+void log_read_mmio(u8 width, const volatile void __iomem *addr,
+ unsigned long caller_addr)
+{
+ trace_rwmmio_read(caller_addr, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
+
+void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
+ unsigned long caller_addr)
+{
+ trace_rwmmio_post_read(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
+#endif /* CONFIG_TRACE_MMIO_ACCESS */
--
2.33.1
Per discussion in [1], it was decided to move to using architecture
independent/asm-generic IO memory barriers to have just one set of
them and deprecate use of arm64 specific IO memory barriers in driver
code. So replace current usage of __io_rmb()/__iowmb() in drivers to
__io_ar()/__io_bw().
[1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/
Cc: Catalin Marinas <[email protected]>
Cc: Mathieu Poirier <[email protected]>
Cc: Suzuki K Poulose <[email protected]>
Cc: Mike Leach <[email protected]>
Cc: [email protected]
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++----
drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index bf18128cf5de..89ba7bb4c41d 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -98,7 +98,7 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
}
if (!_relaxed)
- __iormb(res); /* Imitate the !relaxed I/O helpers */
+ __io_ar(res); /* Imitate the !relaxed I/O helpers */
return res;
}
@@ -106,7 +106,7 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
{
if (!_relaxed)
- __iowmb(); /* Imitate the !relaxed I/O helpers */
+ __io_bw(); /* Imitate the !relaxed I/O helpers */
if (!_64bit)
val &= GENMASK(31, 0);
@@ -130,7 +130,7 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
}
if (!_relaxed)
- __iormb(res); /* Imitate the !relaxed I/O helpers */
+ __io_ar(res); /* Imitate the !relaxed I/O helpers */
return res;
}
@@ -138,7 +138,7 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
{
if (!_relaxed)
- __iowmb(); /* Imitate the !relaxed I/O helpers */
+ __io_bw(); /* Imitate the !relaxed I/O helpers */
if (!_64bit)
val &= GENMASK(31, 0);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 3c4d69b096ca..f54698731582 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -448,14 +448,14 @@
#define etm4x_read32(csa, offset) \
({ \
u32 __val = etm4x_relaxed_read32((csa), (offset)); \
- __iormb(__val); \
+ __io_ar(__val); \
__val; \
})
#define etm4x_read64(csa, offset) \
({ \
u64 __val = etm4x_relaxed_read64((csa), (offset)); \
- __iormb(__val); \
+ __io_ar(__val); \
__val; \
})
@@ -479,13 +479,13 @@
#define etm4x_write32(csa, val, offset) \
do { \
- __iowmb(); \
+ __io_bw(); \
etm4x_relaxed_write32((csa), (val), (offset)); \
} while (0)
#define etm4x_write64(csa, val, offset) \
do { \
- __iowmb(); \
+ __io_bw(); \
etm4x_relaxed_write64((csa), (val), (offset)); \
} while (0)
--
2.33.1
Fix -Woverflow warnings for drm/meson driver which is a result
of moving arm64 custom MMIO accessor macros to asm-generic function
implementations giving a bonus type-checking now and uncovering these
overflow warnings.
drivers/gpu/drm/meson/meson_viu.c: In function ‘meson_viu_init’:
drivers/gpu/drm/meson/meson_registers.h:1826:48: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
#define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
^
drivers/gpu/drm/meson/meson_viu.c:472:18: note: in expansion of macro ‘VIU_OSD_BLEND_REORDER’
writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
^~~~~~~~~~~~~~~~~~~~~
Cc: Arnd Bergmann <[email protected]>
Cc: Neil Armstrong <[email protected]>
Reported-by: kernel test robot <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
drivers/gpu/drm/meson/meson_viu.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index 259f3e6bec90..bb7e109534de 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -469,17 +469,17 @@ void meson_viu_init(struct meson_drm *priv)
priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
- writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
- VIU_OSD_BLEND_REORDER(1, 0) |
- VIU_OSD_BLEND_REORDER(2, 0) |
- VIU_OSD_BLEND_REORDER(3, 0) |
- VIU_OSD_BLEND_DIN_EN(1) |
- VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
- VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
- VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
- VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
- VIU_OSD_BLEND_HOLD_LINES(4),
- priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
+ u32 val = (u32)VIU_OSD_BLEND_REORDER(0, 1) |
+ (u32)VIU_OSD_BLEND_REORDER(1, 0) |
+ (u32)VIU_OSD_BLEND_REORDER(2, 0) |
+ (u32)VIU_OSD_BLEND_REORDER(3, 0) |
+ (u32)VIU_OSD_BLEND_DIN_EN(1) |
+ (u32)VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
+ (u32)VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
+ (u32)VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
+ (u32)VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
+ (u32)VIU_OSD_BLEND_HOLD_LINES(4);
+ writel_relaxed(val, priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
--
2.33.1
Fix -Woverflow warnings for tegra irqchip driver which is a result
of moving arm64 custom MMIO accessor macros to asm-generic function
implementations giving a bonus type-checking now and uncovering these
overflow warnings.
drivers/irqchip/irq-tegra.c: In function ‘tegra_ictlr_suspend’:
drivers/irqchip/irq-tegra.c:151:18: warning: large integer implicitly truncated to unsigned type [-Woverflow]
writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
^
Cc: Marc Zyngier <[email protected]>
Suggested-by: Marc Zyngier <[email protected]>
Reviewed-by: Arnd Bergmann <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
drivers/irqchip/irq-tegra.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
index e1f771c72fc4..ad3e2c1b3c87 100644
--- a/drivers/irqchip/irq-tegra.c
+++ b/drivers/irqchip/irq-tegra.c
@@ -148,10 +148,10 @@ static int tegra_ictlr_suspend(void)
lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
/* Disable COP interrupts */
- writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+ writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
/* Disable CPU interrupts */
- writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+ writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
/* Enable the wakeup sources of ictlr */
writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
@@ -172,12 +172,12 @@ static void tegra_ictlr_resume(void)
writel_relaxed(lic->cpu_iep[i],
ictlr + ICTLR_CPU_IEP_CLASS);
- writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+ writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
writel_relaxed(lic->cpu_ier[i],
ictlr + ICTLR_CPU_IER_SET);
writel_relaxed(lic->cop_iep[i],
ictlr + ICTLR_COP_IEP_CLASS);
- writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+ writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
writel_relaxed(lic->cop_ier[i],
ictlr + ICTLR_COP_IER_SET);
}
@@ -312,7 +312,7 @@ static int __init tegra_ictlr_init(struct device_node *node,
lic->base[i] = base;
/* Disable all interrupts */
- writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
+ writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);
/* All interrupts target IRQ */
writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
--
2.33.1
On Thu, 24 Feb 2022 11:37:07 +0530
Sai Prakash Ranjan <[email protected]> wrote:
> --- /dev/null
> +++ b/include/trace/events/rwmmio.h
> @@ -0,0 +1,97 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +#undef TRACE_SYSTEM
> +#define TRACE_SYSTEM rwmmio
> +
> +#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ)
> +#define _TRACE_RWMMIO_H
> +
> +#include <linux/tracepoint.h>
> +
> +DECLARE_EVENT_CLASS(rwmmio_rw_template,
> +
> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
> +
> + TP_ARGS(caller, val, width, addr),
> +
> + TP_STRUCT__entry(
> + __field(u64, caller)
> + __field(u64, val)
> + __field(u64, addr)
So caller and addr are both pointers. Why not define them as unsigned long?
That will save 8 bytes on 32 bit machines.
__field(unsigned long, caller)
__field(unsigned long, addr)
__feild(u64, val)
to keep the longs together as on 32 bit, it will be better aligned.
The tracing tools can handle the difference from user space. Even when
reading trace files from 32 bit architectures on 64 bit machines, and vise
versa.
> + __field(u8, width)
> + ),
> +
> + TP_fast_assign(
> + __entry->caller = caller;
> + __entry->val = val;
> + __entry->addr = (unsigned long)(void *)addr;
> + __entry->width = width;
> + ),
> +
> + TP_printk("%pS width=%d val=%#llx addr=%#llx",
> + (void *)(unsigned long)__entry->caller, __entry->width,
> + __entry->val, __entry->addr)
> +);
> +
> +DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
> + TP_ARGS(caller, val, width, addr)
> +);
> +
> +DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
> + TP_ARGS(caller, val, width, addr)
> +);
> +
> +TRACE_EVENT(rwmmio_read,
> +
> + TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
> +
> + TP_ARGS(caller, width, addr),
> +
> + TP_STRUCT__entry(
> + __field(u64, caller)
> + __field(u64, addr)
Same here.
-- Steve
> + __field(u8, width)
> + ),
> +
> + TP_fast_assign(
> + __entry->caller = caller;
> + __entry->addr = (unsigned long)(void *)addr;
> + __entry->width = width;
> + ),
> +
> + TP_printk("%pS width=%d addr=%#llx",
> + (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)
> +);
> +
> +TRACE_EVENT(rwmmio_post_read,
> +
> + TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
> +
> + TP_ARGS(caller, val, width, addr),
> +
> + TP_STRUCT__entry(
> + __field(u64, caller)
> + __field(u64, val)
> + __field(u64, addr)
> + __field(u8, width)
> + ),
> +
> + TP_fast_assign(
> + __entry->caller = caller;
> + __entry->val = val;
> + __entry->addr = (unsigned long)(void *)addr;
> + __entry->width = width;
> + ),
> +
> + TP_printk("%pS width=%d val=%#llx addr=%#llx",
> + (void *)(unsigned long)__entry->caller, __entry->width,
> + __entry->val, __entry->addr)
> +);
> +
> +#endif /* _TRACE_RWMMIO_H */
> +
> +#include <trace/define_trace.h>
> diff --git a/lib/Kconfig b/lib/Kconfig
> index c80fde816a7e..ea520c315c0f 100644
> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -119,6 +119,13 @@ config INDIRECT_IOMEM_FALLBACK
> mmio accesses when the IO memory address is not a registered
> emulated region.
>
> +config TRACE_MMIO_ACCESS
> + bool "Register read/write tracing"
> + depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
> + help
> + Create tracepoints for MMIO read/write operations. These trace events
> + can be used for logging all MMIO read/write operations.
> +
> source "lib/crypto/Kconfig"
>
> config CRC_CCITT
> diff --git a/lib/Makefile b/lib/Makefile
> index 300f569c626b..43813b0061cd 100644
> --- a/lib/Makefile
> +++ b/lib/Makefile
> @@ -152,6 +152,8 @@ lib-y += logic_pio.o
>
> lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
>
> +obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
> +
> obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
>
> obj-$(CONFIG_BTREE) += btree.o
> diff --git a/lib/trace_readwrite.c b/lib/trace_readwrite.c
> new file mode 100644
> index 000000000000..88637038b30c
> --- /dev/null
> +++ b/lib/trace_readwrite.c
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Register read and write tracepoints
> + *
> + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/ftrace.h>
> +#include <linux/module.h>
> +#include <asm-generic/io.h>
> +
> +#define CREATE_TRACE_POINTS
> +#include <trace/events/rwmmio.h>
> +
> +#ifdef CONFIG_TRACE_MMIO_ACCESS
> +void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
> + unsigned long caller_addr)
> +{
> + trace_rwmmio_write(caller_addr, val, width, addr);
> +}
> +EXPORT_SYMBOL_GPL(log_write_mmio);
> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
> +
> +void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
> + unsigned long caller_addr)
> +{
> + trace_rwmmio_post_write(caller_addr, val, width, addr);
> +}
> +EXPORT_SYMBOL_GPL(log_post_write_mmio);
> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
> +
> +void log_read_mmio(u8 width, const volatile void __iomem *addr,
> + unsigned long caller_addr)
> +{
> + trace_rwmmio_read(caller_addr, width, addr);
> +}
> +EXPORT_SYMBOL_GPL(log_read_mmio);
> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
> +
> +void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
> + unsigned long caller_addr)
> +{
> + trace_rwmmio_post_read(caller_addr, val, width, addr);
> +}
> +EXPORT_SYMBOL_GPL(log_post_read_mmio);
> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
> +#endif /* CONFIG_TRACE_MMIO_ACCESS */
On 2/24/2022 7:27 PM, Steven Rostedt wrote:
> On Thu, 24 Feb 2022 11:37:07 +0530
> Sai Prakash Ranjan <[email protected]> wrote:
>
>
>> --- /dev/null
>> +++ b/include/trace/events/rwmmio.h
>> @@ -0,0 +1,97 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +#undef TRACE_SYSTEM
>> +#define TRACE_SYSTEM rwmmio
>> +
>> +#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ)
>> +#define _TRACE_RWMMIO_H
>> +
>> +#include <linux/tracepoint.h>
>> +
>> +DECLARE_EVENT_CLASS(rwmmio_rw_template,
>> +
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
>> +
>> + TP_ARGS(caller, val, width, addr),
>> +
>> + TP_STRUCT__entry(
>> + __field(u64, caller)
>> + __field(u64, val)
>> + __field(u64, addr)
> So caller and addr are both pointers. Why not define them as unsigned long?
> That will save 8 bytes on 32 bit machines.
>
> __field(unsigned long, caller)
> __field(unsigned long, addr)
> __feild(u64, val)
>
> to keep the longs together as on 32 bit, it will be better aligned.
>
> The tracing tools can handle the difference from user space. Even when
> reading trace files from 32 bit architectures on 64 bit machines, and vise
> versa.
Sure, I'll change them to unsigned long. Thanks for the suggestion.
>> + __field(u8, width)
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->caller = caller;
>> + __entry->val = val;
>> + __entry->addr = (unsigned long)(void *)addr;
>> + __entry->width = width;
>> + ),
>> +
>> + TP_printk("%pS width=%d val=%#llx addr=%#llx",
>> + (void *)(unsigned long)__entry->caller, __entry->width,
>> + __entry->val, __entry->addr)
>> +);
>> +
>> +DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
>> + TP_ARGS(caller, val, width, addr)
>> +);
>> +
>> +DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
>> + TP_ARGS(caller, val, width, addr)
>> +);
>> +
>> +TRACE_EVENT(rwmmio_read,
>> +
>> + TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
>> +
>> + TP_ARGS(caller, width, addr),
>> +
>> + TP_STRUCT__entry(
>> + __field(u64, caller)
>> + __field(u64, addr)
> Same here.
>
> -- Steve
Sure.
Thanks,
Sai
>
>> + __field(u8, width)
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->caller = caller;
>> + __entry->addr = (unsigned long)(void *)addr;
>> + __entry->width = width;
>> + ),
>> +
>> + TP_printk("%pS width=%d addr=%#llx",
>> + (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)
>> +);
>> +
>> +TRACE_EVENT(rwmmio_post_read,
>> +
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
>> +
>> + TP_ARGS(caller, val, width, addr),
>> +
>> + TP_STRUCT__entry(
>> + __field(u64, caller)
>> + __field(u64, val)
>> + __field(u64, addr)
>> + __field(u8, width)
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->caller = caller;
>> + __entry->val = val;
>> + __entry->addr = (unsigned long)(void *)addr;
>> + __entry->width = width;
>> + ),
>> +
>> + TP_printk("%pS width=%d val=%#llx addr=%#llx",
>> + (void *)(unsigned long)__entry->caller, __entry->width,
>> + __entry->val, __entry->addr)
>> +);
>> +
>> +#endif /* _TRACE_RWMMIO_H */
>> +
>> +#include <trace/define_trace.h>
>> diff --git a/lib/Kconfig b/lib/Kconfig
>> index c80fde816a7e..ea520c315c0f 100644
>> --- a/lib/Kconfig
>> +++ b/lib/Kconfig
>> @@ -119,6 +119,13 @@ config INDIRECT_IOMEM_FALLBACK
>> mmio accesses when the IO memory address is not a registered
>> emulated region.
>>
>> +config TRACE_MMIO_ACCESS
>> + bool "Register read/write tracing"
>> + depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
>> + help
>> + Create tracepoints for MMIO read/write operations. These trace events
>> + can be used for logging all MMIO read/write operations.
>> +
>> source "lib/crypto/Kconfig"
>>
>> config CRC_CCITT
>> diff --git a/lib/Makefile b/lib/Makefile
>> index 300f569c626b..43813b0061cd 100644
>> --- a/lib/Makefile
>> +++ b/lib/Makefile
>> @@ -152,6 +152,8 @@ lib-y += logic_pio.o
>>
>> lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
>>
>> +obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
>> +
>> obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
>>
>> obj-$(CONFIG_BTREE) += btree.o
>> diff --git a/lib/trace_readwrite.c b/lib/trace_readwrite.c
>> new file mode 100644
>> index 000000000000..88637038b30c
>> --- /dev/null
>> +++ b/lib/trace_readwrite.c
>> @@ -0,0 +1,47 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Register read and write tracepoints
>> + *
>> + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/ftrace.h>
>> +#include <linux/module.h>
>> +#include <asm-generic/io.h>
>> +
>> +#define CREATE_TRACE_POINTS
>> +#include <trace/events/rwmmio.h>
>> +
>> +#ifdef CONFIG_TRACE_MMIO_ACCESS
>> +void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_write(caller_addr, val, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_write_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
>> +
>> +void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_post_write(caller_addr, val, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_post_write_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
>> +
>> +void log_read_mmio(u8 width, const volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_read(caller_addr, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_read_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
>> +
>> +void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_post_read(caller_addr, val, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_post_read_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
>> +#endif /* CONFIG_TRACE_MMIO_ACCESS */
Hi Arnd,
On 2/24/2022 11:37 AM, Sai Prakash Ranjan wrote:
> Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
> are typically used to read/write from/to memory mapped registers
> and can cause hangs or some undefined behaviour in following cases,
>
> * If the access to the register space is unclocked, for example: if
> there is an access to multimedia(MM) block registers without MM
> clocks.
>
> * If the register space is protected and not set to be accessible from
> non-secure world, for example: only EL3 (EL: Exception level) access
> is allowed and any EL2/EL1 access is forbidden.
>
> * If xPU(memory/register protection units) is controlling access to
> certain memory/register space for specific clients.
>
> and more...
>
> Such cases usually results in instant reboot/SErrors/NOC or interconnect
> hangs and tracing these register accesses can be very helpful to debug
> such issues during initial development stages and also in later stages.
>
> So use ftrace trace events to log such MMIO register accesses which
> provides rich feature set such as early enablement of trace events,
> filtering capability, dumping ftrace logs on console and many more.
>
> Sample output:
>
> rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
> rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
> rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
> rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610
>
> This series is a follow-up for the series [1] and a recent series [2] making use
> of both.
>
> [1] https://lore.kernel.org/lkml/[email protected]/
> [2] https://lore.kernel.org/lkml/[email protected]/
>
> Note in previous v4 version, Arnd suggested to benchmark and compare size with callback
> based implementation, please see [3] for more details on that with brief comparison below.
>
>
> **Inline version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
> $ size vmlinux
> text data bss dec hex filename
> 23884219 14284468 532568 38701255 24e88c7 vmlinux
>
> **Callback version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
> $ size vmlinux
> text data bss dec hex filename
> 24108179 14279596 532568 38920343 251e097 vmlinux
>
> $ ./scripts/bloat-o-meter inline-vmlinux callback-vmlinux
> add/remove: 8/3 grow/shrink: 4889/89 up/down: 242244/-11564 (230680)
> Total: Before=25812612, After=26043292, chg +0.89%
>
> [3] https://lore.kernel.org/lkml/[email protected]/
>
> Changes in v10:
> * Use GENMASK(31, 0) for -Woverflow warning in irqchip tegra driver (Marc).
> * Convert ETM4x ARM64 driver to use asm-generic IO memory barriers (Catalin).
> * Collect ack from Catalin for arm64 change.
>
> Changes in v9:
> * Use TRACE_EVENT_CLASS for rwmmio_write and post_write (Steven Rostedt).
>
> Changes in v8:
> * Fix build error reported by kernel test robot.
>
> Changes in v7:
> * Use lib/ instead of kernel/trace/ based on review comment by Steven Rostedt.
>
> Changes in v6:
> * Implemented suggestions by Arnd Bergmann:
> - Use arch independent IO barriers in arm64/asm
> - Add ARCH_HAVE_TRACE_MMIO_ACCESS
> - Add post read and post write logging support
> - Remove tracepoint_active check
> * Fix build error reported by kernel test robot.
>
> Changes in v5:
> * Move arm64 to use asm-generic provided high level MMIO accessors (Arnd).
> * Add inline logging for MMIO relaxed and non-relaxed accessors.
> * Move nVHE KVM comment to makefile (Marc).
> * Fix overflow warning due to switch to inline accessors instead of macro.
> * Modify trace event field to include caller and parent details for more detailed logs.
>
> Changes in v4:
> * Drop dynamic debug based filter support since that will be developed later with
> the help from Steven (Ftrace maintainer).
> * Drop value passed to writel as it is causing hangs when tracing is enabled.
> * Code cleanup for trace event as suggested by Steven for earlier version.
> * Fixed some build errors reported by 0-day bot.
>
> Changes in v3:
> * Create a generic mmio header for instrumented version (Earlier suggested in [1]
> by Will Deacon and recently [2] by Greg to have a generic version first).
> * Add dynamic debug support to filter out traces which can be very useful for targeted
> debugging specific to subsystems or drivers.
> * Few modifications to the rwmmio trace event fields to include the mmio width and print
> addresses in hex.
> * Rewrote commit msg to explain some more about usecases.
>
> Prasad Sodagudi (1):
> lib: Add register read/write tracing support
>
> Sai Prakash Ranjan (5):
> arm64: io: Use asm-generic high level MMIO accessors
> coresight: etm4x: Use asm-generic IO memory barriers
> irqchip/tegra: Fix overflow implicit truncation warnings
> drm/meson: Fix overflow implicit truncation warnings
> asm-generic/io: Add logging support for MMIO accessors
>
> arch/Kconfig | 3 +
> arch/arm64/Kconfig | 1 +
> arch/arm64/include/asm/io.h | 41 ++------
> arch/arm64/kvm/hyp/nvhe/Makefile | 7 +-
> drivers/gpu/drm/meson/meson_viu.c | 22 ++---
> .../coresight/coresight-etm4x-core.c | 8 +-
> drivers/hwtracing/coresight/coresight-etm4x.h | 8 +-
> drivers/irqchip/irq-tegra.c | 10 +-
> include/asm-generic/io.h | 82 +++++++++++++++-
> include/trace/events/rwmmio.h | 97 +++++++++++++++++++
> lib/Kconfig | 7 ++
> lib/Makefile | 2 +
> lib/trace_readwrite.c | 47 +++++++++
> 13 files changed, 273 insertions(+), 62 deletions(-)
> create mode 100644 include/trace/events/rwmmio.h
> create mode 100644 lib/trace_readwrite.c
>
>
> base-commit: 754e0b0e35608ed5206d6a67a791563c631cec07
Gentle ping, could you please take a look at this, would appreciate your reviews.
Thanks,
Sai
Hi Arnd,
On 4/8/2022 4:47 PM, Sai Prakash Ranjan wrote:
> Hi Arnd,
>
> On 2/24/2022 11:37 AM, Sai Prakash Ranjan wrote:
>> Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
>> are typically used to read/write from/to memory mapped registers
>> and can cause hangs or some undefined behaviour in following cases,
>>
>> * If the access to the register space is unclocked, for example: if
>> there is an access to multimedia(MM) block registers without MM
>> clocks.
>>
>> * If the register space is protected and not set to be accessible from
>> non-secure world, for example: only EL3 (EL: Exception level) access
>> is allowed and any EL2/EL1 access is forbidden.
>>
>> * If xPU(memory/register protection units) is controlling access to
>> certain memory/register space for specific clients.
>>
>> and more...
>>
>> Such cases usually results in instant reboot/SErrors/NOC or interconnect
>> hangs and tracing these register accesses can be very helpful to debug
>> such issues during initial development stages and also in later stages.
>>
>> So use ftrace trace events to log such MMIO register accesses which
>> provides rich feature set such as early enablement of trace events,
>> filtering capability, dumping ftrace logs on console and many more.
>>
>> Sample output:
>>
>> rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
>> rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
>> rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
>> rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610
>>
>> This series is a follow-up for the series [1] and a recent series [2] making use
>> of both.
>>
>> [1] https://lore.kernel.org/lkml/[email protected]/
>> [2] https://lore.kernel.org/lkml/[email protected]/
>>
>> Note in previous v4 version, Arnd suggested to benchmark and compare size with callback
>> based implementation, please see [3] for more details on that with brief comparison below.
>>
>>
>> **Inline version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
>> $ size vmlinux
>> text data bss dec hex filename
>> 23884219 14284468 532568 38701255 24e88c7 vmlinux
>>
>> **Callback version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**
>> $ size vmlinux
>> text data bss dec hex filename
>> 24108179 14279596 532568 38920343 251e097 vmlinux
>>
>> $ ./scripts/bloat-o-meter inline-vmlinux callback-vmlinux
>> add/remove: 8/3 grow/shrink: 4889/89 up/down: 242244/-11564 (230680)
>> Total: Before=25812612, After=26043292, chg +0.89%
>>
>> [3] https://lore.kernel.org/lkml/[email protected]/
>>
>> Changes in v10:
>> * Use GENMASK(31, 0) for -Woverflow warning in irqchip tegra driver (Marc).
>> * Convert ETM4x ARM64 driver to use asm-generic IO memory barriers (Catalin).
>> * Collect ack from Catalin for arm64 change.
>>
>> Changes in v9:
>> * Use TRACE_EVENT_CLASS for rwmmio_write and post_write (Steven Rostedt).
>>
>> Changes in v8:
>> * Fix build error reported by kernel test robot.
>>
>> Changes in v7:
>> * Use lib/ instead of kernel/trace/ based on review comment by Steven Rostedt.
>>
>> Changes in v6:
>> * Implemented suggestions by Arnd Bergmann:
>> - Use arch independent IO barriers in arm64/asm
>> - Add ARCH_HAVE_TRACE_MMIO_ACCESS
>> - Add post read and post write logging support
>> - Remove tracepoint_active check
>> * Fix build error reported by kernel test robot.
>>
>> Changes in v5:
>> * Move arm64 to use asm-generic provided high level MMIO accessors (Arnd).
>> * Add inline logging for MMIO relaxed and non-relaxed accessors.
>> * Move nVHE KVM comment to makefile (Marc).
>> * Fix overflow warning due to switch to inline accessors instead of macro.
>> * Modify trace event field to include caller and parent details for more detailed logs.
>>
>> Changes in v4:
>> * Drop dynamic debug based filter support since that will be developed later with
>> the help from Steven (Ftrace maintainer).
>> * Drop value passed to writel as it is causing hangs when tracing is enabled.
>> * Code cleanup for trace event as suggested by Steven for earlier version.
>> * Fixed some build errors reported by 0-day bot.
>>
>> Changes in v3:
>> * Create a generic mmio header for instrumented version (Earlier suggested in [1]
>> by Will Deacon and recently [2] by Greg to have a generic version first).
>> * Add dynamic debug support to filter out traces which can be very useful for targeted
>> debugging specific to subsystems or drivers.
>> * Few modifications to the rwmmio trace event fields to include the mmio width and print
>> addresses in hex.
>> * Rewrote commit msg to explain some more about usecases.
>>
>> Prasad Sodagudi (1):
>> lib: Add register read/write tracing support
>>
>> Sai Prakash Ranjan (5):
>> arm64: io: Use asm-generic high level MMIO accessors
>> coresight: etm4x: Use asm-generic IO memory barriers
>> irqchip/tegra: Fix overflow implicit truncation warnings
>> drm/meson: Fix overflow implicit truncation warnings
>> asm-generic/io: Add logging support for MMIO accessors
>>
>> arch/Kconfig | 3 +
>> arch/arm64/Kconfig | 1 +
>> arch/arm64/include/asm/io.h | 41 ++------
>> arch/arm64/kvm/hyp/nvhe/Makefile | 7 +-
>> drivers/gpu/drm/meson/meson_viu.c | 22 ++---
>> .../coresight/coresight-etm4x-core.c | 8 +-
>> drivers/hwtracing/coresight/coresight-etm4x.h | 8 +-
>> drivers/irqchip/irq-tegra.c | 10 +-
>> include/asm-generic/io.h | 82 +++++++++++++++-
>> include/trace/events/rwmmio.h | 97 +++++++++++++++++++
>> lib/Kconfig | 7 ++
>> lib/Makefile | 2 +
>> lib/trace_readwrite.c | 47 +++++++++
>> 13 files changed, 273 insertions(+), 62 deletions(-)
>> create mode 100644 include/trace/events/rwmmio.h
>> create mode 100644 lib/trace_readwrite.c
>>
>>
>> base-commit: 754e0b0e35608ed5206d6a67a791563c631cec07
> Gentle ping, could you please take a look at this, would appreciate your reviews.
>
Gentle Ping !!
Thanks,
Sai
On Thu, Apr 21, 2022 at 4:00 AM Sai Prakash Ranjan
<[email protected]> wrote:
> On 4/8/2022 4:47 PM, Sai Prakash Ranjan wrote:
> > Gentle ping, could you please take a look at this, would appreciate your reviews.
> >
>
> Gentle Ping !!
>
Sorry for dropping the ball on this. I'll go through the patches again
now. From a new
look, this all seems fine, but I'll need to take a little extra time
to understand why we
are getting the warnings that you are fixing, and how one will use the
tracepoints
in the end.
Arnd
On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
<[email protected]> wrote:
>
> Per discussion in [1], it was decided to move to using architecture
> independent/asm-generic IO memory barriers to have just one set of
> them and deprecate use of arm64 specific IO memory barriers in driver
> code. So replace current usage of __io_rmb()/__iowmb() in drivers to
> __io_ar()/__io_bw().
>
> [1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/
>
> Cc: Catalin Marinas <[email protected]>
> Cc: Mathieu Poirier <[email protected]>
> Cc: Suzuki K Poulose <[email protected]>
> Cc: Mike Leach <[email protected]>
> Cc: [email protected]
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Arnd Bergmann <[email protected]>
On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
<[email protected]> wrote:
>
> Fix -Woverflow warnings for drm/meson driver which is a result
> of moving arm64 custom MMIO accessor macros to asm-generic function
> implementations giving a bonus type-checking now and uncovering these
> overflow warnings.
>
> drivers/gpu/drm/meson/meson_viu.c: In function ‘meson_viu_init’:
> drivers/gpu/drm/meson/meson_registers.h:1826:48: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
> #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
> ^
> drivers/gpu/drm/meson/meson_viu.c:472:18: note: in expansion of macro ‘VIU_OSD_BLEND_REORDER’
> writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
> ^~~~~~~~~~~~~~~~~~~~~
>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Reported-by: kernel test robot <[email protected]>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Arnd Bergmann <[email protected]>
It took me a bit to understand why we got the warning in the first place, but I
should have just read the patch description, it's all there....
On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
<[email protected]> wrote:
>
> From: Prasad Sodagudi <[email protected]>
>
> Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
> are typically used to read/write from/to memory mapped registers
> and can cause hangs or some undefined behaviour in following few
> cases,
>
> * If the access to the register space is unclocked, for example: if
> there is an access to multimedia(MM) block registers without MM
> clocks.
>
> * If the register space is protected and not set to be accessible from
> non-secure world, for example: only EL3 (EL: Exception level) access
> is allowed and any EL2/EL1 access is forbidden.
>
> * If xPU(memory/register protection units) is controlling access to
> certain memory/register space for specific clients.
>
> and more...
>
> Such cases usually results in instant reboot/SErrors/NOC or interconnect
> hangs and tracing these register accesses can be very helpful to debug
> such issues during initial development stages and also in later stages.
>
> So use ftrace trace events to log such MMIO register accesses which
> provides rich feature set such as early enablement of trace events,
> filtering capability, dumping ftrace logs on console and many more.
>
> Sample output:
>
> rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
> rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
> rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
> rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610
>
> Signed-off-by: Prasad Sodagudi <[email protected]>
> Co-developed-by: Sai Prakash Ranjan <[email protected]>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
I think this is ok in general. I saw that Steve had a minor comment, and
I suppose you could have just resent the same patches with a fixup in order
to have me pick it up into the asm-generic tree for 5.19.
There is one more thing that I saw looking through this patch again: the
address you print is the virtual __iomem token, but it might be more
valuable to have the physical address instead, which can be looked up
in the devicetree to know which register is affected.
There is a small extra cost to walk the page table, and I'm not sure
if we actually have an interface for it (vmalloc_to_page is almost
what we want, but it returns an invalid page pointer). Any suggestions
on this?
Arnd
On 4/27/2022 9:20 PM, Arnd Bergmann wrote:
> On Thu, Apr 21, 2022 at 4:00 AM Sai Prakash Ranjan
> <[email protected]> wrote:
>> On 4/8/2022 4:47 PM, Sai Prakash Ranjan wrote:
>>> Gentle ping, could you please take a look at this, would appreciate your reviews.
>>>
>> Gentle Ping !!
>>
> Sorry for dropping the ball on this. I'll go through the patches again
> now. From a new
> look, this all seems fine, but I'll need to take a little extra time
> to understand why we
> are getting the warnings that you are fixing, and how one will use the
> tracepoints
> in the end.
>
> Arnd
Thanks Arnd, I saw in other thread that you figured out the reasons for warnings.
Thanks,
Sai
Hi Arnd,
On 4/27/2022 9:44 PM, Arnd Bergmann wrote:
> On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
> <[email protected]> wrote:
>> From: Prasad Sodagudi <[email protected]>
>>
>> Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors
>> are typically used to read/write from/to memory mapped registers
>> and can cause hangs or some undefined behaviour in following few
>> cases,
>>
>> * If the access to the register space is unclocked, for example: if
>> there is an access to multimedia(MM) block registers without MM
>> clocks.
>>
>> * If the register space is protected and not set to be accessible from
>> non-secure world, for example: only EL3 (EL: Exception level) access
>> is allowed and any EL2/EL1 access is forbidden.
>>
>> * If xPU(memory/register protection units) is controlling access to
>> certain memory/register space for specific clients.
>>
>> and more...
>>
>> Such cases usually results in instant reboot/SErrors/NOC or interconnect
>> hangs and tracing these register accesses can be very helpful to debug
>> such issues during initial development stages and also in later stages.
>>
>> So use ftrace trace events to log such MMIO register accesses which
>> provides rich feature set such as early enablement of trace events,
>> filtering capability, dumping ftrace logs on console and many more.
>>
>> Sample output:
>>
>> rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
>> rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
>> rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
>> rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610
>>
>> Signed-off-by: Prasad Sodagudi <[email protected]>
>> Co-developed-by: Sai Prakash Ranjan <[email protected]>
>> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> I think this is ok in general. I saw that Steve had a minor comment, and
> I suppose you could have just resent the same patches with a fixup in order
> to have me pick it up into the asm-generic tree for 5.19.
I had it ready the same day Steve gave the comment :) but given there was no further
reviews on other patches, I thought of slowing down the posting of new versions.
I will send v11 now.
> There is one more thing that I saw looking through this patch again: the
> address you print is the virtual __iomem token, but it might be more
> valuable to have the physical address instead, which can be looked up
> in the devicetree to know which register is affected.
>
> There is a small extra cost to walk the page table, and I'm not sure
> if we actually have an interface for it (vmalloc_to_page is almost
> what we want, but it returns an invalid page pointer). Any suggestions
> on this?
>
>
Right, it would be useful but currently we rely on the caller information (the function name and
the offset) to identify who writes to the location and then post process to identify the register
written based on it. I am also not aware of the interface for page table walk and the walk on this
hot trace path (note that we are capturing every register read/write) would slow down the system
further.
Even in the internal versions, we get the physical address postmortem from the parser tool [1].
[1] https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/linux-ramdump-parser-v2/parsers/rtb.py#n72
Given that we can add fields to this tracepoint without breaking ABI, we can probably add this addon
at a later point.
Thanks,
Sai
On 4/27/2022 9:29 PM, Arnd Bergmann wrote:
> On Thu, Feb 24, 2022 at 7:07 AM Sai Prakash Ranjan
> <[email protected]> wrote:
>> Fix -Woverflow warnings for drm/meson driver which is a result
>> of moving arm64 custom MMIO accessor macros to asm-generic function
>> implementations giving a bonus type-checking now and uncovering these
>> overflow warnings.
>>
>> drivers/gpu/drm/meson/meson_viu.c: In function ‘meson_viu_init’:
>> drivers/gpu/drm/meson/meson_registers.h:1826:48: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
>> #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))
>> ^
>> drivers/gpu/drm/meson/meson_viu.c:472:18: note: in expansion of macro ‘VIU_OSD_BLEND_REORDER’
>> writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
>> ^~~~~~~~~~~~~~~~~~~~~
>>
>> Cc: Arnd Bergmann <[email protected]>
>> Cc: Neil Armstrong <[email protected]>
>> Reported-by: kernel test robot <[email protected]>
>> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> Reviewed-by: Arnd Bergmann <[email protected]>
>
> It took me a bit to understand why we got the warning in the first place, but I
> should have just read the patch description, it's all there....
Right :)
Thanks,
Sai