On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> This series extends KVM RISC-V to allow Guest/VM discover and use
> conditional operations related ISA extensions (namely XVentanaCondOps
> and Zicond).
>
> To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> branch at: https://github.com/avpatel/kvmtool.git
>
> These patches are based upon the latest riscv_kvm_queue and can also be
> found in the riscv_kvm_condops_v2 branch at:
> https://github.com/avpatel/linux.git
>
> Changes since v1:
> - Rebased the series on riscv_kvm_queue
> - Split PATCH1 and PATCH2 of v1 series into two patches
> - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> of v1 series.
>
> Anup Patel (9):
> dt-bindings: riscv: Add XVentanaCondOps extension entry
> RISC-V: Detect XVentanaCondOps from ISA string
> dt-bindings: riscv: Add Zicond extension entry
> RISC-V: Detect Zicond from ISA string
For these 4:
Reviewed-by: Conor Dooley <[email protected]>
Thanks for splitting it out,
Conor.
On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
> On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> > This series extends KVM RISC-V to allow Guest/VM discover and use
> > conditional operations related ISA extensions (namely XVentanaCondOps
> > and Zicond).
> >
> > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> > branch at: https://github.com/avpatel/kvmtool.git
> >
> > These patches are based upon the latest riscv_kvm_queue and can also be
> > found in the riscv_kvm_condops_v2 branch at:
> > https://github.com/avpatel/linux.git
> >
> > Changes since v1:
> > - Rebased the series on riscv_kvm_queue
> > - Split PATCH1 and PATCH2 of v1 series into two patches
> > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> > of v1 series.
> >
> > Anup Patel (9):
> > dt-bindings: riscv: Add XVentanaCondOps extension entry
> > RISC-V: Detect XVentanaCondOps from ISA string
> > dt-bindings: riscv: Add Zicond extension entry
> > RISC-V: Detect Zicond from ISA string
>
> For these 4:
> Reviewed-by: Conor Dooley <[email protected]>
Actually, now that I think of it, I'm going to temporarily un-review this.
From patch-acceptance.rst:
| Additionally, the RISC-V specification allows implementers to create
| their own custom extensions. These custom extensions aren't required
| to go through any review or ratification process by the RISC-V
| Foundation. To avoid the maintenance complexity and potential
| performance impact of adding kernel code for implementor-specific
| RISC-V extensions, we'll only consider patches for extensions that either:
|
| - Have been officially frozen or ratified by the RISC-V Foundation, or
| - Have been implemented in hardware that is widely available, per standard
| Linux practice.
The xventanacondops bits don't qualify under the first entry, and I
don't think they qualify under the second yet. Am I wrong?
On Mon, Sep 25, 2023 at 9:07 PM Conor Dooley <[email protected]> wrote:
>
> On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
> > On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> > > This series extends KVM RISC-V to allow Guest/VM discover and use
> > > conditional operations related ISA extensions (namely XVentanaCondOps
> > > and Zicond).
> > >
> > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> > > branch at: https://github.com/avpatel/kvmtool.git
> > >
> > > These patches are based upon the latest riscv_kvm_queue and can also be
> > > found in the riscv_kvm_condops_v2 branch at:
> > > https://github.com/avpatel/linux.git
> > >
> > > Changes since v1:
> > > - Rebased the series on riscv_kvm_queue
> > > - Split PATCH1 and PATCH2 of v1 series into two patches
> > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> > > of v1 series.
> > >
> > > Anup Patel (9):
> > > dt-bindings: riscv: Add XVentanaCondOps extension entry
> > > RISC-V: Detect XVentanaCondOps from ISA string
> > > dt-bindings: riscv: Add Zicond extension entry
> > > RISC-V: Detect Zicond from ISA string
> >
> > For these 4:
> > Reviewed-by: Conor Dooley <[email protected]>
>
> Actually, now that I think of it, I'm going to temporarily un-review this.
> From patch-acceptance.rst:
> | Additionally, the RISC-V specification allows implementers to create
> | their own custom extensions. These custom extensions aren't required
> | to go through any review or ratification process by the RISC-V
> | Foundation. To avoid the maintenance complexity and potential
> | performance impact of adding kernel code for implementor-specific
> | RISC-V extensions, we'll only consider patches for extensions that either:
> |
> | - Have been officially frozen or ratified by the RISC-V Foundation, or
> | - Have been implemented in hardware that is widely available, per standard
> | Linux practice.
>
> The xventanacondops bits don't qualify under the first entry, and I
> don't think they qualify under the second yet. Am I wrong?
The Ventana Veyron V1 was announced in Dec 2022 at RISC-V summit
followed by press releases:
https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/
https://www.embedded.com/ventana-reveals-risc-v-cpu-compute-chiplet-for-data-center/
https://www.prnewswire.com/news-releases/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family-301700985.html
@Palmer if the above looks good to you then please ack PATCH1-to-4
Thanks,
Anup