From: Lad Prabhakar <[email protected]>
Hi All,
This patch series does the following:
* Adds IRQC support to the RZ/G2UL SoC.
* Drops mapping NMI interrupt as part of IRQ domain
* Parses interrupts based in interrupt-names
* Includes a fix for pinctrl driver when using GPIO pins as interrupts
* Adds PHY interrupt support for ETH{0/1}
v1->v2
* Updated binding doc
* Dropped mapping NMI interrupt as part of IRQ domain
* Fixed review comments pointed by Geert
* Added support to parse interrupts by name
* Added compile time checks for gpio config arrays
RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/[email protected]/
Cheers,
Prabhakar
Lad Prabhakar (9):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document
RZ/G2UL SoC
dt-bindings: interrupt-controller: irqc-rzg2l: Drop RZG2L_NMI macro
irqchip: irq-renesas-rzg2l: Skip mapping NMI interrupt as part of
hierarchy domain
irqchip: irq-renesas-rzg2l: Add support for RZ/G2UL SoC
pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts
pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks
arm64: dts: renesas: r9a07g043u: Add IRQC node
arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO
interrupts
arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for
ETH{0/1}
.../renesas,rzg2l-irqc.yaml | 240 +++++++++++++-----
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 +
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++++
.../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +-
drivers/irqchip/irq-renesas-rzg2l.c | 102 ++++++--
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +-
.../interrupt-controller/irqc-rzg2l.h | 3 -
7 files changed, 366 insertions(+), 89 deletions(-)
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each
supported SoC.
While at it, for readability set n_port_pins based on the GPIO pin configs
and not on GPIO names for r9a07g044_data as done for r9a07g043_data.
Suggested-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* New patch
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 03e9462f39b1..8036485f2e92 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1465,6 +1465,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
struct rzg2l_pinctrl *pctrl;
int ret;
+ BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
+ BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@@ -1528,7 +1534,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pin_configs = rzg2l_gpio_configs,
.n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
- .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
+ .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
};
--
2.25.1
From: Lad Prabhakar <[email protected]>
NMI interrupt is not an external interrupt as compared to the IRQ0-7 and
TINT0-31, this means we need to install the irq handler for NMI in the
IRQC driver and not include it as part of IRQ domain.
This patch skips mapping NMI interrupt as part of the IRQ domain
hierarchy.
Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver")
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* New patch
---
drivers/irqchip/irq-renesas-rzg2l.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 25fd8ee66565..7918fe201218 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -23,7 +23,8 @@
#define IRQC_IRQ_COUNT 8
#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
#define IRQC_TINT_COUNT 32
-#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
+ /* IRQ0-7 + TINT0-31 */
+#define IRQC_NUM_HIERARCHY_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT - 1)
#define ISCR 0x10
#define IITSR 0x14
@@ -58,7 +59,8 @@
struct rzg2l_irqc_priv {
void __iomem *base;
- struct irq_fwspec fwspec[IRQC_NUM_IRQ];
+ /* IRQ0-7 + TINT0-31 will be part of hierarchy domain */
+ struct irq_fwspec fwspec[IRQC_NUM_HIERARCHY_IRQ];
raw_spinlock_t lock;
};
@@ -99,7 +101,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
raw_spin_lock(&priv->lock);
if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
rzg2l_irq_eoi(d);
- else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
+ else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ)
rzg2l_tint_eoi(d);
raw_spin_unlock(&priv->lock);
irq_chip_eoi_parent(d);
@@ -109,7 +111,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d)
{
unsigned int hw_irq = irqd_to_hwirq(d);
- if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
+ if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) {
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
u32 offset = hw_irq - IRQC_TINT_START;
u32 tssr_offset = TSSR_OFFSET(offset);
@@ -129,7 +131,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
{
unsigned int hw_irq = irqd_to_hwirq(d);
- if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
+ if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) {
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned long tint = (uintptr_t)d->chip_data;
u32 offset = hw_irq - IRQC_TINT_START;
@@ -228,7 +230,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
ret = rzg2l_irq_set_type(d, type);
- else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
+ else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ)
ret = rzg2l_tint_set_edge(d, type);
if (ret)
return ret;
@@ -280,7 +282,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
return -EINVAL;
}
- if (hwirq > (IRQC_NUM_IRQ - 1))
+ if (!hwirq || hwirq > IRQC_NUM_HIERARCHY_IRQ)
return -EINVAL;
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
@@ -288,7 +290,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
if (ret)
return ret;
- return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq - 1]);
}
static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
@@ -304,12 +306,12 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
unsigned int i;
int ret;
- for (i = 0; i < IRQC_NUM_IRQ; i++) {
+ for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) {
ret = of_irq_parse_one(np, i, &map);
if (ret)
return ret;
of_phandle_args_to_fwspec(np, map.args, map.args_count,
- &priv->fwspec[i]);
+ &priv->fwspec[i - 1]);
}
return 0;
@@ -366,7 +368,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
raw_spin_lock_init(&priv->lock);
- irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
+ irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_HIERARCHY_IRQ,
node, &rzg2l_irqc_domain_ops,
priv);
if (!irq_domain) {
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* Moved irqc node completely to rzg2ul SoC DTSI
* Added interrupt-names
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 68 +++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 6af5f3bca2d1..c6e25ad98011 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -52,6 +52,74 @@ timer {
&soc {
interrupt-parent = <&gic>;
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g043u-irqc",
+ "renesas,rzg2ul-irqc";
+ reg = <0 0x110a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_IA55_RESETN>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.25.1
From: Lad Prabhakar <[email protected]>
NMI interrupt is not an external interrupt as compared to IRQ0-7 and
TINT0-31 on RZ/G2L SoC, so there is no need for RZG2L_NMI macro.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* New patch
---
include/dt-bindings/interrupt-controller/irqc-rzg2l.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
index 34ce778885a1..dd2da795208d 100644
--- a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
+++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
@@ -9,9 +9,6 @@
#ifndef __DT_BINDINGS_IRQC_RZG2L_H
#define __DT_BINDINGS_IRQC_RZG2L_H
-/* NMI maps to SPI0 */
-#define RZG2L_NMI 0
-
/* IRQ0-7 map to SPI1-8 */
#define RZG2L_IRQ0 1
#define RZG2L_IRQ1 2
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add required properties in pinctrl node to handle GPIO interrupts.
Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
continues without waiting for IRQC to probe.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* No change
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 3f7d451b1199..c8a83e42c4f3 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -531,6 +531,8 @@ pinctrl: pinctrl@11030000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 152>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_GPIO_RSTN>,
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index c6e25ad98011..a31cc54b8ed6 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -49,6 +49,10 @@ timer {
};
};
+&pinctrl {
+ interrupt-parent = <&irqc>;
+};
+
&soc {
interrupt-parent = <&gic>;
--
2.25.1
From: Lad Prabhakar <[email protected]>
On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also
the pin configs are completely different. This patch makes sure we use the
appropriate pin configs for each SoC (which is passed as part of the OF
data) while configuring the GPIO pin as interrupts instead of using
rzg2l_gpio_configs[] for all the SoCs.
Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support")
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
---
v1 -> v2
* Fixed comments pointed by Geert for variable naming
* Added RB tag
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 4e79b2961232..03e9462f39b1 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -127,6 +127,7 @@ struct rzg2l_dedicated_configs {
struct rzg2l_pinctrl_data {
const char * const *port_pins;
const u32 *port_pin_configs;
+ unsigned int n_ports;
struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
@@ -1121,7 +1122,7 @@ static struct {
}
};
-static int rzg2l_gpio_get_gpioint(unsigned int virq)
+static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
{
unsigned int gpioint;
unsigned int i;
@@ -1130,13 +1131,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq)
port = virq / 8;
bit = virq % 8;
- if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
- bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
+ if (port >= data->n_ports ||
+ bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
return -EINVAL;
gpioint = bit;
for (i = 0; i < port; i++)
- gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]);
+ gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
return gpioint;
}
@@ -1236,7 +1237,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned long flags;
int gpioint, irq;
- gpioint = rzg2l_gpio_get_gpioint(child);
+ gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
if (gpioint < 0)
return gpioint;
@@ -1310,8 +1311,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
port = offset / 8;
bit = offset % 8;
- if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
- bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
+ if (port >= pctrl->data->n_ports ||
+ bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
clear_bit(offset, valid_mask);
}
}
@@ -1516,6 +1517,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
@@ -1524,6 +1526,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = rzg2l_gpio_configs,
+ .n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
--
2.25.1
From: Lad Prabhakar <[email protected]>
The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
ETH1 respectively.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* No change
---
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 931efc07d6fb..49ecd33aeeb8 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
@@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -104,6 +107,8 @@ phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -151,7 +156,8 @@ eth0_pins: eth0 {
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
- <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
};
eth1_pins: eth1 {
@@ -169,7 +175,8 @@ eth1_pins: eth1 {
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
- <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
};
sdhi0_emmc_pins: sd0emmc {
--
2.25.1
From: Lad Prabhakar <[email protected]>
Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
is almost identical to one found on the RZ/G2L SoC the only difference
being it can support BUS_ERR_INT for which it has additional registers.
Hence new generic compatible string "renesas,rzg2ul-irqc" is added for
RZ/G2UL SoC.
Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
interrupt-names property is added so that we can parse them based on
names.
While at it updated the example node to four spaces and added
interrupt-names property.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1- > v2
* Dropped RB tags
* Added generic compatible string for rzg2ul
* Added interrupt-names
* Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
* Updated example node with interrupt-names
* Used 4 spaces for example node
---
.../renesas,rzg2l-irqc.yaml | 240 +++++++++++++-----
1 file changed, 180 insertions(+), 60 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 33b90e975e33..6a0cf57698ab 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -19,16 +19,19 @@ description: |
- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
stand-up edge detection interrupts)
-allOf:
- - $ref: /schemas/interrupt-controller.yaml#
-
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g044-irqc # RZ/G2{L,LC}
- - renesas,r9a07g054-irqc # RZ/V2L
- - const: renesas,rzg2l-irqc
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-irqc # RZ/G2{L,LC}
+ - renesas,r9a07g054-irqc # RZ/V2L
+ - const: renesas,rzg2l-irqc
+
+ - items:
+ - enum:
+ - renesas,r9a07g043u-irqc # RZ/G2UL
+ - const: renesas,rzg2ul-irqc
'#interrupt-cells':
description: The first cell should contain external interrupt number (IRQ0-7) and the
@@ -44,7 +47,96 @@ properties:
maxItems: 1
interrupts:
- maxItems: 41
+ minItems: 41
+ items:
+ - description: NMI interrupt
+ - description: IRQ0 interrupt
+ - description: IRQ1 interrupt
+ - description: IRQ2 interrupt
+ - description: IRQ3 interrupt
+ - description: IRQ4 interrupt
+ - description: IRQ5 interrupt
+ - description: IRQ6 interrupt
+ - description: IRQ7 interrupt
+ - description: GPIO interrupt, TINT0
+ - description: GPIO interrupt, TINT1
+ - description: GPIO interrupt, TINT2
+ - description: GPIO interrupt, TINT3
+ - description: GPIO interrupt, TINT4
+ - description: GPIO interrupt, TINT5
+ - description: GPIO interrupt, TINT6
+ - description: GPIO interrupt, TINT7
+ - description: GPIO interrupt, TINT8
+ - description: GPIO interrupt, TINT9
+ - description: GPIO interrupt, TINT10
+ - description: GPIO interrupt, TINT11
+ - description: GPIO interrupt, TINT12
+ - description: GPIO interrupt, TINT13
+ - description: GPIO interrupt, TINT14
+ - description: GPIO interrupt, TINT15
+ - description: GPIO interrupt, TINT16
+ - description: GPIO interrupt, TINT17
+ - description: GPIO interrupt, TINT18
+ - description: GPIO interrupt, TINT19
+ - description: GPIO interrupt, TINT20
+ - description: GPIO interrupt, TINT21
+ - description: GPIO interrupt, TINT22
+ - description: GPIO interrupt, TINT23
+ - description: GPIO interrupt, TINT24
+ - description: GPIO interrupt, TINT25
+ - description: GPIO interrupt, TINT26
+ - description: GPIO interrupt, TINT27
+ - description: GPIO interrupt, TINT28
+ - description: GPIO interrupt, TINT29
+ - description: GPIO interrupt, TINT30
+ - description: GPIO interrupt, TINT31
+ - description: Bus error interrupt
+
+ interrupt-names:
+ minItems: 41
+ items:
+ - const: nmi
+ - const: irq0
+ - const: irq1
+ - const: irq2
+ - const: irq3
+ - const: irq4
+ - const: irq5
+ - const: irq6
+ - const: irq7
+ - const: tint0
+ - const: tint1
+ - const: tint2
+ - const: tint3
+ - const: tint4
+ - const: tint5
+ - const: tint6
+ - const: tint7
+ - const: tint8
+ - const: tint9
+ - const: tint10
+ - const: tint11
+ - const: tint12
+ - const: tint13
+ - const: tint14
+ - const: tint15
+ - const: tint16
+ - const: tint17
+ - const: tint18
+ - const: tint19
+ - const: tint20
+ - const: tint21
+ - const: tint22
+ - const: tint23
+ - const: tint24
+ - const: tint25
+ - const: tint26
+ - const: tint27
+ - const: tint28
+ - const: tint29
+ - const: tint30
+ - const: tint31
+ - const: bus-err
clocks:
maxItems: 2
@@ -72,6 +164,23 @@ required:
- power-domains
- resets
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzg2ul-irqc
+ then:
+ properties:
+ interrupts:
+ minItems: 42
+ interrupt-names:
+ minItems: 42
+ required:
+ - interrupt-names
+
unevaluatedProperties: false
examples:
@@ -80,55 +189,66 @@ examples:
#include <dt-bindings/clock/r9a07g044-cpg.h>
irqc: interrupt-controller@110a0000 {
- compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
- reg = <0x110a0000 0x10000>;
- #interrupt-cells = <2>;
- #address-cells = <0>;
- interrupt-controller;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
- <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
- clock-names = "clk", "pclk";
- power-domains = <&cpg>;
- resets = <&cpg R9A07G044_IA55_RESETN>;
+ compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
+ reg = <0x110a0000 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31";
+ clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_IA55_RESETN>;
};
--
2.25.1
From: Lad Prabhakar <[email protected]>
The IRQC block on RZ/G2UL SoC is almost identical to one found on the
RZ/G2L SoC the only difference being it can support BUS_ERR_INT for
which it has additional registers.
This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string
and now that we have interrupt-names property the driver code parses the
interrupts based on names and for backward compatibility we fallback to
parse interrupts based on index.
For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC
too and in future when the interrupt handler will be registered for
BUS_ERR_INT we will have to implement a new callback.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* New patch
---
drivers/irqchip/irq-renesas-rzg2l.c | 80 ++++++++++++++++++++++++++---
1 file changed, 74 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 7918fe201218..5bdf0106ef51 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -299,19 +299,86 @@ static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
.translate = irq_domain_translate_twocell,
};
-static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
- struct device_node *np)
+static int rzg2l_irqc_parse_interrupt_to_fwspec(struct rzg2l_irqc_priv *priv,
+ struct device_node *np,
+ unsigned int index,
+ unsigned int fwspec_index)
{
struct of_phandle_args map;
+ int ret;
+
+ ret = of_irq_parse_one(np, index, &map);
+ if (ret)
+ return ret;
+
+ of_phandle_args_to_fwspec(np, map.args, map.args_count,
+ &priv->fwspec[fwspec_index]);
+
+ return 0;
+}
+
+static int rzg2l_irqc_parse_interrupt_by_name_to_fwspec(struct rzg2l_irqc_priv *priv,
+ struct device_node *np,
+ char *irq_name,
+ unsigned int fwspec_index)
+{
+ int index;
+
+ index = of_property_match_string(np, "interrupt-names", irq_name);
+ if (index < 0)
+ return index;
+
+ return rzg2l_irqc_parse_interrupt_to_fwspec(priv, np, index, fwspec_index);
+}
+
+/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */
+static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv,
+ struct device_node *np)
+{
+ struct property *pp;
unsigned int i;
int ret;
+ /*
+ * first check if interrupt-names property exists if so parse them by name
+ * or else parse them by index for backward compatibility.
+ */
+ pp = of_find_property(np, "interrupt-names", NULL);
+ if (pp) {
+ char *irq_name;
+
+ /* parse IRQ0-7 */
+ for (i = 0; i < IRQC_IRQ_COUNT; i++) {
+ irq_name = kasprintf(GFP_KERNEL, "irq%d", i);
+ if (!irq_name)
+ return -ENOMEM;
+
+ ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i);
+ kfree(irq_name);
+ if (ret)
+ return ret;
+ }
+
+ /* parse TINT0-31 */
+ for (i = 0; i < IRQC_TINT_COUNT; i++) {
+ irq_name = kasprintf(GFP_KERNEL, "tint%d", i);
+ if (!irq_name)
+ return -ENOMEM;
+
+ ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name,
+ i + IRQC_IRQ_COUNT);
+ kfree(irq_name);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+ }
+
for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) {
- ret = of_irq_parse_one(np, i, &map);
+ ret = rzg2l_irqc_parse_interrupt_to_fwspec(priv, np, i, i - 1);
if (ret)
return ret;
- of_phandle_args_to_fwspec(np, map.args, map.args_count,
- &priv->fwspec[i - 1]);
}
return 0;
@@ -343,7 +410,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- ret = rzg2l_irqc_parse_interrupts(priv, node);
+ ret = rzg2l_irqc_parse_hierarchy_interrupts(priv, node);
if (ret) {
dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
return ret;
@@ -389,6 +456,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
+IRQCHIP_MATCH("renesas,rzg2ul-irqc", rzg2l_irqc_init)
IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
MODULE_AUTHOR("Lad Prabhakar <[email protected]>");
MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
--
2.25.1
On Wed, 21 Dec 2022 00:02:37 +0000,
Prabhakar <[email protected]> wrote:
>
> From: Lad Prabhakar <[email protected]>
>
> The IRQC block on RZ/G2UL SoC is almost identical to one found on the
> RZ/G2L SoC the only difference being it can support BUS_ERR_INT for
> which it has additional registers.
>
> This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string
> and now that we have interrupt-names property the driver code parses the
> interrupts based on names and for backward compatibility we fallback to
> parse interrupts based on index.
>
> For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC
> too and in future when the interrupt handler will be registered for
> BUS_ERR_INT we will have to implement a new callback.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
Since you're posting from a different address, please add a second SoB
with your gmail address.
> ---
> v1 -> v2
> * New patch
> ---
> drivers/irqchip/irq-renesas-rzg2l.c | 80 ++++++++++++++++++++++++++---
> 1 file changed, 74 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> index 7918fe201218..5bdf0106ef51 100644
> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -299,19 +299,86 @@ static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
> .translate = irq_domain_translate_twocell,
> };
>
> -static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
> - struct device_node *np)
> +static int rzg2l_irqc_parse_interrupt_to_fwspec(struct rzg2l_irqc_priv *priv,
> + struct device_node *np,
> + unsigned int index,
> + unsigned int fwspec_index)
> {
> struct of_phandle_args map;
> + int ret;
> +
> + ret = of_irq_parse_one(np, index, &map);
> + if (ret)
> + return ret;
> +
> + of_phandle_args_to_fwspec(np, map.args, map.args_count,
> + &priv->fwspec[fwspec_index]);
> +
> + return 0;
> +}
> +
> +static int rzg2l_irqc_parse_interrupt_by_name_to_fwspec(struct rzg2l_irqc_priv *priv,
> + struct device_node *np,
> + char *irq_name,
> + unsigned int fwspec_index)
> +{
> + int index;
> +
> + index = of_property_match_string(np, "interrupt-names", irq_name);
> + if (index < 0)
> + return index;
> +
> + return rzg2l_irqc_parse_interrupt_to_fwspec(priv, np, index, fwspec_index);
> +}
> +
> +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */
> +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv,
> + struct device_node *np)
> +{
> + struct property *pp;
> unsigned int i;
> int ret;
>
> + /*
> + * first check if interrupt-names property exists if so parse them by name
> + * or else parse them by index for backward compatibility.
> + */
> + pp = of_find_property(np, "interrupt-names", NULL);
> + if (pp) {
> + char *irq_name;
> +
> + /* parse IRQ0-7 */
> + for (i = 0; i < IRQC_IRQ_COUNT; i++) {
> + irq_name = kasprintf(GFP_KERNEL, "irq%d", i);
> + if (!irq_name)
> + return -ENOMEM;
> +
> + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i);
Am I the only one that find it rather odd to construct a name from an
index, only to get another index back?
In any case, the string stuff could be moved into
rzg2l_irqc_parse_interrupt_by_name_to_fwspec(). Which could really do
with a name shortening)... rzg2l_irqc_name_to_fwspec? Same thing for
the other function (rzg2l_irqc_index_to_fwspec).
M.
--
Without deviation from the norm, progress is not possible.
On Wed, 21 Dec 2022 00:02:36 +0000,
Prabhakar <[email protected]> wrote:
>
> From: Lad Prabhakar <[email protected]>
>
> NMI interrupt is not an external interrupt as compared to the IRQ0-7 and
> TINT0-31, this means we need to install the irq handler for NMI in the
> IRQC driver and not include it as part of IRQ domain.
>
> This patch skips mapping NMI interrupt as part of the IRQ domain
> hierarchy.
Does it mean nobody can connect anything to it? Where is the handler
you're mentioning for this NMI?
>
> Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver")
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v1 -> v2
> * New patch
> ---
> drivers/irqchip/irq-renesas-rzg2l.c | 24 +++++++++++++-----------
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> index 25fd8ee66565..7918fe201218 100644
> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -23,7 +23,8 @@
> #define IRQC_IRQ_COUNT 8
> #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
> #define IRQC_TINT_COUNT 32
> -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
> + /* IRQ0-7 + TINT0-31 */
> +#define IRQC_NUM_HIERARCHY_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT - 1)
>
> #define ISCR 0x10
> #define IITSR 0x14
> @@ -58,7 +59,8 @@
>
> struct rzg2l_irqc_priv {
> void __iomem *base;
> - struct irq_fwspec fwspec[IRQC_NUM_IRQ];
> + /* IRQ0-7 + TINT0-31 will be part of hierarchy domain */
> + struct irq_fwspec fwspec[IRQC_NUM_HIERARCHY_IRQ];
> raw_spinlock_t lock;
> };
>
> @@ -99,7 +101,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> raw_spin_lock(&priv->lock);
> if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
> rzg2l_irq_eoi(d);
> - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
> + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ)
> rzg2l_tint_eoi(d);
> raw_spin_unlock(&priv->lock);
> irq_chip_eoi_parent(d);
> @@ -109,7 +111,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d)
> {
> unsigned int hw_irq = irqd_to_hwirq(d);
>
> - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) {
> struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> u32 offset = hw_irq - IRQC_TINT_START;
> u32 tssr_offset = TSSR_OFFSET(offset);
> @@ -129,7 +131,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
> {
> unsigned int hw_irq = irqd_to_hwirq(d);
>
> - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) {
> struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> unsigned long tint = (uintptr_t)d->chip_data;
> u32 offset = hw_irq - IRQC_TINT_START;
> @@ -228,7 +230,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
>
> if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
> ret = rzg2l_irq_set_type(d, type);
> - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
> + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ)
How about you define a "tint_hwirq()" helper that checks got the
boundaries? Same thing for the other IRQ type.
> ret = rzg2l_tint_set_edge(d, type);
> if (ret)
> return ret;
> @@ -280,7 +282,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
> return -EINVAL;
> }
>
> - if (hwirq > (IRQC_NUM_IRQ - 1))
> + if (!hwirq || hwirq > IRQC_NUM_HIERARCHY_IRQ)
> return -EINVAL;
>
> ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
> @@ -288,7 +290,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
> if (ret)
> return ret;
>
> - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
> + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq - 1]);
> }
>
> static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
> @@ -304,12 +306,12 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
> unsigned int i;
> int ret;
>
> - for (i = 0; i < IRQC_NUM_IRQ; i++) {
> + for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) {
> ret = of_irq_parse_one(np, i, &map);
> if (ret)
> return ret;
> of_phandle_args_to_fwspec(np, map.args, map.args_count,
> - &priv->fwspec[i]);
> + &priv->fwspec[i - 1]);
Starting the loop at 1 really is non-idiomatic, and I'd rather see
something like this:
for (i = 0; i < IRQC_NUM_HIERARCHY_IRQ; i++) {
ret = of_irq_parse_one(np, i + 1, &map);
if (ret)
return ret;
of_phandle_args_to_fwspec(np, map.args, map.args_count,
&priv->fwspec[i]);
}
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier <[email protected]> wrote:
> On Wed, 21 Dec 2022 00:02:37 +0000,
> Prabhakar <[email protected]> wrote:
> >
> > From: Lad Prabhakar <[email protected]>
> >
> > The IRQC block on RZ/G2UL SoC is almost identical to one found on the
> > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for
> > which it has additional registers.
> >
> > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string
> > and now that we have interrupt-names property the driver code parses the
> > interrupts based on names and for backward compatibility we fallback to
> > parse interrupts based on index.
> >
> > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC
> > too and in future when the interrupt handler will be registered for
> > BUS_ERR_INT we will have to implement a new callback.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */
> > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv,
> > + struct device_node *np)
> > +{
> > + struct property *pp;
> > unsigned int i;
> > int ret;
> >
> > + /*
> > + * first check if interrupt-names property exists if so parse them by name
> > + * or else parse them by index for backward compatibility.
> > + */
> > + pp = of_find_property(np, "interrupt-names", NULL);
> > + if (pp) {
> > + char *irq_name;
> > +
> > + /* parse IRQ0-7 */
> > + for (i = 0; i < IRQC_IRQ_COUNT; i++) {
> > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i);
%u
> > + if (!irq_name)
> > + return -ENOMEM;
> > +
> > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i);
>
> Am I the only one that find it rather odd to construct a name from an
> index, only to get another index back?
The issue is that there are two number ranges ("irq%u" and "tint%u"),
stored in a single interrupts property.
An alternative solution would be to get rid of the "interrupt-names",
and use two separate prefixed interrupts properties instead, like is
common for e.g. gpios: "irq-interrupts" and "tint-interrupts".
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Wed, Dec 21, 2022 at 1:03 AM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> is almost identical to one found on the RZ/G2L SoC the only difference
> being it can support BUS_ERR_INT for which it has additional registers.
> Hence new generic compatible string "renesas,rzg2ul-irqc" is added for
> RZ/G2UL SoC.
>
> Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> interrupt-names property is added so that we can parse them based on
> names.
>
> While at it updated the example node to four spaces and added
> interrupt-names property.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v1- > v2
> * Dropped RB tags
> * Added generic compatible string for rzg2ul
> * Added interrupt-names
> * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> * Updated example node with interrupt-names
> * Used 4 spaces for example node
Thanks for the update!
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -19,16 +19,19 @@ description: |
> - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> stand-up edge detection interrupts)
>
> -allOf:
> - - $ref: /schemas/interrupt-controller.yaml#
> -
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> - - renesas,r9a07g054-irqc # RZ/V2L
> - - const: renesas,rzg2l-irqc
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> + - renesas,r9a07g054-irqc # RZ/V2L
> + - const: renesas,rzg2l-irqc
> +
> + - items:
> + - enum:
> + - renesas,r9a07g043u-irqc # RZ/G2UL
> + - const: renesas,rzg2ul-irqc
I'm not sure it's worth splitting into RZ/G2L and RZ/G2UL alike
variants, and adding the "renesas,rzg2ul-irqc" family-specific
compatible value. You can easily handle the difference by the presence
(or absence) of the "bus-err" interrupt source.
I understand there "renesas,r9a07g043f-irqc" will be added later to
support RZ/Five?
>
> '#interrupt-cells':
> description: The first cell should contain external interrupt number (IRQ0-7) and the
> @@ -44,7 +47,96 @@ properties:
> maxItems: 1
>
> interrupts:
> - maxItems: 41
> + minItems: 41
> + items:
> + - description: NMI interrupt
> + - description: IRQ0 interrupt
> + - description: IRQ1 interrupt
> + - description: IRQ2 interrupt
> + - description: IRQ3 interrupt
> + - description: IRQ4 interrupt
> + - description: IRQ5 interrupt
> + - description: IRQ6 interrupt
> + - description: IRQ7 interrupt
> + - description: GPIO interrupt, TINT0
> + - description: GPIO interrupt, TINT1
> + - description: GPIO interrupt, TINT2
> + - description: GPIO interrupt, TINT3
> + - description: GPIO interrupt, TINT4
> + - description: GPIO interrupt, TINT5
> + - description: GPIO interrupt, TINT6
> + - description: GPIO interrupt, TINT7
> + - description: GPIO interrupt, TINT8
> + - description: GPIO interrupt, TINT9
> + - description: GPIO interrupt, TINT10
> + - description: GPIO interrupt, TINT11
> + - description: GPIO interrupt, TINT12
> + - description: GPIO interrupt, TINT13
> + - description: GPIO interrupt, TINT14
> + - description: GPIO interrupt, TINT15
> + - description: GPIO interrupt, TINT16
> + - description: GPIO interrupt, TINT17
> + - description: GPIO interrupt, TINT18
> + - description: GPIO interrupt, TINT19
> + - description: GPIO interrupt, TINT20
> + - description: GPIO interrupt, TINT21
> + - description: GPIO interrupt, TINT22
> + - description: GPIO interrupt, TINT23
> + - description: GPIO interrupt, TINT24
> + - description: GPIO interrupt, TINT25
> + - description: GPIO interrupt, TINT26
> + - description: GPIO interrupt, TINT27
> + - description: GPIO interrupt, TINT28
> + - description: GPIO interrupt, TINT29
> + - description: GPIO interrupt, TINT30
> + - description: GPIO interrupt, TINT31
> + - description: Bus error interrupt
> +
> + interrupt-names:
> + minItems: 41
> + items:
> + - const: nmi
> + - const: irq0
> + - const: irq1
> + - const: irq2
> + - const: irq3
> + - const: irq4
> + - const: irq5
> + - const: irq6
> + - const: irq7
> + - const: tint0
> + - const: tint1
> + - const: tint2
> + - const: tint3
> + - const: tint4
> + - const: tint5
> + - const: tint6
> + - const: tint7
> + - const: tint8
> + - const: tint9
> + - const: tint10
> + - const: tint11
> + - const: tint12
> + - const: tint13
> + - const: tint14
> + - const: tint15
> + - const: tint16
> + - const: tint17
> + - const: tint18
> + - const: tint19
> + - const: tint20
> + - const: tint21
> + - const: tint22
> + - const: tint23
> + - const: tint24
> + - const: tint25
> + - const: tint26
> + - const: tint27
> + - const: tint28
> + - const: tint29
> + - const: tint30
> + - const: tint31
> + - const: bus-err
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Wed, Dec 21, 2022 at 12:37 PM Geert Uytterhoeven
<[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 1:03 AM Prabhakar <[email protected]> wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> > is almost identical to one found on the RZ/G2L SoC the only difference
> > being it can support BUS_ERR_INT for which it has additional registers.
> > Hence new generic compatible string "renesas,rzg2ul-irqc" is added for
> > RZ/G2UL SoC.
> >
> > Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> > interrupt-names property is added so that we can parse them based on
> > names.
> >
> > While at it updated the example node to four spaces and added
> > interrupt-names property.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > v1- > v2
> > * Dropped RB tags
> > * Added generic compatible string for rzg2ul
> > * Added interrupt-names
> > * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> > * Updated example node with interrupt-names
> > * Used 4 spaces for example node
>
> Thanks for the update!
>
> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > @@ -19,16 +19,19 @@ description: |
> > - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > stand-up edge detection interrupts)
> >
> > -allOf:
> > - - $ref: /schemas/interrupt-controller.yaml#
> > -
> > properties:
> > compatible:
> > - items:
> > - - enum:
> > - - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> > - - renesas,r9a07g054-irqc # RZ/V2L
> > - - const: renesas,rzg2l-irqc
> > + oneOf:
> > + - items:
> > + - enum:
> > + - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> > + - renesas,r9a07g054-irqc # RZ/V2L
> > + - const: renesas,rzg2l-irqc
> > +
> > + - items:
> > + - enum:
> > + - renesas,r9a07g043u-irqc # RZ/G2UL
> > + - const: renesas,rzg2ul-irqc
>
> I'm not sure it's worth splitting into RZ/G2L and RZ/G2UL alike
> variants, and adding the "renesas,rzg2ul-irqc" family-specific
> compatible value. You can easily handle the difference by the presence
> (or absence) of the "bus-err" interrupt source.
>
Yes, the only reason to add "renesas,rzg2ul-irqc" is to differentiate
RZ/Five later. I have not worked out on how this driver will work in
case of RZ/Five yet with PLIC (as we sifive plic driver as a chained
handler and then we have the RISC-V intc driver). If you insist I can
drop it for now and then later when we add RZ/FIve we could add a
check for compat string maybe?
> I understand there "renesas,r9a07g043f-irqc" will be added later to
> support RZ/Five?
>
Yes.
Cheers,
Prabhakar
Hi Prabhakar,
On Wed, Dec 21, 2022 at 10:06 PM Lad, Prabhakar
<[email protected]> wrote:
> On Wed, Dec 21, 2022 at 12:37 PM Geert Uytterhoeven
> <[email protected]> wrote:
> > On Wed, Dec 21, 2022 at 1:03 AM Prabhakar <[email protected]> wrote:
> > > From: Lad Prabhakar <[email protected]>
> > >
> > > Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> > > is almost identical to one found on the RZ/G2L SoC the only difference
> > > being it can support BUS_ERR_INT for which it has additional registers.
> > > Hence new generic compatible string "renesas,rzg2ul-irqc" is added for
> > > RZ/G2UL SoC.
> > >
> > > Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> > > interrupt-names property is added so that we can parse them based on
> > > names.
> > >
> > > While at it updated the example node to four spaces and added
> > > interrupt-names property.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > ---
> > > v1- > v2
> > > * Dropped RB tags
> > > * Added generic compatible string for rzg2ul
> > > * Added interrupt-names
> > > * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> > > * Updated example node with interrupt-names
> > > * Used 4 spaces for example node
> >
> > Thanks for the update!
> >
> > > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > @@ -19,16 +19,19 @@ description: |
> > > - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > > stand-up edge detection interrupts)
> > >
> > > -allOf:
> > > - - $ref: /schemas/interrupt-controller.yaml#
> > > -
> > > properties:
> > > compatible:
> > > - items:
> > > - - enum:
> > > - - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> > > - - renesas,r9a07g054-irqc # RZ/V2L
> > > - - const: renesas,rzg2l-irqc
> > > + oneOf:
> > > + - items:
> > > + - enum:
> > > + - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> > > + - renesas,r9a07g054-irqc # RZ/V2L
> > > + - const: renesas,rzg2l-irqc
> > > +
> > > + - items:
> > > + - enum:
> > > + - renesas,r9a07g043u-irqc # RZ/G2UL
> > > + - const: renesas,rzg2ul-irqc
> >
> > I'm not sure it's worth splitting into RZ/G2L and RZ/G2UL alike
> > variants, and adding the "renesas,rzg2ul-irqc" family-specific
> > compatible value. You can easily handle the difference by the presence
> > (or absence) of the "bus-err" interrupt source.
> >
> Yes, the only reason to add "renesas,rzg2ul-irqc" is to differentiate
> RZ/Five later. I have not worked out on how this driver will work in
> case of RZ/Five yet with PLIC (as we sifive plic driver as a chained
> handler and then we have the RISC-V intc driver). If you insist I can
> drop it for now and then later when we add RZ/FIve we could add a
> check for compat string maybe?
Given you already use "renesas,r9a07g043u-irqc" (note the "u") here,
you will have "renesas,r9a07g043f-irqc" to handle the (minor)
differences.
> > I understand there "renesas,r9a07g043f-irqc" will be added later to
> > support RZ/Five?
> >
> Yes.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Wed, Dec 21, 2022 at 12:18 PM Geert Uytterhoeven
<[email protected]> wrote:
>
> On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier <[email protected]> wrote:
> > On Wed, 21 Dec 2022 00:02:37 +0000,
> > Prabhakar <[email protected]> wrote:
> > >
> > > From: Lad Prabhakar <[email protected]>
> > >
> > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the
> > > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for
> > > which it has additional registers.
> > >
> > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string
> > > and now that we have interrupt-names property the driver code parses the
> > > interrupts based on names and for backward compatibility we fallback to
> > > parse interrupts based on index.
> > >
> > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC
> > > too and in future when the interrupt handler will be registered for
> > > BUS_ERR_INT we will have to implement a new callback.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
>
> > > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */
> > > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv,
> > > + struct device_node *np)
> > > +{
> > > + struct property *pp;
> > > unsigned int i;
> > > int ret;
> > >
> > > + /*
> > > + * first check if interrupt-names property exists if so parse them by name
> > > + * or else parse them by index for backward compatibility.
> > > + */
> > > + pp = of_find_property(np, "interrupt-names", NULL);
> > > + if (pp) {
> > > + char *irq_name;
> > > +
> > > + /* parse IRQ0-7 */
> > > + for (i = 0; i < IRQC_IRQ_COUNT; i++) {
> > > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i);
>
> %u
>
Ok.
> > > + if (!irq_name)
> > > + return -ENOMEM;
> > > +
> > > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i);
> >
> > Am I the only one that find it rather odd to construct a name from an
> > index, only to get another index back?
>
> The issue is that there are two number ranges ("irq%u" and "tint%u"),
> stored in a single interrupts property.
>
> An alternative solution would be to get rid of the "interrupt-names",
> and use two separate prefixed interrupts properties instead, like is
> common for e.g. gpios: "irq-interrupts" and "tint-interrupts".
>
Maybe I will read all the interrupts based on index only for all the
SoCs and we still add interrupt-names in dt bindings with the
dt_binding check we can make sure all the interrupts for each SoC
exist in the DT and the driver still reads them based on index. Does
that sound good?
Cheers,
Prabhakar
Hi Geert,
On Thu, Dec 22, 2022 at 8:19 AM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 10:06 PM Lad, Prabhakar
> <[email protected]> wrote:
> > On Wed, Dec 21, 2022 at 12:37 PM Geert Uytterhoeven
> > <[email protected]> wrote:
> > > On Wed, Dec 21, 2022 at 1:03 AM Prabhakar <[email protected]> wrote:
> > > > From: Lad Prabhakar <[email protected]>
> > > >
> > > > Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> > > > is almost identical to one found on the RZ/G2L SoC the only difference
> > > > being it can support BUS_ERR_INT for which it has additional registers.
> > > > Hence new generic compatible string "renesas,rzg2ul-irqc" is added for
> > > > RZ/G2UL SoC.
> > > >
> > > > Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> > > > interrupt-names property is added so that we can parse them based on
> > > > names.
> > > >
> > > > While at it updated the example node to four spaces and added
> > > > interrupt-names property.
> > > >
> > > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > > ---
> > > > v1- > v2
> > > > * Dropped RB tags
> > > > * Added generic compatible string for rzg2ul
> > > > * Added interrupt-names
> > > > * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> > > > * Updated example node with interrupt-names
> > > > * Used 4 spaces for example node
> > >
> > > Thanks for the update!
> > >
> > > > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > > @@ -19,16 +19,19 @@ description: |
> > > > - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> > > > stand-up edge detection interrupts)
> > > >
> > > > -allOf:
> > > > - - $ref: /schemas/interrupt-controller.yaml#
> > > > -
> > > > properties:
> > > > compatible:
> > > > - items:
> > > > - - enum:
> > > > - - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> > > > - - renesas,r9a07g054-irqc # RZ/V2L
> > > > - - const: renesas,rzg2l-irqc
> > > > + oneOf:
> > > > + - items:
> > > > + - enum:
> > > > + - renesas,r9a07g044-irqc # RZ/G2{L,LC}
> > > > + - renesas,r9a07g054-irqc # RZ/V2L
> > > > + - const: renesas,rzg2l-irqc
> > > > +
> > > > + - items:
> > > > + - enum:
> > > > + - renesas,r9a07g043u-irqc # RZ/G2UL
> > > > + - const: renesas,rzg2ul-irqc
> > >
> > > I'm not sure it's worth splitting into RZ/G2L and RZ/G2UL alike
> > > variants, and adding the "renesas,rzg2ul-irqc" family-specific
> > > compatible value. You can easily handle the difference by the presence
> > > (or absence) of the "bus-err" interrupt source.
> > >
> > Yes, the only reason to add "renesas,rzg2ul-irqc" is to differentiate
> > RZ/Five later. I have not worked out on how this driver will work in
> > case of RZ/Five yet with PLIC (as we sifive plic driver as a chained
> > handler and then we have the RISC-V intc driver). If you insist I can
> > drop it for now and then later when we add RZ/FIve we could add a
> > check for compat string maybe?
>
> Given you already use "renesas,r9a07g043u-irqc" (note the "u") here,
> you will have "renesas,r9a07g043f-irqc" to handle the (minor)
> differences.
>
Ok, so I'll revert back to the previous version of the patch and still
add the interrupt names.
Cheers,
Prabhakar
Hi Marc, Geert,
On Wed, Dec 21, 2022 at 10:31 AM Marc Zyngier <[email protected]> wrote:
>
> On Wed, 21 Dec 2022 00:02:36 +0000,
> Prabhakar <[email protected]> wrote:
> >
> > From: Lad Prabhakar <[email protected]>
> >
> > NMI interrupt is not an external interrupt as compared to the IRQ0-7 and
> > TINT0-31, this means we need to install the irq handler for NMI in the
> > IRQC driver and not include it as part of IRQ domain.
> >
> > This patch skips mapping NMI interrupt as part of the IRQ domain
> > hierarchy.
>
> Does it mean nobody can connect anything to it? Where is the handler
> you're mentioning for this NMI?
>
I got this clarified internally the NMI interrupt is an external
interrupt just like the other IRQ0-7/TINT interrupts. I'll drop this
patch in the next version.
Cheers,
Prabhakar
Hi Prabhakar,
On Thu, Dec 22, 2022 at 12:50 PM Lad, Prabhakar
<[email protected]> wrote:
> On Wed, Dec 21, 2022 at 12:18 PM Geert Uytterhoeven
> <[email protected]> wrote:
> > On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier <[email protected]> wrote:
> > > On Wed, 21 Dec 2022 00:02:37 +0000,
> > > Prabhakar <[email protected]> wrote:
> > > >
> > > > From: Lad Prabhakar <[email protected]>
> > > >
> > > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the
> > > > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for
> > > > which it has additional registers.
> > > >
> > > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string
> > > > and now that we have interrupt-names property the driver code parses the
> > > > interrupts based on names and for backward compatibility we fallback to
> > > > parse interrupts based on index.
> > > >
> > > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC
> > > > too and in future when the interrupt handler will be registered for
> > > > BUS_ERR_INT we will have to implement a new callback.
> > > >
> > > > Signed-off-by: Lad Prabhakar <[email protected]>
> >
> > > > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */
> > > > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv,
> > > > + struct device_node *np)
> > > > +{
> > > > + struct property *pp;
> > > > unsigned int i;
> > > > int ret;
> > > >
> > > > + /*
> > > > + * first check if interrupt-names property exists if so parse them by name
> > > > + * or else parse them by index for backward compatibility.
> > > > + */
> > > > + pp = of_find_property(np, "interrupt-names", NULL);
> > > > + if (pp) {
> > > > + char *irq_name;
> > > > +
> > > > + /* parse IRQ0-7 */
> > > > + for (i = 0; i < IRQC_IRQ_COUNT; i++) {
> > > > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i);
> >
> > %u
> >
> Ok.
>
> > > > + if (!irq_name)
> > > > + return -ENOMEM;
> > > > +
> > > > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i);
> > >
> > > Am I the only one that find it rather odd to construct a name from an
> > > index, only to get another index back?
> >
> > The issue is that there are two number ranges ("irq%u" and "tint%u"),
> > stored in a single interrupts property.
> >
> > An alternative solution would be to get rid of the "interrupt-names",
> > and use two separate prefixed interrupts properties instead, like is
> > common for e.g. gpios: "irq-interrupts" and "tint-interrupts".
> >
> Maybe I will read all the interrupts based on index only for all the
> SoCs and we still add interrupt-names in dt bindings with the
> dt_binding check we can make sure all the interrupts for each SoC
> exist in the DT and the driver still reads them based on index. Does
> that sound good?
Sure, sounds fine.
You can postpone parsing interrupt-names in the driver (until a new
SoC arrives that uses a different number of IRQ or TINT interrupts).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar,
On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> ETH1 respectively.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> @@ -6,6 +6,7 @@
> */
>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>
> / {
> @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
> compatible = "ethernet-phy-id0022.1640",
> "ethernet-phy-ieee802.3-c22";
> reg = <7>;
> + interrupt-parent = <&irqc>;
Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have
the irqc node yet, so I cannot take this as-is.
> + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
> rxc-skew-psec = <2400>;
> txc-skew-psec = <2400>;
> rxdv-skew-psec = <0>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Tue, Dec 27, 2022 at 1:02 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <[email protected]> wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> > ETH1 respectively.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > @@ -6,6 +6,7 @@
> > */
> >
> > #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
> > #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> >
> > / {
> > @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
> > compatible = "ethernet-phy-id0022.1640",
> > "ethernet-phy-ieee802.3-c22";
> > reg = <7>;
> > + interrupt-parent = <&irqc>;
>
> Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have
> the irqc node yet, so I cannot take this as-is.
>
Agreed, is it OK if we temporarily add the (above+below) properties in
the boards DTS and once we have full fledged support for RZ/Five we
move it back to the SoM DTSi (as done in this patch)?
Cheers,
Prabhakar
> > + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
> > rxc-skew-psec = <2400>;
> > txc-skew-psec = <2400>;
> > rxdv-skew-psec = <0>;
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
On 21/12/2022 01:02, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> NMI interrupt is not an external interrupt as compared to IRQ0-7 and
> TINT0-31 on RZ/G2L SoC, so there is no need for RZG2L_NMI macro.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v1 -> v2
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Thu, Dec 29, 2022 at 9:46 AM Krzysztof Kozlowski
<[email protected]> wrote:
> On 21/12/2022 01:02, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > NMI interrupt is not an external interrupt as compared to IRQ0-7 and
> > TINT0-31 on RZ/G2L SoC, so there is no need for RZG2L_NMI macro.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > v1 -> v2
>
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Given
https://lore.kernel.org/all/CA+V-a8vb-PfzMWX=ndF8nsyYVbkfYBkAQZ-UoS9zpQPndL871Q@mail.gmail.com
I think this patch is planned to be dropped, too?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Tue, Jan 3, 2023 at 8:43 AM Geert Uytterhoeven <[email protected]> wrote:
>
> On Thu, Dec 29, 2022 at 9:46 AM Krzysztof Kozlowski
> <[email protected]> wrote:
> > On 21/12/2022 01:02, Prabhakar wrote:
> > > From: Lad Prabhakar <[email protected]>
> > >
> > > NMI interrupt is not an external interrupt as compared to IRQ0-7 and
> > > TINT0-31 on RZ/G2L SoC, so there is no need for RZG2L_NMI macro.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > ---
> > > v1 -> v2
> >
> >
> > Acked-by: Krzysztof Kozlowski <[email protected]>
>
> Given
> https://lore.kernel.org/all/CA+V-a8vb-PfzMWX=ndF8nsyYVbkfYBkAQZ-UoS9zpQPndL871Q@mail.gmail.com
> I think this patch is planned to be dropped, too?
>
Yes that's correct (and I have dropped in the v3).
Cheers,
Prabhakar