This series adds SDHI/MMC support for the RZ/V2M SoC.
Thanks,
Fab
Fabrizio Castro (3):
dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support
mmc: renesas_sdhi: Add RZ/V2M compatible string
arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support
Phil Edworthy (1):
clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 1 +
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 48 +++++++++++++++++++
drivers/clk/renesas/r9a09g011-cpg.c | 34 +++++++++++++
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 11 +++++
4 files changed, 94 insertions(+)
--
2.34.1
From: Phil Edworthy <[email protected]>
Add SDHI/eMMC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <[email protected]>
---
This patch can clash with the below patch (which hasn't been reviewed
yet):
https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
drivers/clk/renesas/r9a09g011-cpg.c | 34 +++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index dd5e442ec4a9..8437b7d38e94 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -23,11 +23,14 @@
#define DIV_A DDIV_PACK(0x200, 0, 3)
#define DIV_B DDIV_PACK(0x204, 0, 2)
+#define DIV_D DDIV_PACK(0x204, 4, 2)
#define DIV_E DDIV_PACK(0x204, 8, 1)
#define DIV_W DDIV_PACK(0x328, 0, 3)
#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
+#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
+#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
enum clk_ids {
@@ -50,11 +53,14 @@ enum clk_ids {
CLK_PLL4,
CLK_DIV_A,
CLK_DIV_B,
+ CLK_DIV_D,
CLK_DIV_E,
CLK_DIV_W,
CLK_SEL_B,
CLK_SEL_B_D2,
+ CLK_SEL_D,
CLK_SEL_E,
+ CLK_SEL_SDI,
CLK_SEL_W0,
/* Module Clocks */
@@ -81,6 +87,14 @@ static const struct clk_div_table dtable_divb[] = {
{0, 0},
};
+
+static const struct clk_div_table dtable_divd[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_divw[] = {
{0, 6},
{1, 7},
@@ -94,8 +108,10 @@ static const struct clk_div_table dtable_divw[] = {
/* Mux clock tables */
static const char * const sel_b[] = { ".main", ".divb" };
+static const char * const sel_d[] = { ".main", ".divd" };
static const char * const sel_e[] = { ".main", ".dive" };
static const char * const sel_w[] = { ".main", ".divw" };
+static const char * const sel_sdi[] = { ".main", ".pll2_200" };
static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
/* External Clock Inputs */
@@ -115,11 +131,14 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
+ DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd),
DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL),
DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b),
+ DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
+ DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi),
DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
@@ -128,6 +147,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
+ DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0),
+ DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1),
+ DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2),
+ DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3),
+ DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4),
+ DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5),
+ DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6),
+ DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7),
+ DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8),
+ DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9),
+ DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10),
+ DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11),
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
@@ -151,6 +182,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
static const struct rzg2l_reset r9a09g011_resets[] = {
DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
+ DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6),
+ DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7),
+ DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8),
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
--
2.34.1
Document support for the SD Card/MMC interface on the Renesas
RZ/V2M (a.k.a. r9a09g011) SoC.
Signed-off-by: Fabrizio Castro <[email protected]>
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 7bfb10c62566..435773607489 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -59,6 +59,7 @@ properties:
- renesas,sdhi-r9a07g043 # RZ/G2UL
- renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
- renesas,sdhi-r9a07g054 # RZ/V2L
+ - renesas,sdhi-r9a09g011 # RZ/V2M
- const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
- items:
- enum:
--
2.34.1
The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface.
Add the relevant nodes to the SoC specific device tree.
Signed-off-by: Fabrizio Castro <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 0373ec409d54..dd35a8ff72ee 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -69,6 +69,54 @@ gic: interrupt-controller@82010000 {
clock-names = "clk";
};
+ sdhi0: mmc@85000000 {
+ compatible = "renesas,sdhi-r9a09g011",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x85000000 0 0x2000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
+ <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
+ <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
+ <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A09G011_SDI0_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sdhi1: mmc@85010000 {
+ compatible = "renesas,sdhi-r9a09g011",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x85010000 0 0x2000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
+ <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
+ <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
+ <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A09G011_SDI1_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ emmc: mmc@85020000 {
+ compatible = "renesas,sdhi-r9a09g011",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x85020000 0 0x2000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
+ <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
+ <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
+ <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A09G011_EMM_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
avb: ethernet@a3300000 {
compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
reg = <0 0xa3300000 0 0x800>;
--
2.34.1
On Tue, 13 Dec 2022 23:01:27 +0000, Fabrizio Castro wrote:
> Document support for the SD Card/MMC interface on the Renesas
> RZ/V2M (a.k.a. r9a09g011) SoC.
>
> Signed-off-by: Fabrizio Castro <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Tue, Dec 13, 2022 at 11:01:27PM +0000, Fabrizio Castro wrote:
> Document support for the SD Card/MMC interface on the Renesas
> RZ/V2M (a.k.a. r9a09g011) SoC.
>
> Signed-off-by: Fabrizio Castro <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Hi Fabrizio,
On Wed, Dec 14, 2022 at 12:01 AM Fabrizio Castro
<[email protected]> wrote:
> From: Phil Edworthy <[email protected]>
>
> Add SDHI/eMMC clock/reset entries to CPG driver.
>
> Signed-off-by: Phil Edworthy <[email protected]>
> ---
>
> This patch can clash with the below patch (which hasn't been reviewed
> yet):
> https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
I'll just ignore the overlap...
I couldn't review the clock parents, as that information seems to
be restricted, but the rest LGTM.
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-clk-for-v6.3.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, 14 Dec 2022 at 00:01, Fabrizio Castro
<[email protected]> wrote:
>
> Document support for the SD Card/MMC interface on the Renesas
> RZ/V2M (a.k.a. r9a09g011) SoC.
>
> Signed-off-by: Fabrizio Castro <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> index 7bfb10c62566..435773607489 100644
> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> @@ -59,6 +59,7 @@ properties:
> - renesas,sdhi-r9a07g043 # RZ/G2UL
> - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
> - renesas,sdhi-r9a07g054 # RZ/V2L
> + - renesas,sdhi-r9a09g011 # RZ/V2M
> - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
> - items:
> - enum:
> --
> 2.34.1
>
Hi Fabrizio,
On Wed, Dec 14, 2022 at 12:02 AM Fabrizio Castro
<[email protected]> wrote:
> The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface.
> Add the relevant nodes to the SoC specific device tree.
>
> Signed-off-by: Fabrizio Castro <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v6.3.
Note that this causes "make dtbs_check" failures, due to a bug in
the bindings. I have sent a fix.
https://lore.kernel.org/054c9f4dbb0bb1525f780d1e85c724436465c20c.1673270716.git.geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
>
> Hi Fabrizio,
>
> On Wed, Dec 14, 2022 at 12:02 AM Fabrizio Castro
> <[email protected]> wrote:
> > The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface.
> > Add the relevant nodes to the SoC specific device tree.
> >
> > Signed-off-by: Fabrizio Castro <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> i.e. will queue in renesas-devel for v6.3.
>
> Note that this causes "make dtbs_check" failures, due to a bug in
> the bindings. I have sent a fix.
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ker
> nel.org%2F054c9f4dbb0bb1525f780d1e85c724436465c20c.1673270716.git.geert%2B
> renesas%40glider.be&data=05%7C01%7Cfabrizio.castro.jz%40renesas.com%7Cb621
> 0a13c0e64f5719a408daf245694d%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C
> 638088677177461554%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2l
> uMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=cHhpiy1cwPTiri2I
> l1j7Ck6iwR9DEdvlc8egJDBc2cM%3D&reserved=0
Thanks for that!
Fab
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds