This series adds the plain basic support for booting a bare
kernel on the RZ/N1D-DB Board. It's been trimmed to the strict
minimum as a 'base', further patches that will add the
rest of the support.
Special note on the clock driver: Current usage of the clocks on Linux
involves Linux 'claiming' all of them, disabling the one it doesn't
need and so on.
On *this* architecture it can't be done, there is at least one other
OS running on the CM3 core that claims it's own clock; Linux can claim
some others but definitely not start disabling stuff it isn't supposed to.
Thanks for the comments on the previous versions!
v6:
+ Fix for suggestion by Geert Uytterhoeven
+ Removed "renesas,rzn1" from the board bindings
+ Removed patches already merged.
+ Removed reboot driver
+ Added a whole clock infrastructure.
+ Rebased on next-20180517
v5:
+ Given the problems I have with getting in some structure around the
sysctrl block, I've removed the MFD, I've now attached the reboot
driver on it's own pair of registers.
+ Rebased on next-20180417
v4:
+ Fixes for suggestions by Simon Horman
+ Fixes for suggestions by Jacopo Mondi
+ Fixes for suggestions by Geert Uytterhoeven
+ Renamed the r9a06g0xx.dtsi file, given up on trying to get a family
common file in, so dropped potential RZ/N1S support and now only
focus on RZ/N1D for this patchset.
+ Added 'always-on' to the architected timer node, because it is.
+ Added ARCH_R9A06G032, to match others patterns like RCAR
+ Sorted the .dts files, added empty lines as required.
+ Fixed patch prefixes to match git-log for bindings&dts
+ Merged board .dts & Makefile changes together
+ Rebased on next-20180410
v3:
+ Fixes for suggestions by Geert Uytterhoeven
+ Removed SoC Specific renesas,r9a06g032-xxx, as it's not needed for now.
+ Kept renesas,rzn1 as a family/generic for this family.
+ Fixed a couple of the commit messages.
+ Added Geert's Reviewed-By where appropriate.
v2:
+ Fixes for suggestions by Simon Horman
+ Fixes for suggestions by Rob Herring
+ Fixes for suggestions by Geert Uytterhoeven
+ Removed the mach file
+ Added a MFD base for the sysctrl block
+ Added a regmap based sub driver for the reboot handler
+ Renamed the files to match shmobile conventions
+ Adapted the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
dt-bindings: arm: Document the RZN1D-DB board
dt-bindings: Add the rzn1-clocks.h file
dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver
ARM: dts: Renesas RZ/N1 SoC base device tree file
ARM: dts: Renesas RZN1D-DB Board base file
clk: renesas: Renesas RZ/N1 clock driver
Documentation/devicetree/bindings/arm/shmobile.txt | 5 +-
.../bindings/clock/renesas,rzn1-clocks.txt | 44 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 29 +
arch/arm/boot/dts/r9a06g032.dtsi | 86 +++
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/rzn1-clocks.c | 814 +++++++++++++++++++++
include/dt-bindings/clock/rzn1-clocks.h | 187 +++++
9 files changed, 1172 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
create mode 100644 drivers/clk/renesas/rzn1-clocks.c
create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
--
2.7.4
This adds the constants necessary to use the renesas,rzn1-clocks driver.
Signed-off-by: Michel Pollet <[email protected]>
---
include/dt-bindings/clock/rzn1-clocks.h | 187 ++++++++++++++++++++++++++++++++
1 file changed, 187 insertions(+)
create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
diff --git a/include/dt-bindings/clock/rzn1-clocks.h b/include/dt-bindings/clock/rzn1-clocks.h
new file mode 100644
index 0000000..8a73db2
--- /dev/null
+++ b/include/dt-bindings/clock/rzn1-clocks.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/N1 clock IDs
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <[email protected]>, <[email protected]>
+ * Derived from zx-reboot.c
+ */
+
+#ifndef __DT_BINDINGS_RZN1_CLOCK_H__
+#define __DT_BINDINGS_RZN1_CLOCK_H__
+
+#define RZN1_CLKOUT 0
+#define RZN1_CLK_PLL_USB 1
+#define RZN1_CLK_48 1 /* AKA CLK_PLL_USB */
+#define RZN1_CLKOUT_D10 2
+#define RZN1_CLKOUT_D16 3
+#define RZN1_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
+#define RZN1_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
+#define RZN1_CLKOUT_D160 4
+#define RZN1_CLKOUT_D1OR2 5
+#define RZN1_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
+#define RZN1_CLKOUT_D20 6
+#define RZN1_CLK50 6 /* AKA CLKOUT_D20 */
+#define RZN1_CLKOUT_D40 7
+#define RZN1_CLK25 7 /* AKA CLKOUT_D40 */
+#define RZN1_CLKOUT_D5 8
+#define RZN1_CLKOUT_D8 9
+#define RZN1_CLK125 9 /* AKA CLKOUT_D8 */
+#define RZN1_DIV_ADC 10
+#define RZN1_DIV_I2C 11
+#define RZN1_DIV_NAND 12
+#define RZN1_DIV_P1_PG 13
+#define RZN1_DIV_P2_PG 14
+#define RZN1_DIV_P3_PG 15
+#define RZN1_DIV_P4_PG 16
+#define RZN1_DIV_P5_PG 17
+#define RZN1_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
+#define RZN1_DIV_P6_PG 18
+#define RZN1_DIV_QSPI0 19
+#define RZN1_DIV_QSPI1 20
+#define RZN1_DIV_REF_SYNC 21
+#define RZN1_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
+#define RZN1_DIV_SDIO0 22
+#define RZN1_DIV_SDIO1 23
+#define RZN1_DIV_SWITCH 24
+#define RZN1_DIV_UART 25
+#define RZN1_CLK_25_PG4 26
+#define RZN1_CLK_25_PG5 27
+#define RZN1_CLK_25_PG6 28
+#define RZN1_CLK_25_PG7 29
+#define RZN1_CLK_25_PG8 30
+#define RZN1_CLK_ADC 31
+#define RZN1_CLK_ECAT100 32
+#define RZN1_CLK_HSR100 33
+#define RZN1_CLK_I2C0 34
+#define RZN1_CLK_I2C1 35
+#define RZN1_CLK_MII_REF 36
+#define RZN1_CLK_NAND 37
+#define RZN1_CLK_NOUSBP2_PG6 38
+#define RZN1_CLK_P1_PG2 39
+#define RZN1_CLK_P1_PG3 40
+#define RZN1_CLK_P1_PG4 41
+#define RZN1_CLK_P4_PG3 42
+#define RZN1_CLK_P4_PG4 43
+#define RZN1_CLK_P6_PG1 44
+#define RZN1_CLK_P6_PG2 45
+#define RZN1_CLK_P6_PG3 46
+#define RZN1_CLK_P6_PG4 47
+#define RZN1_CLK_PCI_USB 48
+#define RZN1_CLK_QSPI0 49
+#define RZN1_CLK_QSPI1 50
+#define RZN1_CLK_RGMII_REF 51
+#define RZN1_CLK_RMII_REF 52
+#define RZN1_CLK_SDIO0 53
+#define RZN1_CLK_SDIO1 54
+#define RZN1_CLK_SERCOS100 55
+#define RZN1_CLK_SLCD 56
+#define RZN1_CLK_SPI0 57
+#define RZN1_CLK_SPI1 58
+#define RZN1_CLK_SPI2 59
+#define RZN1_CLK_SPI3 60
+#define RZN1_CLK_SPI4 61
+#define RZN1_CLK_SPI5 62
+#define RZN1_CLK_SWITCH 63
+#define RZN1_DIV_MOTOR 64
+#define RZN1_HCLK_ECAT125 65
+#define RZN1_HCLK_PINCONFIG 66
+#define RZN1_HCLK_SERCOS 67
+#define RZN1_HCLK_SGPIO2 68
+#define RZN1_HCLK_SGPIO3 69
+#define RZN1_HCLK_SGPIO4 70
+#define RZN1_HCLK_TIMER0 71
+#define RZN1_HCLK_TIMER1 72
+#define RZN1_HCLK_USBF 73
+#define RZN1_HCLK_USBH 74
+#define RZN1_HCLK_USBPM 75
+#define RZN1_CLK_48_PG_F 76
+#define RZN1_CLK_48_PG4 77
+#define RZN1_CLK_DDRPHY_PLLCLK_D4 78
+#define RZN1_CLK_ECAT100_D4 79
+#define RZN1_CLK_HSR100_D2 80
+#define RZN1_CLK_REF_SYNC_D4 81
+#define RZN1_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
+#define RZN1_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
+#define RZN1_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
+#define RZN1_CLK_REF_SYNC_D8 82
+#define RZN1_CLK_SERCOS100_D2 83
+#define RZN1_DIV_CA7 84
+#define RZN1_CLK_A7MP 84 /* AKA DIV_CA7 */
+#define RZN1_HCLK_CAN0 85
+#define RZN1_HCLK_CAN1 86
+#define RZN1_HCLK_DELTASIGMA 87
+#define RZN1_HCLK_PWMPTO 88
+#define RZN1_HCLK_RSV 89
+#define RZN1_HCLK_SGPIO0 90
+#define RZN1_HCLK_SGPIO1 91
+#define RZN1_RTOS_MDC 92
+#define RZN1_CLK_CM3 93
+#define RZN1_CLK_DDRC 94
+#define RZN1_CLK_ECAT25 95
+#define RZN1_CLK_HSR50 96
+#define RZN1_CLK_HW_RTOS 97
+#define RZN1_CLK_SERCOS50 98
+#define RZN1_HCLK_ADC 99
+#define RZN1_HCLK_CM3 100
+#define RZN1_HCLK_CRYPTO_EIP150 101
+#define RZN1_HCLK_CRYPTO_EIP93 102
+#define RZN1_HCLK_DDRC 103
+#define RZN1_HCLK_DMA0 104
+#define RZN1_HCLK_DMA1 105
+#define RZN1_HCLK_GMAC0 106
+#define RZN1_HCLK_GMAC1 107
+#define RZN1_HCLK_GPIO0 108
+#define RZN1_HCLK_GPIO1 109
+#define RZN1_HCLK_GPIO2 110
+#define RZN1_HCLK_HSR 111
+#define RZN1_HCLK_I2C0 112
+#define RZN1_HCLK_I2C1 113
+#define RZN1_HCLK_LCD 114
+#define RZN1_HCLK_MSEBI_M 115
+#define RZN1_HCLK_MSEBI_S 116
+#define RZN1_HCLK_NAND 117
+#define RZN1_HCLK_PG_I 118
+#define RZN1_HCLK_PG19 119
+#define RZN1_HCLK_PG20 120
+#define RZN1_HCLK_PG3 121
+#define RZN1_HCLK_PG4 122
+#define RZN1_HCLK_QSPI0 123
+#define RZN1_HCLK_QSPI1 124
+#define RZN1_HCLK_ROM 125
+#define RZN1_HCLK_RTC 126
+#define RZN1_HCLK_SDIO0 127
+#define RZN1_HCLK_SDIO1 128
+#define RZN1_HCLK_SEMAP 129
+#define RZN1_HCLK_SPI0 130
+#define RZN1_HCLK_SPI1 131
+#define RZN1_HCLK_SPI2 132
+#define RZN1_HCLK_SPI3 133
+#define RZN1_HCLK_SPI4 134
+#define RZN1_HCLK_SPI5 135
+#define RZN1_HCLK_SWITCH 136
+#define RZN1_HCLK_SWITCH_RG 137
+#define RZN1_HCLK_UART0 138
+#define RZN1_HCLK_UART1 139
+#define RZN1_HCLK_UART2 140
+#define RZN1_HCLK_UART3 141
+#define RZN1_HCLK_UART4 142
+#define RZN1_HCLK_UART5 143
+#define RZN1_HCLK_UART6 144
+#define RZN1_HCLK_UART7 145
+#define RZN1_CLK_UART0 146
+#define RZN1_CLK_UART1 147
+#define RZN1_CLK_UART2 148
+#define RZN1_CLK_UART3 149
+#define RZN1_CLK_UART4 150
+#define RZN1_CLK_UART5 151
+#define RZN1_CLK_UART6 152
+#define RZN1_CLK_UART7 153
+
+#define RZN1_UART_GROUP_012 154
+#define RZN1_UART_GROUP_34567 155
+
+#define RZN1_CLOCK_COUNT (RZN1_UART_GROUP_34567 + 1)
+
+#endif /* __DT_BINDINGS_RZN1_CLOCK_H__ */
--
2.7.4
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index d8cf740..89b4a38 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
-
+ - RZ/N1D (R9A06G032)
+ compatible = "renesas,r9a06g032"
Boards:
@@ -112,6 +113,8 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
+ - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+ compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
--
2.7.4
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <[email protected]>
---
arch/arm/boot/dts/r9a06g032.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
new file mode 100644
index 0000000..c7764c7
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rzn1-clock.h>
+
+/ {
+ compatible = "renesas,r9a06g032", "renesas,rzn1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock RZN1_DIV_CA7>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ clock: clocks@4000c000 {
+ compatible = "renesas,r9a06g032-clocks",
+ "renesas,rzn1-clocks";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@40060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&clock RZN1_CLK_UART0>;
+ clock-names = "baudclk";
+ status = "disabled";
+ };
+
+ gic: gic@44101000 {
+ compatible = "arm,cortex-a7-gic", "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x44101000 0x1000>, /* Distributer */
+ <0x44102000 0x2000>, /* CPU interface */
+ <0x44104000 0x2000>, /* Virt interface control */
+ <0x44106000 0x2000>; /* Virt CPU interface */
+ interrupts =
+ <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ timer {
+ compatible = "arm,cortex-a7-timer",
+ "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ arm,cpu-registers-not-fw-configured;
+ always-on;
+ interrupts =
+ <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.7.4
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
to provide the SoC clock infrastructure for Linux.
This documents the driver bindings.
Signed-off-by: Michel Pollet <[email protected]>
---
.../bindings/clock/renesas,rzn1-clocks.txt | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
new file mode 100644
index 0000000..0c41137
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
@@ -0,0 +1,44 @@
+* Renesas RZ/N1 Clock Driver
+
+This driver provides the clock infrastructure used by all the other drivers.
+
+One of the 'special' feature of this infrastructure is that Linux doesn't
+necessary 'own' all the clocks on the SoC, some other OS runs on
+the Cortex-M3 core and that OS can access and claim it's own clocks.
+
+Required Properties:
+
+ - compatible: Must be
+ - "renesas,r9a06g032-clocks" for the RZ/N1D
+ and "renesas,rzn1-clocks" as a fallback.
+ - reg: Base address and length of the memory resource used by the driver
+ - #clock-cells: Must be 1
+
+Examples
+--------
+
+ - Clock driver device node:
+
+ clock: clocks@4000c000 {
+ compatible = "renesas,r9a06g032-clocks",
+ "renesas,rzn1-clocks";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ };
+
+
+ - Other drivers can use the clocks as in:
+
+ uart0: serial@40060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&clock RZN1_CLK_UART0>;
+ clock-names = "baudclk";
+ };
+ Note the use of RZN1_CLK_UART0 -- these constants are declared in
+ the rzn1-clocks.h header file. These are not hardware based constants
+ and are Linux specific.
--
2.7.4
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 29 +++++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4753b0..6157897 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -814,6 +814,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
+ r9a06g032-rzn1d400-db.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-evb.dtb \
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 0000000..5fc2c40
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+
+/ {
+ model = "RZN1D-DB Board";
+ compatible = "renesas,rzn1d400-db",
+ "renesas,r9a06g032", "renesas,rzn1";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.7.4
This provides a clock driver for the Renesas RZ/N1 parts (#R09A06G0xx).
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet <[email protected]>
---
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/rzn1-clocks.c | 814 ++++++++++++++++++++++++++++++++++++++
3 files changed, 821 insertions(+)
create mode 100644 drivers/clk/renesas/rzn1-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f9ba71311..bdb8129 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,6 +21,7 @@ config CLK_RENESAS
select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
+ select CLK_RZN1 if ARCH_RZN1
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@@ -151,6 +152,11 @@ config CLK_RCAR_USB2_CLOCK_SEL
help
This is a driver for R-Car USB2 clock selector
+config CLK_RZN1
+ bool "Renesas RZ/N1 clock driver"
+ help
+ This is a driver for RZ/N1 clocks
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index fe5bac9..754281c 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
+obj-$(CONFIG_CLK_RZN1) += rzn1-clocks.o
# Generic
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
diff --git a/drivers/clk/renesas/rzn1-clocks.c b/drivers/clk/renesas/rzn1-clocks.c
new file mode 100644
index 0000000..06c176b
--- /dev/null
+++ b/drivers/clk/renesas/rzn1-clocks.c
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <[email protected]>, <[email protected]>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <dt-bindings/clock/rzn1-clocks.h>
+
+struct rzn1_gate {
+ uint16_t gate, reset, ready, midle,
+ scon, mirack, mistat;
+};
+
+/* This is used to describe a clock for instantiation */
+struct rzn1_clkdesc {
+ const char *name;
+ uint32_t type: 3;
+ uint32_t index: 8;
+ uint32_t source : 8; /* source index + 1 (0 == none) */
+ /* these are used to populate the bitsel struct */
+ union {
+ struct rzn1_gate gate;
+ /* for dividers */
+ struct {
+ unsigned int div_min : 10, div_max : 10, reg: 10;
+ uint16_t div_table[4];
+ };
+ /* For fixed-factor ones */
+ uint16_t div;
+ unsigned int factor;
+ unsigned int frequency;
+ /* for dual gate */
+ struct {
+ uint16_t group : 1, index: 3;
+ uint16_t sel, g1, r1, g2, r2;
+ } dual;
+ };
+} __packed;
+
+#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
+ { .gate = _clk, .reset = _rst, \
+ .ready = _rdy, .midle = _midle, \
+ .scon = _scon, .mirack = _mirack, .mistat = _mistat }
+#define D_GATE(_idx, _n, _src, ...) \
+ { .type = K_GATE, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .gate = I_GATE(__VA_ARGS__), }
+#define D_FC(_idx, _n, _freq) \
+ { .type = K_FC, .index = RZN1_##_idx, .name = _n, .frequency = _freq, }
+#define D_FFC(_idx, _n, _src, _div) \
+ { .type = K_FFC, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .div = _div, }
+#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
+ { .type = K_DIV, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .reg = _reg, .div_min = _min, .div_max = _max, \
+ .div_table = { __VA_ARGS__ } }
+#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
+ { .type = K_DUALGATE, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .dual = { .group = _g, .index = _gi, \
+ .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
+
+enum { K_GATE = 0, K_FFC, K_FC, K_DIV, K_BITSEL, K_DUALGATE };
+
+static const struct rzn1_clkdesc rzn1_clocks[] __initconst = {
+ D_FC(CLKOUT, "clkout", 1000000000),
+ D_FC(CLK_PLL_USB, "clk_pll_usb", 48000000),
+ D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
+ D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
+ D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
+ D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
+ D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
+ D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
+ D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
+ D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
+ D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
+ D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
+ D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
+ D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
+ D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
+ D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
+ D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
+ D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
+ D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
+ D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
+ D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
+ D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
+ D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
+ D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
+ D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
+ D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
+ D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
+ D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
+ D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
+ D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
+ D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
+ D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
+ D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
+ D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
+ D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
+ D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
+ D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
+ D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
+ D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
+ D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
+ D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
+ D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
+ D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
+ D_GATE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
+ D_GATE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
+ D_GATE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
+ D_GATE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
+ D_GATE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
+ D_GATE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
+ D_GATE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
+ D_GATE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
+ D_GATE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
+ D_GATE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
+ D_GATE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
+ D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
+ D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
+ D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
+ D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
+ D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
+ D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
+ D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
+ D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
+ D_GATE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
+ D_GATE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
+ D_GATE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
+ D_GATE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
+ D_GATE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
+ D_GATE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
+ D_GATE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
+ D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
+ D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
+ D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
+ D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
+ D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
+ D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
+ D_GATE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
+ D_GATE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
+ D_GATE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
+ D_GATE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
+ D_GATE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
+ D_GATE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
+ D_GATE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
+ D_GATE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
+ D_GATE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
+ D_GATE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
+ D_GATE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
+ D_GATE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
+ D_GATE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
+ D_GATE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
+ D_GATE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
+ D_GATE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
+ D_GATE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
+ D_GATE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
+ D_GATE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
+ D_GATE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
+ D_GATE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
+ D_GATE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
+ D_GATE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
+ D_GATE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
+ D_GATE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
+ D_GATE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
+ D_GATE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
+ D_GATE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
+ D_GATE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
+ D_GATE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
+ D_GATE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
+ D_GATE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
+ D_GATE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
+ D_GATE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
+ D_GATE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
+ D_GATE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
+ D_GATE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
+ D_GATE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
+ D_GATE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
+ D_GATE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
+ D_GATE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
+ D_GATE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
+ /*
+ * These are not hardware clocks, but are needed to handle the special
+ * case where we have a 'selector bit' that doesn't just change the
+ * parent for a clock, but also the gate it's suposed to use.
+ */
+ {
+ .index = RZN1_UART_GROUP_012,
+ .name = "uart_group_012",
+ .type = K_BITSEL,
+ .source = 1 + RZN1_DIV_UART,
+ /* RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
+ .dual.sel = ((0xec / 4) << 5) | 24,
+ .dual.group = 0,
+ },
+ {
+ .index = RZN1_UART_GROUP_34567,
+ .name = "uart_group_34567",
+ .type = K_BITSEL,
+ .source = 1 + RZN1_DIV_P2_PG,
+ /* RZN1_SYSCTRL_REG_PWRCTRL_PG0_0 */
+ .dual.sel = ((0x34 / 4) << 5) | 30,
+ .dual.group = 1,
+ },
+ D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
+ D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
+ D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
+ D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
+ D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
+ D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
+ D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
+ D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
+};
+
+struct rzn1_priv {
+ struct clk_onecell_data data;
+ spinlock_t lock;
+ void __iomem *reg;
+};
+
+/* register/bit pairs are encoded as an uint16_t */
+static void clk_rdesc_set(
+ struct rzn1_priv *clocks,
+ uint16_t one, unsigned int on)
+{
+ u32 *reg = ((u32 *)clocks->reg) + (one >> 5);
+ u32 val = clk_readl(reg);
+
+ val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
+ clk_writel(val, reg);
+}
+
+static int clk_rdesc_get(
+ struct rzn1_priv *clocks,
+ uint16_t one)
+{
+ u32 *reg = ((u32 *)clocks->reg) + (one >> 5);
+ u32 val = clk_readl(reg);
+
+ return !!(val & (1U << (one & 0x1f)));
+}
+
+/*
+ * This implements the RZ/N1 clock gate 'driver'. We cannot use the system's
+ * clock gate framework as the gates on the RZ/N1 have a special enabling
+ * sequence, therefore we use this little proxy to call into the general
+ * clock gate API in rznr-clock.c that implements what is needed.
+ */
+struct rzn1_clk_gate {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ unsigned read_only : 1;
+
+ struct rzn1_gate gate;
+};
+
+#define to_rzn1_gate(_hw) container_of(_hw, struct rzn1_clk_gate, hw)
+
+static void rzn1_clk_gate_set(
+ struct rzn1_priv *clocks,
+ struct rzn1_gate *g, int on)
+{
+ unsigned long flags;
+
+ WARN_ON(!g->gate);
+
+ spin_lock_irqsave(&clocks->lock, flags);
+ clk_rdesc_set(clocks, g->gate, on);
+ /* De-assert reset */
+ if (g->reset)
+ clk_rdesc_set(clocks, g->reset, 1);
+ spin_unlock_irqrestore(&clocks->lock, flags);
+
+ /* Hardware manual recommends 5us delay after enabling clock & reset */
+ udelay(5);
+
+ /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
+ * associated SLVRDY bit in the System Controller that needs to be set
+ * so that the FlexWAY bus fabric passes on the read/write requests.
+ */
+ if (g->ready || g->midle) {
+ spin_lock_irqsave(&clocks->lock, flags);
+ if (g->ready)
+ clk_rdesc_set(clocks, g->ready, on);
+ /* Clear 'Master Idle Request' bit */
+ if (g->midle)
+ clk_rdesc_set(clocks, g->midle, !on);
+ spin_unlock_irqrestore(&clocks->lock, flags);
+ }
+ /* Note: We don't wait for FlexWAY Socket Connection signal */
+}
+
+static int rzn1_clk_gate_enable(struct clk_hw *hw)
+{
+ struct rzn1_clk_gate *g = to_rzn1_gate(hw);
+
+ rzn1_clk_gate_set(g->clocks, &g->gate, 1);
+ return 0;
+}
+
+static void rzn1_clk_gate_disable(struct clk_hw *hw)
+{
+ struct rzn1_clk_gate *g = to_rzn1_gate(hw);
+
+ if (!g->read_only)
+ rzn1_clk_gate_set(g->clocks, &g->gate, 0);
+ else
+ pr_debug("%s %s: disallowed\n", __func__,
+ __clk_get_name(hw->clk));
+}
+
+static int rzn1_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct rzn1_clk_gate *g = to_rzn1_gate(hw);
+
+ return clk_rdesc_get(g->clocks, g->gate.gate);
+}
+
+static const struct clk_ops rzn1_clk_gate_ops = {
+ .enable = rzn1_clk_gate_enable,
+ .disable = rzn1_clk_gate_disable,
+ .is_enabled = rzn1_clk_gate_is_enabled,
+};
+
+static struct clk *rzn1_register_gate(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc)
+{
+ struct clk *clk;
+ struct rzn1_clk_gate *g;
+ struct clk_init_data init;
+
+ g = kzalloc(sizeof(struct rzn1_clk_gate), GFP_KERNEL);
+ if (!g)
+ return NULL;
+
+ init.name = desc->name;
+ init.ops = &rzn1_clk_gate_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ g->clocks = clocks;
+ g->index = desc->index;
+ g->gate = desc->gate;
+ g->hw.init = &init;
+ g->read_only = 0;
+
+ clk = clk_register(NULL, &g->hw);
+ if (IS_ERR(clk)) {
+ kfree(g);
+ return NULL;
+ }
+ /*
+ * important here, some clocks are already in use by the CM3, we
+ * have to assume they are not Linux's to play with and try to disable
+ * at the end of the boot!
+ * Therefore we increase the clock usage count by arbitrarily enabling
+ * the clock, allowing it to stay untouched at the end of the boot.
+ */
+ g->read_only = rzn1_clk_gate_is_enabled(&g->hw);
+ if (g->read_only)
+ pr_debug("%s was enabled, making read-only\n", desc->name);
+ return clk;
+}
+
+struct rzn1_clk_div {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ u16 reg;
+ u16 min, max;
+ uint8_t table_size;
+ u16 table[8]; /* we know there are no more than 8 */
+};
+
+#define to_rzn1_divider(_hw) container_of(_hw, struct rzn1_clk_div, hw)
+
+static unsigned long rzn1_divider_recalc_rate(
+ struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct rzn1_clk_div *clk = to_rzn1_divider(hw);
+ u32 *reg = ((u32 *)clk->clocks->reg) + clk->reg;
+ long div = clk_readl(reg);
+
+ if (div < clk->min)
+ div = clk->min;
+ else if (div > clk->max)
+ div = clk->max;
+ return DIV_ROUND_UP(parent_rate, div);
+}
+
+/*
+ * Attempts to find a value that is in range of min,max,
+ * and if a table of set dividers was specified for this
+ * register, try to find the fixed divider that is the closest
+ * to the target frequency
+ */
+static long rzn1_divider_clamp_div(
+ struct rzn1_clk_div *clk,
+ unsigned long rate, unsigned long prate)
+{
+ /* + 1 to cope with rates that have the remainder dropped */
+ long div = DIV_ROUND_UP(prate, rate + 1);
+ int i;
+
+ if (div <= clk->min)
+ return clk->min;
+ if (div >= clk->max)
+ return clk->max;
+
+ for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
+ if (div >= clk->table[i] && div <= clk->table[i+1]) {
+ unsigned long m = rate -
+ DIV_ROUND_UP(prate, clk->table[i]);
+ unsigned long p =
+ DIV_ROUND_UP(prate, clk->table[i + 1]) -
+ rate;
+ /*
+ * select the divider that generates
+ * the value closest to the ideal frequency
+ */
+ div = p >= m ? clk->table[i] : clk->table[i + 1];
+ return div;
+ }
+ }
+ return div;
+}
+
+static long rzn1_divider_round_rate(
+ struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct rzn1_clk_div *clk = to_rzn1_divider(hw);
+ long div = DIV_ROUND_UP(*prate, rate);
+
+ pr_devel("%s %pC %ld (prate %ld) (wanted div %ld)\n", __func__,
+ hw->clk, rate, *prate, div);
+ pr_devel(" min %d (%ld) max %d (%ld)\n",
+ clk->min, DIV_ROUND_UP(*prate, clk->min),
+ clk->max, DIV_ROUND_UP(*prate, clk->max));
+
+ div = rzn1_divider_clamp_div(clk, rate, *prate);
+ /*
+ * this is a hack. Currently the serial driver asks for a clock rate
+ * that is 16 times the baud rate -- and that is wildly outside the
+ * range of the UART divider, somehow there is no provision for that
+ * case of 'let the divider as is if outside range'.
+ * The serial driver *shouldn't* play with these clocks anyway, there's
+ * several uarts attached to this divider, and changing this impacts
+ * everyone.
+ */
+ if (clk->index == RZN1_DIV_UART) {
+ pr_devel("%s div uart hack!\n", __func__);
+ return clk_get_rate(hw->clk);
+ }
+ pr_devel("%s %pC %ld / %ld = %ld\n", __func__, hw->clk,
+ *prate, div, DIV_ROUND_UP(*prate, div));
+ return DIV_ROUND_UP(*prate, div);
+}
+
+static int rzn1_divider_set_rate(
+ struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct rzn1_clk_div *clk = to_rzn1_divider(hw);
+ /* + 1 to cope with rates that have the remainder dropped */
+ u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
+ u32 *reg = ((u32 *)clk->clocks->reg) + clk->reg;
+
+ pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
+ rate, parent_rate, div);
+
+ /*
+ * Need to write the bit 31 with the divider value to
+ * latch it. Technically we should wait until it has been
+ * cleared too.
+ * TODO: Find whether this callback is sleepable, in case
+ * the hardware /does/ require some sort of spinloop here.
+ */
+ clk_writel(div | (1U << 31), reg);
+
+ return 0;
+}
+
+static const struct clk_ops rzn1_clk_div_ops = {
+ .recalc_rate = rzn1_divider_recalc_rate,
+ .round_rate = rzn1_divider_round_rate,
+ .set_rate = rzn1_divider_set_rate,
+};
+
+static struct clk *rzn1_register_divider(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc)
+{
+ struct rzn1_clk_div *div;
+ struct clk *clk;
+ struct clk_init_data init;
+ int i;
+
+ if (desc->index == RZN1_CLKOUT_D1OR2) {
+ /*
+ * TODO: handle bizare case of the divider that is set by an
+ * external pin, for the DDR2/3 switch
+ */
+ }
+
+ div = kzalloc(sizeof(struct rzn1_clk_div), GFP_KERNEL);
+ if (!div)
+ return NULL;
+
+ init.name = desc->name;
+ init.ops = &rzn1_clk_div_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ div->clocks = clocks;
+ div->index = desc->index;
+ div->reg = desc->reg;
+ div->hw.init = &init;
+ div->min = desc->div_min;
+ div->max = desc->div_max;
+ /* populate (optional) divider table fixed values */
+ for (i = 0; i < ARRAY_SIZE(div->table) &&
+ i < ARRAY_SIZE(desc->div_table) &&
+ desc->div_table[i]; i++) {
+ div->table[div->table_size++] = desc->div_table[i];
+ }
+
+ clk = clk_register(NULL, &div->hw);
+ if (IS_ERR(clk)) {
+ kfree(div);
+ return NULL;
+ }
+ return clk;
+}
+
+/*
+ * This clock provider handles the case of the RZN1 where you have peripherals
+ * that have two potential clock source and two gates, one for each of the
+ * clock source - the used clock source (for all sub clocks) is selected by a
+ * single bit.
+ * That single bit affects all sub-clocks, and therefore needs to change the
+ * active gate (and turn the others off) and force a recalculation of the rates.
+ *
+ * This implements two clock providers, one 'bitselect' that
+ * handles the switch between both parents, and another 'dualgate'
+ * that knows which gate to poke at, depending on the parent's bit position.
+ */
+struct rzn1_clk_bitsel {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ u16 selector; /* selector register + bit */
+};
+
+#define to_clk_bitselect(_hw) container_of(_hw, struct rzn1_clk_bitsel, hw)
+
+static u8 rzn1_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct rzn1_clk_bitsel *set = to_clk_bitselect(hw);
+
+ return clk_rdesc_get(set->clocks, set->selector);
+}
+
+static int rzn1_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct rzn1_clk_bitsel *set = to_clk_bitselect(hw);
+
+ /* a single bit in the register selects one of two parent clocks */
+ clk_rdesc_set(set->clocks, set->selector, !!index);
+
+ return 0;
+}
+
+static const struct clk_ops clk_bitselect_ops = {
+ .get_parent = rzn1_clk_mux_get_parent,
+ .set_parent = rzn1_clk_mux_set_parent,
+};
+
+static struct clk *rzn1_register_bitsel(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc)
+{
+ struct clk *clk;
+ struct rzn1_clk_bitsel *g;
+ struct clk_init_data init;
+ const char *names[2];
+
+ /* allocate the gate */
+ g = kzalloc(sizeof(struct rzn1_clk_bitsel), GFP_KERNEL);
+ if (!g)
+ return NULL;
+
+ names[0] = parent_name;
+ names[1] = "clk_pll_usb";
+
+ init.name = desc->name;
+ init.ops = &clk_bitselect_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = names;
+ init.num_parents = 2;
+
+ g->clocks = clocks;
+ g->index = desc->index;
+ g->selector = desc->dual.sel;
+ g->hw.init = &init;
+
+ clk = clk_register(NULL, &g->hw);
+ if (IS_ERR(clk)) {
+ kfree(g);
+ return NULL;
+ }
+ return clk;
+}
+
+struct rzn1_clk_dualgate {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ u16 selector; /* selector register + bit */
+ struct rzn1_gate gate[2];
+};
+#define to_clk_dualgate(_hw) container_of(_hw, struct rzn1_clk_dualgate, hw)
+
+static int rzn1_clk_dualgate_setenable(struct rzn1_clk_dualgate *g, int enable)
+{
+ uint8_t sel_bit = clk_rdesc_get(g->clocks, g->selector);
+
+ /* we always turn off the 'other' gate, regardless */
+ rzn1_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
+ rzn1_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
+
+ return 0;
+}
+
+static int rzn1_clk_dualgate_enable(struct clk_hw *hw)
+{
+ struct rzn1_clk_dualgate *gate = to_clk_dualgate(hw);
+
+ rzn1_clk_dualgate_setenable(gate, 1);
+
+ return 0;
+}
+
+static void rzn1_clk_dualgate_disable(struct clk_hw *hw)
+{
+ struct rzn1_clk_dualgate *gate = to_clk_dualgate(hw);
+
+ rzn1_clk_dualgate_setenable(gate, 0);
+}
+
+static int rzn1_clk_dualgate_is_enabled(struct clk_hw *hw)
+{
+ struct rzn1_clk_dualgate *g = to_clk_dualgate(hw);
+ uint8_t sel_bit = clk_rdesc_get(g->clocks, g->selector);
+
+ return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
+}
+
+static const struct clk_ops rzn1_clk_dualgate_ops = {
+ .enable = rzn1_clk_dualgate_enable,
+ .disable = rzn1_clk_dualgate_disable,
+ .is_enabled = rzn1_clk_dualgate_is_enabled,
+};
+
+static struct clk *rzn1_register_dualgate(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc,
+ uint16_t sel)
+{
+ struct rzn1_clk_dualgate *g;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ g = kzalloc(sizeof(struct rzn1_clk_dualgate), GFP_KERNEL);
+ if (!g)
+ return NULL;
+ g->clocks = clocks;
+ g->index = desc->index;
+ g->selector = sel;
+ g->gate[0].gate = desc->dual.g1;
+ g->gate[0].reset = desc->dual.r1;
+ g->gate[1].gate = desc->dual.g2;
+ g->gate[1].reset = desc->dual.r2;
+
+ init.name = desc->name;
+ init.ops = &rzn1_clk_dualgate_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ g->hw.init = &init;
+
+ clk = clk_register(NULL, &g->hw);
+ if (IS_ERR(clk)) {
+ kfree(g);
+ return NULL;
+ }
+ return clk;
+}
+
+static void __init rzn1_clocks_init(struct device_node *np)
+{
+ struct rzn1_priv *clocks;
+ struct clk **clks;
+ unsigned int i;
+ uint16_t uart_group_sel[2];
+
+ clocks = kzalloc(sizeof(*clocks), GFP_KERNEL);
+ clks = kzalloc(RZN1_CLOCK_COUNT * sizeof(struct clk *), GFP_KERNEL);
+ if (clocks == NULL || clks == NULL) {
+ /* We're leaking memory on purpose, there's no point in cleaning
+ * up as the system won't boot anyway.
+ */
+ return;
+ }
+ spin_lock_init(&clocks->lock);
+
+ clocks->data.clks = clks;
+ clocks->data.clk_num = RZN1_CLOCK_COUNT;
+
+ clocks->reg = of_iomap(np, 0);
+ if (WARN_ON(clocks->reg == NULL))
+ return;
+ for (i = 0; i < ARRAY_SIZE(rzn1_clocks); ++i) {
+ const struct rzn1_clkdesc *d = &rzn1_clocks[i];
+ const char *parent_name = d->source ?
+ __clk_get_name(clocks->data.clks[d->source - 1]) : NULL;
+ struct clk *clk = NULL;
+
+ switch (d->type) {
+ case K_FC:
+ clk = clk_register_fixed_rate(NULL, d->name,
+ parent_name, 0, d->frequency);
+ break;
+ case K_FFC:
+ clk = clk_register_fixed_factor(NULL, d->name,
+ parent_name, 0, 1, d->div);
+ break;
+ case K_GATE:
+ clk = rzn1_register_gate(clocks, parent_name, d);
+ break;
+ case K_DIV:
+ clk = rzn1_register_divider(clocks, parent_name, d);
+ break;
+ case K_BITSEL:
+ /* keep that selector register around */
+ uart_group_sel[d->dual.group] = d->dual.sel;
+ clk = rzn1_register_bitsel(clocks, parent_name, d);
+ break;
+ case K_DUALGATE:
+ clk = rzn1_register_dualgate(clocks, parent_name, d,
+ uart_group_sel[d->dual.group]);
+ break;
+ }
+ clocks->data.clks[d->index] = clk;
+ }
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
+}
+CLK_OF_DECLARE(rzn1_clks, "renesas,rzn1-clocks",
+ rzn1_clocks_init);
--
2.7.4
On Tue, May 22, 2018 at 11:01:22AM +0100, Michel Pollet wrote:
> This adds the constants necessary to use the renesas,rzn1-clocks driver.
>
> Signed-off-by: Michel Pollet <[email protected]>
> ---
> include/dt-bindings/clock/rzn1-clocks.h | 187 ++++++++++++++++++++++++++++++++
> 1 file changed, 187 insertions(+)
> create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
Reviewed-by: Rob Herring <[email protected]>
On Tue, May 22, 2018 at 11:01:23AM +0100, Michel Pollet wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> to provide the SoC clock infrastructure for Linux.
>
> This documents the driver bindings.
>
> Signed-off-by: Michel Pollet <[email protected]>
> ---
> .../bindings/clock/renesas,rzn1-clocks.txt | 44 ++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> new file mode 100644
> index 0000000..0c41137
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> @@ -0,0 +1,44 @@
> +* Renesas RZ/N1 Clock Driver
> +
> +This driver provides the clock infrastructure used by all the other drivers.
Bindings document h/w not drivers.
> +
> +One of the 'special' feature of this infrastructure is that Linux doesn't
Bindings are not just for Linux.
> +necessary 'own' all the clocks on the SoC, some other OS runs on
> +the Cortex-M3 core and that OS can access and claim it's own clocks.
How is this relevant to the binding?
> +
> +Required Properties:
> +
> + - compatible: Must be
> + - "renesas,r9a06g032-clocks" for the RZ/N1D
> + and "renesas,rzn1-clocks" as a fallback.
Is "clocks" how the chip reference manual refers to this block?
> + - reg: Base address and length of the memory resource used by the driver
> + - #clock-cells: Must be 1
> +
> +Examples
> +--------
> +
> + - Clock driver device node:
> +
> + clock: clocks@4000c000 {
clock-controller@...
> + compatible = "renesas,r9a06g032-clocks",
> + "renesas,rzn1-clocks";
> + reg = <0x4000c000 0x1000>;
> + status = "okay";
Don't show status in examples. (Plus, I doubt you ever want to have this
disabled, so you don't need the property in your dts files either).
> + #clock-cells = <1>;
> + };
> +
> +
> + - Other drivers can use the clocks as in:
s/drivers/nodes/
> +
> + uart0: serial@40060000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x40060000 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&clock RZN1_CLK_UART0>;
> + clock-names = "baudclk";
> + };
> + Note the use of RZN1_CLK_UART0 -- these constants are declared in
> + the rzn1-clocks.h header file. These are not hardware based constants
> + and are Linux specific.
No, they are not Linux specific. They are part of the DT ABI.
While it is not a requirement to base them on some h/w numbering, it is
preferred if you can. That usually only works if you can base them on
bit positions or register offsets.
Rob
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
<[email protected]> wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> to provide the SoC clock infrastructure for Linux.
>
> This documents the driver bindings.
>
> Signed-off-by: Michel Pollet <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> @@ -0,0 +1,44 @@
> +* Renesas RZ/N1 Clock Driver
> +
> +This driver provides the clock infrastructure used by all the other drivers.
> +
> +One of the 'special' feature of this infrastructure is that Linux doesn't
> +necessary 'own' all the clocks on the SoC, some other OS runs on
> +the Cortex-M3 core and that OS can access and claim it's own clocks.
> +
> +Required Properties:
> +
> + - compatible: Must be
> + - "renesas,r9a06g032-clocks" for the RZ/N1D
> + and "renesas,rzn1-clocks" as a fallback.
Why the fallback? I doubt all existing (and future) RZ/N1D SoCs provide the
exact same clock hierarchy.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
<[email protected]> wrote:
> This adds the constants necessary to use the renesas,rzn1-clocks driver.
>
> Signed-off-by: Michel Pollet <[email protected]>
Thanks for your patch!
> ---
> include/dt-bindings/clock/rzn1-clocks.h | 187 ++++++++++++++++++++++++++++++++
> 1 file changed, 187 insertions(+)
> create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
>
> diff --git a/include/dt-bindings/clock/rzn1-clocks.h b/include/dt-bindings/clock/rzn1-clocks.h
> new file mode 100644
> index 0000000..8a73db2
> --- /dev/null
> +++ b/include/dt-bindings/clock/rzn1-clocks.h
Given this is part of the DT ABI, and there exist multiple different RZ/N1
SoCs (and there are probably planned more), I wouldn't call this header
file "rzn1-clocks.h", but e.g. "r9a06g032-clocks.h".
> @@ -0,0 +1,187 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * RZ/N1 clock IDs
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + * Michel Pollet <[email protected]>, <[email protected]>
> + * Derived from zx-reboot.c
> + */
> +
> +#ifndef __DT_BINDINGS_RZN1_CLOCK_H__
> +#define __DT_BINDINGS_RZN1_CLOCK_H__
> +
> +#define RZN1_CLKOUT 0
Similar for the RZN1 prefix.
I'll look at the actual list of clocks later...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, 22 May 2018 at 19:44, Geert Uytterhoeven <[email protected]>
wrote:
> Hi Michel,
> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> <[email protected]> wrote:
> > This adds the constants necessary to use the renesas,rzn1-clocks driver.
> >
> > Signed-off-by: Michel Pollet <[email protected]>
> Thanks for your patch!
> > ---
> > include/dt-bindings/clock/rzn1-clocks.h | 187
++++++++++++++++++++++++++++++++
> > 1 file changed, 187 insertions(+)
> > create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
> >
> > diff --git a/include/dt-bindings/clock/rzn1-clocks.h
b/include/dt-bindings/clock/rzn1-clocks.h
> > new file mode 100644
> > index 0000000..8a73db2
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/rzn1-clocks.h
> Given this is part of the DT ABI, and there exist multiple different RZ/N1
> SoCs (and there are probably planned more), I wouldn't call this header
> file "rzn1-clocks.h", but e.g. "r9a06g032-clocks.h".
Actually, no, there already are two r906g03X devices that will work
perfectly fine with this driver. We had that discussion before, and you
insist and me removing mentions of the rzn1 everywhere, however, this
applies to *two* devices already, and I'm supposed to upstream support for
them. I can't rename r9g06g032 because it is *inexact* that's why it's
called rzn1. So unless you let me call it r9a06g0xx-clocks.h (which i know
you won't as per multiple previous discussions) this can't be called
r9a06g032 because it won't be fit for my purpose when I try to bring back
the RZ/N1S into the picture. There are minor difference to clocking,
I don't know if Renesas plans to release any more rzn1's in this series,
but my little finger tells me this isn't the case. But regardless of what
we plan, Marketing will screw it up.
Cheers,
Michel
> > @@ -0,0 +1,187 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * RZ/N1 clock IDs
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Europe Limited
> > + *
> > + * Michel Pollet <[email protected]>, <[email protected]>
> > + * Derived from zx-reboot.c
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RZN1_CLOCK_H__
> > +#define __DT_BINDINGS_RZN1_CLOCK_H__
> > +
> > +#define RZN1_CLKOUT 0
> Similar for the RZN1 prefix.
> I'll look at the actual list of clocks later...
> Gr{oetje,eeting}s,
> Geert
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
[email protected]
> In personal conversations with technical people, I call myself a hacker.
But
> when I'm talking to journalists I just say "programmer" or something like
that.
> -- Linus Torvalds
Hi Rob,
On Tue, 22 May 2018 at 17:09, Rob Herring <[email protected]> wrote:
> On Tue, May 22, 2018 at 11:01:23AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> > to provide the SoC clock infrastructure for Linux.
> >
> > This documents the driver bindings.
> >
> > Signed-off-by: Michel Pollet <[email protected]>
> > ---
> > .../bindings/clock/renesas,rzn1-clocks.txt | 44
++++++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> > create mode 100644
Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> >
> > diff --git
a/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> > new file mode 100644
> > index 0000000..0c41137
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> > @@ -0,0 +1,44 @@
> > +* Renesas RZ/N1 Clock Driver
> > +
> > +This driver provides the clock infrastructure used by all the other
drivers.
> Bindings document h/w not drivers.
> > +
> > +One of the 'special' feature of this infrastructure is that Linux
doesn't
> Bindings are not just for Linux.
> > +necessary 'own' all the clocks on the SoC, some other OS runs on
> > +the Cortex-M3 core and that OS can access and claim it's own clocks.
> How is this relevant to the binding?
Well you just said it, if the binding is not just for linux, it's probably
a good idea to mention it somewhere since I can promise you it's *not*
documented in the hardware manual. Whatever this binding is for, it's
relevant to point out it is different from the other clock drivers in the
same directory... ?
> > +
> > +Required Properties:
> > +
> > + - compatible: Must be
> > + - "renesas,r9a06g032-clocks" for the RZ/N1D
> > + and "renesas,rzn1-clocks" as a fallback.
> Is "clocks" how the chip reference manual refers to this block?
No, the block is called 'sysctrl' and has tons of other stuff in there.
I've tried multiple times to get a 'sysctrl' driver in the previous
versions of the patch, in various shape or form, and I can't because I'd be
supposed to 'document' binding for stuff that has no code, no purpose, no
testing, and have all wildly different topics. So, after some more
lengthily discussion with Geert, we've decided to make the 'primary'
feature of that block (clocks) as a driver, and see from there onward.
Thanks for all the other comments, all taken onboard for next version!
Michel
> > + - reg: Base address and length of the memory resource used by the
driver
> > + - #clock-cells: Must be 1
> > +
> > +Examples
> > +--------
> > +
> > + - Clock driver device node:
> > +
> > + clock: clocks@4000c000 {
> clock-controller@...
> > + compatible = "renesas,r9a06g032-clocks",
> > + "renesas,rzn1-clocks";
> > + reg = <0x4000c000 0x1000>;
> > + status = "okay";
> Don't show status in examples. (Plus, I doubt you ever want to have this
> disabled, so you don't need the property in your dts files either).
> > + #clock-cells = <1>;
> > + };
> > +
> > +
> > + - Other drivers can use the clocks as in:
> s/drivers/nodes/
> > +
> > + uart0: serial@40060000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x40060000 0x400>;
> > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&clock RZN1_CLK_UART0>;
> > + clock-names = "baudclk";
> > + };
> > + Note the use of RZN1_CLK_UART0 -- these constants are declared in
> > + the rzn1-clocks.h header file. These are not hardware based
constants
> > + and are Linux specific.
> No, they are not Linux specific. They are part of the DT ABI.
> While it is not a requirement to base them on some h/w numbering, it is
> preferred if you can. That usually only works if you can base them on
> bit positions or register offsets.
> Rob
Hi Michel,
On Wed, May 23, 2018 at 8:44 AM, M P <[email protected]> wrote:
> On Tue, 22 May 2018 at 19:44, Geert Uytterhoeven <[email protected]>
> wrote:
>> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
>> <[email protected]> wrote:
>> > This adds the constants necessary to use the renesas,rzn1-clocks driver.
>> >
>> > Signed-off-by: Michel Pollet <[email protected]>
>> > --- /dev/null
>> > +++ b/include/dt-bindings/clock/rzn1-clocks.h
>
>> Given this is part of the DT ABI, and there exist multiple different RZ/N1
>> SoCs (and there are probably planned more), I wouldn't call this header
>> file "rzn1-clocks.h", but e.g. "r9a06g032-clocks.h".
>
> Actually, no, there already are two r906g03X devices that will work
> perfectly fine with this driver. We had that discussion before, and you
> insist and me removing mentions of the rzn1 everywhere, however, this
> applies to *two* devices already, and I'm supposed to upstream support for
> them. I can't rename r9g06g032 because it is *inexact* that's why it's
My worry is not that there are two r906g03X devices that will work fine
with this driver, but that there will be other "rzn1" devices that will not
work with these bindings (the header file is part of the bindings).
Besides, RZ/N1D and RZ/N1S (Which apparently differ in packaging only?
Oh no, RZ/N1D (the larger package) has less QSPI channels than RZ/N1S
(the smaller package)), there's also (at least) RZ/N1L.
> called rzn1. So unless you let me call it r9a06g0xx-clocks.h (which i know
> you won't as per multiple previous discussions) this can't be called
> r9a06g032 because it won't be fit for my purpose when I try to bring back
> the RZ/N1S into the picture.
You can add r9a06g033-clocks.h when adding support for RZ/N1S.
> There are minor difference to clocking,
Aha?
> I don't know if Renesas plans to release any more rzn1's in this series,
> but my little finger tells me this isn't the case. But regardless of what
We thought the same thing when the first RZ member (RZ/A1H) showed up.
Did we know this was not going to be the first SoC of a new RZ family, but
the first SoC of the first subfamily (RZ/A) of the RZ family... And the
various subfamilies bear not much similarity.
> we plan, Marketing will screw it up.
Correct. And to mitigate that, we have no other choice than to use the real
part numbers to differentiate. Once bitten, twice shy.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Morning Geert,
On Wed, 23 May 2018 at 08:26, Geert Uytterhoeven <[email protected]>
wrote:
> Hi Michel,
> On Wed, May 23, 2018 at 8:44 AM, M P <[email protected]> wrote:
> > On Tue, 22 May 2018 at 19:44, Geert Uytterhoeven <[email protected]>
> > wrote:
> >> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> >> <[email protected]> wrote:
> >> > This adds the constants necessary to use the renesas,rzn1-clocks
driver.
> >> >
> >> > Signed-off-by: Michel Pollet <[email protected]>
> >> > --- /dev/null
> >> > +++ b/include/dt-bindings/clock/rzn1-clocks.h
> >
> >> Given this is part of the DT ABI, and there exist multiple different
RZ/N1
> >> SoCs (and there are probably planned more), I wouldn't call this header
> >> file "rzn1-clocks.h", but e.g. "r9a06g032-clocks.h".
> >
> > Actually, no, there already are two r906g03X devices that will work
> > perfectly fine with this driver. We had that discussion before, and you
> > insist and me removing mentions of the rzn1 everywhere, however, this
> > applies to *two* devices already, and I'm supposed to upstream support
for
> > them. I can't rename r9g06g032 because it is *inexact* that's why it's
> My worry is not that there are two r906g03X devices that will work fine
> with this driver, but that there will be other "rzn1" devices that will
not
> work with these bindings (the header file is part of the bindings).
> Besides, RZ/N1D and RZ/N1S (Which apparently differ in packaging only?
> Oh no, RZ/N1D (the larger package) has less QSPI channels than RZ/N1S
> (the smaller package)), there's also (at least) RZ/N1L.
> > called rzn1. So unless you let me call it r9a06g0xx-clocks.h (which i
know
> > you won't as per multiple previous discussions) this can't be called
> > r9a06g032 because it won't be fit for my purpose when I try to bring
back
> > the RZ/N1S into the picture.
> You can add r9a06g033-clocks.h when adding support for RZ/N1S.
So it is now acceptable to duplicate a huge amount of code, and constants
when in fact there differences are so minor they would require minimal
amount of code to take care of them? That just flies straight against my
30+ years of programming -- We're going to have twice the *identical* code,
twice the header, and completely incompatible device tree files -- I mean,
*right now* our rzn1.dtsi works *as is* on the 1D and 1S, we've got ONE
file to maintain, and you can switch your CPU board from 1D to 1S and your
'board file' can stay the same.
Wasn't it the idea of that stuff in the first place? Isn't it in the
customer/engineer interest to be able to cross grade from one
manufacturer's device *in the same series* to another without having to
duplicate his whole board file?
> > There are minor difference to clocking,
> Aha?
Sure, 1S doesn't' have DDR, 1D doesn't have the second QSPI. That's about
it (I lie, theres a few other bits I'm sure). It's not like it won't even
*work* or anything, the registers are there, the bit positions are there,
all is the same, I'm *sure* that's what the compatible="" thing were
supposed to be used for, isn't it? Heck, I'm pretty sure there's a register
in sysctrl, that tells me that anyway, so I wouldn't even have to have a
special compatible= -- I didn't do it since the driver is already so big.
> > I don't know if Renesas plans to release any more rzn1's in this series,
> > but my little finger tells me this isn't the case. But regardless of
what
> We thought the same thing when the first RZ member (RZ/A1H) showed up.
> Did we know this was not going to be the first SoC of a new RZ family, but
> the first SoC of the first subfamily (RZ/A) of the RZ family... And the
> various subfamilies bear not much similarity.
> > we plan, Marketing will screw it up.
> Correct. And to mitigate that, we have no other choice than to use the
real
> part numbers to differentiate. Once bitten, twice shy.
It's not mitigation from where I stand -- it's a gigantic kludge; To handle
one exception, you throw away the baby with the bathwater. From where I
sit, it's like having to a different screwdriver for the screws on the left
of a panel vs the right of the panel.
Sorry to come out as pretty miffed -- I've just spent weeks polishing up a
driver to make it more or less similar to what they were 10 years ago (whoo
look a platform file with a big table in it!), after throwing away all the
work I had done to make it all device-tree based and make the code as
agnostic as we could -- and now it turns out we need to make it even worse
by throwing away the fact it actually *does* work on two SoC -- and that
just because... because what, again?
What about *making up names* -- The 'family names' can/will change -- the
part numbers are *too limited in scope* -- why not just make up names? does
it matter as long as it's close to reality and are documented? I dunno,
"rzn1_18" or "rzn1_mk1" and so we have a way out when they release a new
one next year? It seems to be working fine for cars "I got a 2018's
<Manufacturer> <series>"...
Cheers,
Michel
> Gr{oetje,eeting}s,
> Geert
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
[email protected]
> In personal conversations with technical people, I call myself a hacker.
But
> when I'm talking to journalists I just say "programmer" or something like
that.
> -- Linus Torvalds
On Tue, May 22, 2018 at 11:01:21AM +0100, Michel Pollet wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
This looks fine but I will wait to see if there are other reviews before
applying.
Reviewed-by: Simon Horman <[email protected]>
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
<[email protected]> wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, May 22, 2018 at 11:01:24AM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
>
> Signed-off-by: Michel Pollet <[email protected]>
I am marking this and the following patch as deferred
pending acceptance of the bindings it uses.
> ---
> arch/arm/boot/dts/r9a06g032.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
> create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
>
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> new file mode 100644
> index 0000000..c7764c7
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/rzn1-clock.h>
> +
> +/ {
> + compatible = "renesas,r9a06g032", "renesas,rzn1";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&clock RZN1_DIV_CA7>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <1>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + clock: clocks@4000c000 {
> + compatible = "renesas,r9a06g032-clocks",
> + "renesas,rzn1-clocks";
> + reg = <0x4000c000 0x1000>;
> + status = "okay";
> + #clock-cells = <1>;
> + };
> +
> + uart0: serial@40060000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x40060000 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&clock RZN1_CLK_UART0>;
> + clock-names = "baudclk";
> + status = "disabled";
> + };
> +
> + gic: gic@44101000 {
> + compatible = "arm,cortex-a7-gic", "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x44101000 0x1000>, /* Distributer */
> + <0x44102000 0x2000>, /* CPU interface */
> + <0x44104000 0x2000>, /* Virt interface control */
> + <0x44106000 0x2000>; /* Virt CPU interface */
> + interrupts =
> + <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,cortex-a7-timer",
> + "arm,armv7-timer";
> + interrupt-parent = <&gic>;
> + arm,cpu-registers-not-fw-configured;
> + always-on;
> + interrupts =
> + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +};
> --
> 2.7.4
>
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
<[email protected]> wrote:
> This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
>
> Signed-off-by: Michel Pollet <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/rzn1-clock.h>
> +
> +/ {
> + compatible = "renesas,r9a06g032", "renesas,rzn1";
Please drop the "renesas,rzn1".
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&clock RZN1_DIV_CA7>;
I think the clocks property should be moved to the individual CPU nodes.
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <1>;
> + };
> + };
The rest looks OK to me (pending acceptance of the clock bindings).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Michel,
On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
<[email protected]> wrote:
> This adds a base device tree file for the RZN1-DB board, with only the
> basic support allowing the system to boot to a prompt. Only one UART is
> used, with only a single CPU running.
>
> Signed-off-by: Michel Pollet <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the RZN1D-DB Board
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "r9a06g032.dtsi"
> +
> +/ {
> + model = "RZN1D-DB Board";
> + compatible = "renesas,rzn1d400-db",
> + "renesas,r9a06g032", "renesas,rzn1";
Please drop the "renesas,rzn1".
With the above fixed:
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, May 23, 2018 at 11:03:56AM +0200, Geert Uytterhoeven wrote:
> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> <[email protected]> wrote:
> > This documents the RZ/N1 bindings for the RZN1D-DB board.
> >
> > Signed-off-by: Michel Pollet <[email protected]>
> > Reviewed-by: Rob Herring <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
Thanks, applied.
Hi Geert,
On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven <[email protected]>
wrote:
> Hi Michel,
> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> <[email protected]> wrote:
> > This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
> > bone support.
> >
> > This currently only handles generic parts (gic, architected timer)
> > and a UART.
> > For simplicity sake, this also relies on the bootloader to set the
> > pinctrl and clocks.
> >
> > Signed-off-by: Michel Pollet <[email protected]>
> Thanks for your patch!
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clocks = <&clock RZN1_DIV_CA7>;
> I think the clocks property should be moved to the individual CPU nodes.
Ah, I had a look around, and I found some instances that are in the cpu
sub-node, and others that are not -- it seems that having it in the cpu
sub-node would implies it's core specific... here if that clock is changed
both cores would change speed...
Either way, it's not used by the kernel in any way at the moment -- I had
hoped cpufreq or something would claim it, but it's not the case.
Thanks,
Michel
Hi Michel,
On Wed, May 23, 2018 at 11:20 AM, M P <[email protected]> wrote:
> On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven <[email protected]>
> wrote:
>> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
>> <[email protected]> wrote:
>> > + #address-cells = <1>;
>> > + #size-cells = <1>;
>> > +
>> > + cpus {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > + clocks = <&clock RZN1_DIV_CA7>;
>
>> I think the clocks property should be moved to the individual CPU nodes.
>
> Ah, I had a look around, and I found some instances that are in the cpu
> sub-node, and others that are not -- it seems that having it in the cpu
> sub-node would implies it's core specific... here if that clock is changed
> both cores would change speed...
Assumed the driver code knows to look in the parent node, which I doubt
the cpufreq code does.
> Either way, it's not used by the kernel in any way at the moment -- I had
> hoped cpufreq or something would claim it, but it's not the case.
I guess you have to add your main SoC compatible value to the whitelist
in drivers/cpufreq/cpufreq-dt-platdev.c first.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Wed, 23 May 2018 at 12:18, Geert Uytterhoeven <[email protected]>
wrote:
> Hi Michel,
> On Wed, May 23, 2018 at 11:20 AM, M P <[email protected]> wrote:
> > On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven <[email protected]>
> > wrote:
> >> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
> >> <[email protected]> wrote:
> >> > + #address-cells = <1>;
> >> > + #size-cells = <1>;
> >> > +
> >> > + cpus {
> >> > + #address-cells = <1>;
> >> > + #size-cells = <0>;
> >> > + clocks = <&clock RZN1_DIV_CA7>;
> >
> >> I think the clocks property should be moved to the individual CPU
nodes.
> >
> > Ah, I had a look around, and I found some instances that are in the cpu
> > sub-node, and others that are not -- it seems that having it in the cpu
> > sub-node would implies it's core specific... here if that clock is
changed
> > both cores would change speed...
> Assumed the driver code knows to look in the parent node, which I doubt
> the cpufreq code does.
> > Either way, it's not used by the kernel in any way at the moment -- I
had
> > hoped cpufreq or something would claim it, but it's not the case.
> I guess you have to add your main SoC compatible value to the whitelist
> in drivers/cpufreq/cpufreq-dt-platdev.c first.
Most excellent tip here -- I'll add a further patch to enable this, after
this series eventually gets merged...
Cheers,
Michel
On Wed, May 23, 2018 at 1:52 AM, M P <[email protected]> wrote:
> Hi Rob,
>
> On Tue, 22 May 2018 at 17:09, Rob Herring <[email protected]> wrote:
>
>> On Tue, May 22, 2018 at 11:01:23AM +0100, Michel Pollet wrote:
>> > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
>> > to provide the SoC clock infrastructure for Linux.
>> >
>> > This documents the driver bindings.
>> >
>> > Signed-off-by: Michel Pollet <[email protected]>
>> > ---
>> > .../bindings/clock/renesas,rzn1-clocks.txt | 44
> ++++++++++++++++++++++
>> > 1 file changed, 44 insertions(+)
>> > create mode 100644
> Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
>> >
>> > diff --git
> a/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
>> > new file mode 100644
>> > index 0000000..0c41137
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
>> > @@ -0,0 +1,44 @@
>> > +* Renesas RZ/N1 Clock Driver
>> > +
>> > +This driver provides the clock infrastructure used by all the other
> drivers.
>
>> Bindings document h/w not drivers.
>
>> > +
>> > +One of the 'special' feature of this infrastructure is that Linux
> doesn't
>
>> Bindings are not just for Linux.
>
>> > +necessary 'own' all the clocks on the SoC, some other OS runs on
>> > +the Cortex-M3 core and that OS can access and claim it's own clocks.
>
>> How is this relevant to the binding?
>
> Well you just said it, if the binding is not just for linux, it's probably
> a good idea to mention it somewhere since I can promise you it's *not*
> documented in the hardware manual. Whatever this binding is for, it's
> relevant to point out it is different from the other clock drivers in the
> same directory... ?
That's not an uncommon issue (sometimes it's secure world that owns
the clocks, not even a different processor). I'm just not sure what I
do with this information. It doesn't tell me which clocks are owned by
the M3 or not.
>> > +
>> > +Required Properties:
>> > +
>> > + - compatible: Must be
>> > + - "renesas,r9a06g032-clocks" for the RZ/N1D
>> > + and "renesas,rzn1-clocks" as a fallback.
>
>> Is "clocks" how the chip reference manual refers to this block?
>
> No, the block is called 'sysctrl' and has tons of other stuff in there.
> I've tried multiple times to get a 'sysctrl' driver in the previous
> versions of the patch, in various shape or form, and I can't because I'd be
> supposed to 'document' binding for stuff that has no code, no purpose, no
> testing, and have all wildly different topics. So, after some more
> lengthily discussion with Geert, we've decided to make the 'primary'
> feature of that block (clocks) as a driver, and see from there onward.
If you are referring to Geert's reply on v4, then this is not how I
interpreted it. I understood it as make the clock driver bind to the
sysctrl node and the clock driver can register other functions like
reset. Then later if you need multiple drivers, you can make an MFD
driver that binds to the sysctrl node and creates child devices to
bind sub-drivers (like clocks) to. But the DT doesn't change in the
process wrt clocks.
You don't have to have a driver for everything, but the binding should
be as complete as possible and done in an extendable way. The way you
have done it now is not. I can already see that at some point you will
want to break things and do something like this:
{
compatible = "renesas,r9a06g032-sysctrl";
...
{
compatible = "renesas,r9a06g032-clocks";
...
};
};
Which is likely wrong because there's no need to have a child node
like that. The parent node can be the clock provider (and any other
provider). There are cases when child nodes do make sense, but we need
a more complete binding to make that decision. Evolving it one feature
at a time doesn't work.
Rob
Hi Michel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20180517]
[also build test ERROR on v4.17-rc6]
[cannot apply to robh/for-next renesas-drivers/clk-renesas renesas/devel v4.17-rc6 v4.17-rc5 v4.17-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Michel-Pollet/arm-Base-support-for-Renesas-RZN1D-DB-Board/20180524-052042
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
In file included from arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts:11:0:
>> arch/arm/boot/dts/r9a06g032.dtsi:10:10: fatal error: dt-bindings/clock/rzn1-clock.h: No such file or directory
#include <dt-bindings/clock/rzn1-clock.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +10 arch/arm/boot/dts/r9a06g032.dtsi
f9ea3b52 Michel Pollet 2018-05-22 @10 #include <dt-bindings/clock/rzn1-clock.h>
f9ea3b52 Michel Pollet 2018-05-22 11
:::::: The code at line 10 was first introduced by commit
:::::: f9ea3b52d31219bb2ad77f919417ed61fc779fcb ARM: dts: Renesas RZ/N1 SoC base device tree file
:::::: TO: Michel Pollet <[email protected]>
:::::: CC: 0day robot <[email protected]>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Michel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20180517]
[also build test WARNING on v4.17-rc6]
[cannot apply to robh/for-next renesas-drivers/clk-renesas renesas/devel v4.17-rc6 v4.17-rc5 v4.17-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Michel-Pollet/arm-Base-support-for-Renesas-RZN1D-DB-Board/20180524-052042
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/rzn1-clocks.c:270:22: sparse: cast removes address space of expression
>> drivers/clk/renesas/rzn1-clocks.c:271:29: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:271:29: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:271:29: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:274:25: sparse: incorrect type in argument 2 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:274:25: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:274:25: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:281:22: sparse: cast removes address space of expression
drivers/clk/renesas/rzn1-clocks.c:282:29: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:282:29: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:282:29: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:430:22: sparse: cast removes address space of expression
drivers/clk/renesas/rzn1-clocks.c:431:30: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:431:30: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:431:30: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:516:22: sparse: cast removes address space of expression
drivers/clk/renesas/rzn1-clocks.c:528:38: sparse: incorrect type in argument 2 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:528:38: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:528:38: got unsigned int [usertype] *reg
vim +270 drivers/clk/renesas/rzn1-clocks.c
264
265 /* register/bit pairs are encoded as an uint16_t */
266 static void clk_rdesc_set(
267 struct rzn1_priv *clocks,
268 uint16_t one, unsigned int on)
269 {
> 270 u32 *reg = ((u32 *)clocks->reg) + (one >> 5);
> 271 u32 val = clk_readl(reg);
272
273 val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
274 clk_writel(val, reg);
275 }
276
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Michel,
On Wed, May 23, 2018 at 10:17 AM, M P <[email protected]> wrote:
> On Wed, 23 May 2018 at 08:26, Geert Uytterhoeven <[email protected]>
> wrote:
>> On Wed, May 23, 2018 at 8:44 AM, M P <[email protected]> wrote:
>> > On Tue, 22 May 2018 at 19:44, Geert Uytterhoeven <[email protected]>
>> > wrote:
>> >> On Tue, May 22, 2018 at 12:01 PM, Michel Pollet
>> >> <[email protected]> wrote:
>> >> > --- /dev/null
>> >> > +++ b/include/dt-bindings/clock/rzn1-clocks.h
>> >
>> >> Given this is part of the DT ABI, and there exist multiple different
> RZ/N1
>> >> SoCs (and there are probably planned more), I wouldn't call this header
>> >> file "rzn1-clocks.h", but e.g. "r9a06g032-clocks.h".
>> >
>> > Actually, no, there already are two r906g03X devices that will work
>> > perfectly fine with this driver. We had that discussion before, and you
>> > insist and me removing mentions of the rzn1 everywhere, however, this
>> > applies to *two* devices already, and I'm supposed to upstream support
> for
>> > them. I can't rename r9g06g032 because it is *inexact* that's why it's
>
>> My worry is not that there are two r906g03X devices that will work fine
>> with this driver, but that there will be other "rzn1" devices that will
> not
>> work with these bindings (the header file is part of the bindings).
>> Besides, RZ/N1D and RZ/N1S (Which apparently differ in packaging only?
>> Oh no, RZ/N1D (the larger package) has less QSPI channels than RZ/N1S
>> (the smaller package)), there's also (at least) RZ/N1L.
>
>> > called rzn1. So unless you let me call it r9a06g0xx-clocks.h (which i
> know
>> > you won't as per multiple previous discussions) this can't be called
>> > r9a06g032 because it won't be fit for my purpose when I try to bring
> back
>> > the RZ/N1S into the picture.
>
>> You can add r9a06g033-clocks.h when adding support for RZ/N1S.
>
> So it is now acceptable to duplicate a huge amount of code, and constants
> when in fact there differences are so minor they would require minimal
> amount of code to take care of them? That just flies straight against my
> 30+ years of programming -- We're going to have twice the *identical* code,
> twice the header, and completely incompatible device tree files -- I mean,
> *right now* our rzn1.dtsi works *as is* on the 1D and 1S, we've got ONE
> file to maintain, and you can switch your CPU board from 1D to 1S and your
> 'board file' can stay the same.
>
> Wasn't it the idea of that stuff in the first place? Isn't it in the
> customer/engineer interest to be able to cross grade from one
> manufacturer's device *in the same series* to another without having to
> duplicate his whole board file?
Yes, all of these are desirable.
Now, given the clock definitions for RZ/N1[DSL] are the same (although some
don't exist on some variants), you could keep on using RZN1_CLK_FOO for the
names of the defines, and store them in a common file, included by the
soc-specific file. But please make clear the common file cannot be included
directly, so the filename does not become part of the DT ABI, and you are
shielded from future marketing silliness (e.g. next quarter's RZ/N1X being
totally different).
E.g.:
include/dt-bindings/clock/r9a06g033-clocks.h:
#ifndef __DT_BINDINGS_R9A06G033_CLOCK_H__
#define __DT_BINDINGS_R9A06G033_CLOCK_H__
#include "rzn1-clocks.h"
// ... additions and fixups, if needed
#endif // __DT_BINDINGS_R9A06G033_CLOCK_H__
include/dt-bindings/clock/rzn1-clocks.h:
#ifndef __DT_BINDINGS_RZN1_CLOCK_H__
#define __DT_BINDINGS_RZN1_CLOCK_H__
#ifndef __DT_BINDINGS_R9A06G033_CLOCK_H__
#error Do not include rzn1-clocks.h directly
#endif
#define RZN1_CLK_FOO 0
#define RZN1_CLK_BAR 1
...
#endif // __DT_BINDINGS_RZN1_CLOCK_H__
As for the driver, I think you should make sure the driver instantiates no
clocks that don't exist on the actual SoC it runs on.
BTW, someone asked why I didn't use the same definitions for R-Car M3-W and
R-Car H3 (there were only a few differences), and didn't use common
definitions for all R-Car Gen3 SoCs.
I doubted a long time that we made the right decision, but then V3M and V3H
appeared in later revisions of the datasheet, and D3 and E3 later,
reconfirming our decision.
Even for compatible values for IP cores within the same family: there are
differences, but usually we only discover them after a while.
In theory all the same IP cores in R-Car Gen3 SoCs are the same (except for
obvious differences like clocks and pinctrl), in practice they are not.
So it may sound silly to have SoC-specific compatible values for the gross
of the IP cores, but it would be worse if we got bitten later by not having
them.
BTW, you're too quick reposting your series. I can't finish my reviews in
time ;-)
Please give people a reasonable amount of time to handle them.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On 25 May 2018 10:13 Geert Uytterhoeven wrote:
[snip]
> Now, given the clock definitions for RZ/N1[DSL] are the same (although some
> don't exist on some variants), you could keep on using RZN1_CLK_FOO for
> the names of the defines, and store them in a common file, included by the
> soc-specific file. But please make clear the common file cannot be included
> directly, so the filename does not become part of the DT ABI, and you are
> shielded from future marketing silliness (e.g. next quarter's RZ/N1X being
> totally different).
How does an include filename become part of the DT ABI?
I thought the dtb is the ABI, not the dts. Am I wrong?
Thanks
Phil
Hi Phil,
On Wed, May 30, 2018 at 3:30 PM, Phil Edworthy
<[email protected]> wrote:
> On 25 May 2018 10:13 Geert Uytterhoeven wrote:
> [snip]
>
>> Now, given the clock definitions for RZ/N1[DSL] are the same (although some
>> don't exist on some variants), you could keep on using RZN1_CLK_FOO for
>> the names of the defines, and store them in a common file, included by the
>> soc-specific file. But please make clear the common file cannot be included
>> directly, so the filename does not become part of the DT ABI, and you are
>> shielded from future marketing silliness (e.g. next quarter's RZ/N1X being
>> totally different).
> How does an include filename become part of the DT ABI?
> I thought the dtb is the ABI, not the dts. Am I wrong?
You're right. In se the DT ABI applies to the DTB, not to the DTS.
The definitions inside the include file are part of the DT bindings,
and thus cannot
be changed. Your DTS files get these definitions by including the header file,
so the header filename is also part of the bindings, and thus can't be changed
that easily.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On 30 May 2018 14:37 Geert Uytterhoeven wrote:
> On Wed, May 30, 2018 at 3:30 PM, Phil Edworthy wrote:
> > On 25 May 2018 10:13 Geert Uytterhoeven wrote:
> > [snip]
> >
> >> Now, given the clock definitions for RZ/N1[DSL] are the same
> >> (although some don't exist on some variants), you could keep on using
> >> RZN1_CLK_FOO for the names of the defines, and store them in a
> common
> >> file, included by the soc-specific file. But please make clear the
> >> common file cannot be included directly, so the filename does not
> >> become part of the DT ABI, and you are shielded from future marketing
> >> silliness (e.g. next quarter's RZ/N1X being totally different).
> > How does an include filename become part of the DT ABI?
> > I thought the dtb is the ABI, not the dts. Am I wrong?
>
> You're right. In se the DT ABI applies to the DTB, not to the DTS.
>
> The definitions inside the include file are part of the DT bindings, and thus
> cannot be changed. Your DTS files get these definitions by including the
> header file, so the header filename is also part of the bindings, and thus can't
> be changed that easily.
That seems a bit onerous...
It makes sense that bindings that affect the dtb can only be added to, so that
an old dtb still works. However, I would have thought it's the value of the
constant that is the ABI, not the symbol name used to specify it.
Thanks for you feedback!
Phil