This series is based on the alternatives changes done in my svpbmt series
and thus also depends on Atish's isa-extension parsing series.
It implements using the cache-management instructions from the Zicbom-
extension to handle cache flush, etc actions on platforms needing them.
SoCs using cpu cores from T-Head like the Allwinne D1 implement a
different set of cache instructions. But while they are different,
instructions they provide the same functionality, so a variant can
easly hook into the existing alternatives mechanism on those.
An ongoing discussion is about the currently used pre-coded
instructions. Palmer's current thinking is that we should wait
until the relevant instructions have landed in binutils.
The main Zicbom instructions are in toolchains now and at least
Debian also carries a binutils snapshot with it, but the T-Head
variant still uses pre-coded instructions for now.
The series sits on top of my svpbmt fixup series, which
for example includes the conversion away from function pointers
for the check-functions. And also uses my nops-series.
Hopefully I caught all the review-comments from v3.
changes in v4:
- modify of_dma_is_coherent() also handle coherent system
with maybe noncoherent devices
- move Zicbom to use real instructions
- split off the actual dma-noncoherent code from the Zicbom
extension
- Don't assumes devices are non-coherent, instead default to
coherent and require the non-coherent ones to be marked
- CPUFEATURE_ZICBOM instead of CPUFEATURE_CMO
- fix used cache addresses
- drop some unused headers from dma-noncoherent.c
- move unsigned long cast when calling ALT_CMO_OP
- remove unneeded memset-0
- define ARCH_DMA_MINALIGN
- use flush instead of inval in arch_sync_dma_for_cpu()
- depend on !XIP_KERNEL
- trim some line lengths
- improve Kconfig description
changes in v3:
- rebase onto 5.19-rc1 + svpbmt-fixup-series
- adapt wording for block-size binding
- include asm/cacheflush.h into dma-noncoherent to fix the
no-prototype error clang seems to generate
- use __nops macro for readability
- add some received tags
- add a0 to the clobber list
changes in v2:
- cbom-block-size is hardware-specific and comes from firmware
- update Kconfig name to use the ISA extension name
- select the ALTERNATIVES symbol when enabled
- shorten the line lengths of the errata-assembly
Heiko Stuebner (4):
of: also handle dma-noncoherent in of_dma_is_coherent()
dt-bindings: riscv: document cbom-block-size
riscv: Implement Zicbom-based cache management operations
riscv: implement cache-management errata for T-Head SoCs
.../devicetree/bindings/riscv/cpus.yaml | 5 +
arch/riscv/Kconfig | 31 ++++++
arch/riscv/Kconfig.erratas | 11 +++
arch/riscv/Makefile | 4 +
arch/riscv/errata/thead/errata.c | 15 +++
arch/riscv/include/asm/cache.h | 4 +
arch/riscv/include/asm/cacheflush.h | 6 ++
arch/riscv/include/asm/errata_list.h | 59 +++++++++++-
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 18 ++++
arch/riscv/kernel/setup.c | 2 +
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/dma-noncoherent.c | 96 +++++++++++++++++++
drivers/of/address.c | 16 +++-
15 files changed, 263 insertions(+), 7 deletions(-)
create mode 100644 arch/riscv/mm/dma-noncoherent.c
--
2.35.1
The Zicbom ISA-extension was ratified in november 2021
and introduces instructions for dcache invalidate, clean
and flush operations.
Implement cache management operations based on them.
Of course not all cores will support this, so implement an
alternative-based mechanism that replaces empty instructions
with ones done around Zicbom instructions.
As discussed in previous versions, assume the platform
being coherent by default so that non-coherent devices need
to get marked accordingly by firmware.
Signed-off-by: Heiko Stuebner <[email protected]>
Cc: Christoph Hellwig <[email protected]>
Cc: Atish Patra <[email protected]>
Cc: Guo Ren <[email protected]>
Cc: Anup Patel <[email protected]>
---
arch/riscv/Kconfig | 31 +++++++++
arch/riscv/Makefile | 4 ++
arch/riscv/include/asm/cache.h | 4 ++
arch/riscv/include/asm/cacheflush.h | 6 ++
arch/riscv/include/asm/errata_list.h | 19 +++++-
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 18 ++++++
arch/riscv/kernel/setup.c | 2 +
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/dma-noncoherent.c | 96 ++++++++++++++++++++++++++++
11 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/mm/dma-noncoherent.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 32ffef9f6e5b..f7b2b3a4b7f1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,7 @@ config RISCV
select MODULES_USE_ELF_RELA if MODULES
select MODULE_SECTIONS if MODULES
select OF
+ select OF_DMA_DEFAULT_COHERENT
select OF_EARLY_FLATTREE
select OF_IRQ
select PCI_DOMAINS_GENERIC if PCI
@@ -218,6 +219,14 @@ config PGTABLE_LEVELS
config LOCKDEP_SUPPORT
def_bool y
+config RISCV_DMA_NONCOHERENT
+ bool
+ select ARCH_HAS_DMA_PREP_COHERENT
+ select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
+ select ARCH_HAS_SETUP_DMA_OPS
+ select DMA_DIRECT_REMAP
+
source "arch/riscv/Kconfig.socs"
source "arch/riscv/Kconfig.erratas"
@@ -376,6 +385,28 @@ config RISCV_ISA_SVPBMT
If you don't know what to do here, say Y.
+config CC_HAS_ZICBOM
+ bool
+ default y if 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicbom)
+ default y if 32BIT && $(cc-option,-mabi=lp64 -march=rv32ima_zicbom)
+
+config RISCV_ISA_ZICBOM
+ bool "Zicbom extension support for non-coherent DMA operation"
+ depends on CC_HAS_ZICBOM
+ depends on !XIP_KERNEL
+ select RISCV_DMA_NONCOHERENT
+ select RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the ZICBOM
+ extension (Cache Block Management Operations) and enable its
+ usage.
+
+ The Zicbom extension can be used to handle for example
+ non-coherent DMA support on devices that need it.
+
+ If you don't know what to do here, say Y.
+
config FPU
bool "FPU support"
default y
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 34cf8a598617..fbaabc98b3d2 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
+# Check if the toolchain supports Zicbom extension
+toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom)
+riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom
+
KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
KBUILD_AFLAGS += -march=$(riscv-march-y)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 9b58b104559e..d3036df23ccb 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -11,6 +11,10 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#ifdef CONFIG_RISCV_DMA_NONCOHERENT
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+#endif
+
/*
* RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
* the flat loader aligns it accordingly.
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index 23ff70350992..eb12d014b158 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -42,6 +42,12 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
#endif /* CONFIG_SMP */
+#ifdef CONFIG_RISCV_ISA_ZICBOM
+void riscv_init_cbom_blocksize(void);
+#else
+static inline void riscv_init_cbom_blocksize(void) { }
+#endif
+
/*
* Bits in sys_riscv_flush_icache()'s flags argument.
*/
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 398e351e7002..79d89aeeaa6c 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -20,7 +20,8 @@
#endif
#define CPUFEATURE_SVPBMT 0
-#define CPUFEATURE_NUMBER 1
+#define CPUFEATURE_ZICBOM 1
+#define CPUFEATURE_NUMBER 2
#ifdef __ASSEMBLY__
@@ -87,6 +88,22 @@ asm volatile(ALTERNATIVE( \
#define ALT_THEAD_PMA(_val)
#endif
+#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
+asm volatile(ALTERNATIVE( \
+ __nops(5), \
+ "mv a0, %1\n\t" \
+ "j 2f\n\t" \
+ "3:\n\t" \
+ "cbo." __stringify(_op) " (a0)\n\t" \
+ "add a0, a0, %0\n\t" \
+ "2:\n\t" \
+ "bltu a0, %2, 3b\n\t", 0, \
+ CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \
+ : : "r"(_cachesize), \
+ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
+ "r"((unsigned long)(_start) + (_size)) \
+ : "a0")
+
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4e2486881840..6044e402003d 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -53,6 +53,7 @@ extern unsigned long elf_hwcap;
enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_SVPBMT,
+ RISCV_ISA_EXT_ZICBOM,
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index fba9e9f46a8c..0365557f7122 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node)
static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+ __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
};
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 6a40cb8134bd..c66bf5c33cc3 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -199,6 +199,7 @@ void __init riscv_fill_hwcap(void)
} else {
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+ SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
}
#undef SET_ISA_EXT_MAP
}
@@ -259,6 +260,20 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
return false;
}
+static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
+{
+#ifdef CONFIG_RISCV_ISA_ZICBOM
+ switch (stage) {
+ case RISCV_ALTERNATIVES_EARLY_BOOT:
+ return false;
+ default:
+ return riscv_isa_extension_available(NULL, ZICBOM);
+ }
+#endif
+
+ return false;
+}
+
/*
* Probe presence of individual extensions.
*
@@ -273,6 +288,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
if (cpufeature_probe_svpbmt(stage))
cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
+ if (cpufeature_probe_zicbom(stage))
+ cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
+
return cpu_req_feature;
}
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index f0f36a4a0e9b..95ef6e2bf45c 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -22,6 +22,7 @@
#include <linux/crash_dump.h>
#include <asm/alternative.h>
+#include <asm/cacheflush.h>
#include <asm/cpu_ops.h>
#include <asm/early_ioremap.h>
#include <asm/pgtable.h>
@@ -296,6 +297,7 @@ void __init setup_arch(char **cmdline_p)
#endif
riscv_fill_hwcap();
+ riscv_init_cbom_blocksize();
apply_boot_alternatives();
}
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index ac7a25298a04..d76aabf4b94d 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -30,3 +30,4 @@ endif
endif
obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
+obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
new file mode 100644
index 000000000000..6be6ff2cd5d8
--- /dev/null
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RISC-V specific functions to support DMA for non-coherent devices
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/dma-direct.h>
+#include <linux/dma-map-ops.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <asm/cacheflush.h>
+
+static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
+
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+ enum dma_data_direction dir)
+{
+ void *vaddr = phys_to_virt(paddr);
+
+ switch (dir) {
+ case DMA_TO_DEVICE:
+ ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
+ break;
+ case DMA_FROM_DEVICE:
+ ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
+ break;
+ case DMA_BIDIRECTIONAL:
+ ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+ break;
+ default:
+ break;
+ }
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+ enum dma_data_direction dir)
+{
+ void *vaddr = phys_to_virt(paddr);
+
+ switch (dir) {
+ case DMA_TO_DEVICE:
+ break;
+ case DMA_FROM_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+ break;
+ default:
+ break;
+ }
+}
+
+void arch_dma_prep_coherent(struct page *page, size_t size)
+{
+ void *flush_addr = page_address(page);
+
+ ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
+}
+
+void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+ const struct iommu_ops *iommu, bool coherent)
+{
+ dev->dma_coherent = coherent;
+}
+
+#ifdef CONFIG_RISCV_ISA_ZICBOM
+void riscv_init_cbom_blocksize(void)
+{
+ struct device_node *node;
+ int ret;
+ u32 val;
+
+ for_each_of_cpu_node(node) {
+ int hartid = riscv_of_processor_hartid(node);
+ int cbom_hartid;
+
+ if (hartid < 0)
+ continue;
+
+ /* set block-size for cbom extension if available */
+ ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
+ if (ret)
+ continue;
+
+ if (!riscv_cbom_block_size) {
+ riscv_cbom_block_size = val;
+ cbom_hartid = hartid;
+ } else {
+ if (riscv_cbom_block_size != val)
+ pr_warn("cbom-block-size mismatched between harts %d and %d\n",
+ cbom_hartid, hartid);
+ }
+ }
+}
+#endif
--
2.35.1
The T-Head C906 and C910 implement a scheme for handling
cache operations different from the generic Zicbom extension.
Add an errata for it next to the generic dma coherency ops.
Signed-off-by: Heiko Stuebner <[email protected]>
---
arch/riscv/Kconfig.erratas | 11 +++++++
arch/riscv/errata/thead/errata.c | 15 +++++++++
arch/riscv/include/asm/errata_list.h | 48 +++++++++++++++++++++++++---
3 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
index 457ac72c9b36..3223e533fd87 100644
--- a/arch/riscv/Kconfig.erratas
+++ b/arch/riscv/Kconfig.erratas
@@ -55,4 +55,15 @@ config ERRATA_THEAD_PBMT
If you don't know what to do here, say "Y".
+config ERRATA_THEAD_CMO
+ bool "Apply T-Head cache management errata"
+ depends on ERRATA_THEAD
+ select RISCV_DMA_NONCOHERENT
+ default y
+ help
+ This will apply the cache management errata to handle the
+ non-standard handling on non-coherent operations on T-Head SoCs.
+
+ If you don't know what to do here, say "Y".
+
endmenu
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index b37b6fedd53b..c97e59ae1b79 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -27,6 +27,18 @@ static bool errata_probe_pbmt(unsigned int stage,
return false;
}
+static bool errata_probe_cmo(unsigned int stage,
+ unsigned long arch_id, unsigned long impid)
+{
+ if (arch_id != 0 || impid != 0)
+ return false;
+
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ return false;
+
+ return true;
+}
+
static u32 thead_errata_probe(unsigned int stage,
unsigned long archid, unsigned long impid)
{
@@ -35,6 +47,9 @@ static u32 thead_errata_probe(unsigned int stage,
if (errata_probe_pbmt(stage, archid, impid))
cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
+ if (errata_probe_cmo(stage, archid, impid))
+ cpu_req_errata |= (1U << ERRATA_THEAD_CMO);
+
return cpu_req_errata;
}
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 79d89aeeaa6c..19a771085781 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -16,7 +16,8 @@
#ifdef CONFIG_ERRATA_THEAD
#define ERRATA_THEAD_PBMT 0
-#define ERRATA_THEAD_NUMBER 1
+#define ERRATA_THEAD_CMO 1
+#define ERRATA_THEAD_NUMBER 2
#endif
#define CPUFEATURE_SVPBMT 0
@@ -88,17 +89,54 @@ asm volatile(ALTERNATIVE( \
#define ALT_THEAD_PMA(_val)
#endif
+/*
+ * dcache.ipa rs1 (invalidate, physical address)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000001 01010 rs1 000 00000 0001011
+ * dache.iva rs1 (invalida, virtual address)
+ * 0000001 00110 rs1 000 00000 0001011
+ *
+ * dcache.cpa rs1 (clean, physical address)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000001 01001 rs1 000 00000 0001011
+ * dcache.cva rs1 (clean, virtual address)
+ * 0000001 00100 rs1 000 00000 0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate, physical address)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000001 01011 rs1 000 00000 0001011
+ * dcache.civa rs1 (... virtual address)
+ * 0000001 00111 rs1 000 00000 0001011
+ *
+ * sync.s (make sure all cache operations finished)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000000 11001 00000 000 00000 0001011
+ */
+#define THEAD_inval_A0 ".long 0x0265000b"
+#define THEAD_clean_A0 ".long 0x0245000b"
+#define THEAD_flush_A0 ".long 0x0275000b"
+#define THEAD_SYNC_S ".long 0x0190000b"
+
#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
-asm volatile(ALTERNATIVE( \
- __nops(5), \
+asm volatile(ALTERNATIVE_2( \
+ __nops(6), \
"mv a0, %1\n\t" \
"j 2f\n\t" \
"3:\n\t" \
"cbo." __stringify(_op) " (a0)\n\t" \
"add a0, a0, %0\n\t" \
"2:\n\t" \
- "bltu a0, %2, 3b\n\t", 0, \
- CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \
+ "bltu a0, %2, 3b\n\t" \
+ "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
+ "mv a0, %1\n\t" \
+ "j 2f\n\t" \
+ "3:\n\t" \
+ THEAD_##_op##_A0 "\n\t" \
+ "add a0, a0, %0\n\t" \
+ "2:\n\t" \
+ "bltu a0, %2, 3b\n\t" \
+ THEAD_SYNC_S, THEAD_VENDOR_ID, \
+ ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
: : "r"(_cachesize), \
"r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
"r"((unsigned long)(_start) + (_size)) \
--
2.35.1
The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.
So add the necessary property for the system to know the core's
block-size.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..873dd12f6e89 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
+ riscv,cbom-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicbom cache operations.
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
--
2.35.1
of_dma_is_coherent() currently expects the architecture to be
non-coherent and some devices being coherent getting marked
as such with the dma-coherent devicetree property.
For PowerPC CONFIG_OF_DMA_DEFAULT_COHERENT was added which currently
makes of_dma_is_coherent() always return true but doesn't handle
the case of the architecture being coherent but some devices not.
So modify the function to also check for dma-noncoherent and
set a suitable default return value. If CONFIG_OF_DMA_DEFAULT_COHERENT
is set the value starts with true and finding dma-noncoherent will
set it to false and without CONFIG_OF_DMA_DEFAULT_COHERENT, the
behaviour is reversed.
Signed-off-by: Heiko Stuebner <[email protected]>
---
drivers/of/address.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 94f017d808c4..1c362d09983d 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1045,26 +1045,32 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np)
*
* It returns true if "dma-coherent" property was found
* for this device in the DT, or if DMA is coherent by
- * default for OF devices on the current platform.
+ * default for OF devices on the current platform and no
+ * "dma-noncoherent" property was found for this device.
*/
bool of_dma_is_coherent(struct device_node *np)
{
struct device_node *node;
+ bool ret = false;
if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
- return true;
+ ret = true;
node = of_node_get(np);
while (node) {
if (of_property_read_bool(node, "dma-coherent")) {
- of_node_put(node);
- return true;
+ ret = true;
+ break;
+ }
+ if (of_property_read_bool(node, "dma-noncoherent")) {
+ ret = false;
+ break;
}
node = of_get_next_dma_parent(node);
}
of_node_put(node);
- return false;
+ return ret;
}
EXPORT_SYMBOL_GPL(of_dma_is_coherent);
--
2.35.1
On Sun, Jun 19, 2022 at 10:32:09PM +0200, Heiko Stuebner wrote:
> bool of_dma_is_coherent(struct device_node *np)
> {
> struct device_node *node;
> + bool ret = false;
I'd rename this to coherent or is_coherent.
>
> if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
> - return true;
> + ret = true;
And then do this at initialization time:
bool is_coherent = IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT);
but otherwise this looks good to me.
On Sun, Jun 19, 2022 at 10:32:11PM +0200, Heiko Stuebner wrote:
> +#ifdef CONFIG_RISCV_DMA_NONCOHERENT
> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
> +#endif
This needs to be greater or equal to riscv_cbom_block_size, but the
core code requires a compile time constant here. So we'll need a big
fat comment here, and panic if riscv_cbom_block_size is >
L1_CACHE_BYTES/ARCH_DMA_MINALIGN in the code that queries
riscv_cbom_block_size.
Note that the arm64 folks are looking into making this variable or
killing it off in this current form, so things might be getting better
soon.
> +void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> + enum dma_data_direction dir)
> +{
> + void *vaddr = phys_to_virt(paddr);
> +
> + switch (dir) {
> + case DMA_TO_DEVICE:
> + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> + break;
> + case DMA_FROM_DEVICE:
> + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
> + break;
For this also see:
https://lore.kernel.org/all/20220606152150.GA31568@willie-the-truck/
and
https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
> +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> + const struct iommu_ops *iommu, bool coherent)
> +{
> + dev->dma_coherent = coherent;
> +}
This probably wants a sanity check warn if coherent if false without
any support for cache flushing as that will cause data corruption.
On Sun, Jun 19, 2022 at 1:32 PM Heiko Stuebner <[email protected]> wrote:
>
> of_dma_is_coherent() currently expects the architecture to be
> non-coherent and some devices being coherent getting marked
> as such with the dma-coherent devicetree property.
>
> For PowerPC CONFIG_OF_DMA_DEFAULT_COHERENT was added which currently
> makes of_dma_is_coherent() always return true but doesn't handle
> the case of the architecture being coherent but some devices not.
>
> So modify the function to also check for dma-noncoherent and
> set a suitable default return value. If CONFIG_OF_DMA_DEFAULT_COHERENT
> is set the value starts with true and finding dma-noncoherent will
> set it to false and without CONFIG_OF_DMA_DEFAULT_COHERENT, the
> behaviour is reversed.
>
> Signed-off-by: Heiko Stuebner <[email protected]>
> ---
> drivers/of/address.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index 94f017d808c4..1c362d09983d 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -1045,26 +1045,32 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np)
> *
> * It returns true if "dma-coherent" property was found
> * for this device in the DT, or if DMA is coherent by
> - * default for OF devices on the current platform.
> + * default for OF devices on the current platform and no
> + * "dma-noncoherent" property was found for this device.
"dma-noncoherent" is not a standard DT property. I couldn't find any
references to
it in the kernel as well. If we are introducing a new DT property for
non-coherent devices,
it should be added in DT bindings as well ?
> */
> bool of_dma_is_coherent(struct device_node *np)
> {
> struct device_node *node;
> + bool ret = false;
>
> if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
> - return true;
> + ret = true;
>
> node = of_node_get(np);
>
> while (node) {
> if (of_property_read_bool(node, "dma-coherent")) {
> - of_node_put(node);
> - return true;
> + ret = true;
> + break;
> + }
> + if (of_property_read_bool(node, "dma-noncoherent")) {
> + ret = false;
> + break;
> }
> node = of_get_next_dma_parent(node);
> }
> of_node_put(node);
> - return false;
> + return ret;
> }
> EXPORT_SYMBOL_GPL(of_dma_is_coherent);
>
> --
> 2.35.1
>
--
Regards,
Atish
Hi Atish,
Am Montag, 20. Juni 2022, 18:33:09 CEST schrieb Atish Patra:
> On Sun, Jun 19, 2022 at 1:32 PM Heiko Stuebner <[email protected]> wrote:
> >
> > of_dma_is_coherent() currently expects the architecture to be
> > non-coherent and some devices being coherent getting marked
> > as such with the dma-coherent devicetree property.
> >
> > For PowerPC CONFIG_OF_DMA_DEFAULT_COHERENT was added which currently
> > makes of_dma_is_coherent() always return true but doesn't handle
> > the case of the architecture being coherent but some devices not.
> >
> > So modify the function to also check for dma-noncoherent and
> > set a suitable default return value. If CONFIG_OF_DMA_DEFAULT_COHERENT
> > is set the value starts with true and finding dma-noncoherent will
> > set it to false and without CONFIG_OF_DMA_DEFAULT_COHERENT, the
> > behaviour is reversed.
> >
> > Signed-off-by: Heiko Stuebner <[email protected]>
> > ---
> > drivers/of/address.c | 16 +++++++++++-----
> > 1 file changed, 11 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/of/address.c b/drivers/of/address.c
> > index 94f017d808c4..1c362d09983d 100644
> > --- a/drivers/of/address.c
> > +++ b/drivers/of/address.c
> > @@ -1045,26 +1045,32 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np)
> > *
> > * It returns true if "dma-coherent" property was found
> > * for this device in the DT, or if DMA is coherent by
> > - * default for OF devices on the current platform.
> > + * default for OF devices on the current platform and no
> > + * "dma-noncoherent" property was found for this device.
>
> "dma-noncoherent" is not a standard DT property. I couldn't find any
> references to
> it in the kernel as well. If we are introducing a new DT property for
> non-coherent devices,
> it should be added in DT bindings as well ?
The dma-coherent is part of the core devicetree-spec,
so I sent a patch adding dma-noncoherent [0]
to the devicetree-spec mailing list yesterday as well.
[0] https://www.spinics.net/lists/devicetree-spec/msg01053.html
>
> > */
> > bool of_dma_is_coherent(struct device_node *np)
> > {
> > struct device_node *node;
> > + bool ret = false;
> >
> > if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
> > - return true;
> > + ret = true;
> >
> > node = of_node_get(np);
> >
> > while (node) {
> > if (of_property_read_bool(node, "dma-coherent")) {
> > - of_node_put(node);
> > - return true;
> > + ret = true;
> > + break;
> > + }
> > + if (of_property_read_bool(node, "dma-noncoherent")) {
> > + ret = false;
> > + break;
> > }
> > node = of_get_next_dma_parent(node);
> > }
> > of_node_put(node);
> > - return false;
> > + return ret;
> > }
> > EXPORT_SYMBOL_GPL(of_dma_is_coherent);
> >
> > --
> > 2.35.1
> >
>
>
>
On Mon, Jun 20, 2022 at 11:11 AM Heiko Stuebner <[email protected]> wrote:
>
> Hi Atish,
>
> Am Montag, 20. Juni 2022, 18:33:09 CEST schrieb Atish Patra:
> > On Sun, Jun 19, 2022 at 1:32 PM Heiko Stuebner <[email protected]> wrote:
> > >
> > > of_dma_is_coherent() currently expects the architecture to be
> > > non-coherent and some devices being coherent getting marked
> > > as such with the dma-coherent devicetree property.
> > >
> > > For PowerPC CONFIG_OF_DMA_DEFAULT_COHERENT was added which currently
> > > makes of_dma_is_coherent() always return true but doesn't handle
> > > the case of the architecture being coherent but some devices not.
> > >
> > > So modify the function to also check for dma-noncoherent and
> > > set a suitable default return value. If CONFIG_OF_DMA_DEFAULT_COHERENT
> > > is set the value starts with true and finding dma-noncoherent will
> > > set it to false and without CONFIG_OF_DMA_DEFAULT_COHERENT, the
> > > behaviour is reversed.
> > >
> > > Signed-off-by: Heiko Stuebner <[email protected]>
> > > ---
> > > drivers/of/address.c | 16 +++++++++++-----
> > > 1 file changed, 11 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/of/address.c b/drivers/of/address.c
> > > index 94f017d808c4..1c362d09983d 100644
> > > --- a/drivers/of/address.c
> > > +++ b/drivers/of/address.c
> > > @@ -1045,26 +1045,32 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct device_node *np)
> > > *
> > > * It returns true if "dma-coherent" property was found
> > > * for this device in the DT, or if DMA is coherent by
> > > - * default for OF devices on the current platform.
> > > + * default for OF devices on the current platform and no
> > > + * "dma-noncoherent" property was found for this device.
> >
> > "dma-noncoherent" is not a standard DT property. I couldn't find any
> > references to
> > it in the kernel as well. If we are introducing a new DT property for
> > non-coherent devices,
> > it should be added in DT bindings as well ?
>
> The dma-coherent is part of the core devicetree-spec,
> so I sent a patch adding dma-noncoherent [0]
> to the devicetree-spec mailing list yesterday as well.
>
Ahh. That's great. Thanks!
> [0] https://www.spinics.net/lists/devicetree-spec/msg01053.html
>
>
> >
> > > */
> > > bool of_dma_is_coherent(struct device_node *np)
> > > {
> > > struct device_node *node;
> > > + bool ret = false;
> > >
> > > if (IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT))
> > > - return true;
> > > + ret = true;
> > >
> > > node = of_node_get(np);
> > >
> > > while (node) {
> > > if (of_property_read_bool(node, "dma-coherent")) {
> > > - of_node_put(node);
> > > - return true;
> > > + ret = true;
> > > + break;
> > > + }
> > > + if (of_property_read_bool(node, "dma-noncoherent")) {
> > > + ret = false;
> > > + break;
> > > }
> > > node = of_get_next_dma_parent(node);
> > > }
> > > of_node_put(node);
> > > - return false;
> > > + return ret;
> > > }
> > > EXPORT_SYMBOL_GPL(of_dma_is_coherent);
> > >
> > > --
> > > 2.35.1
> > >
> >
> >
> >
>
>
>
>
--
Regards,
Atish
Hi Christoph,
Am Montag, 20. Juni 2022, 08:16:07 CEST schrieb Christoph Hellwig:
> On Sun, Jun 19, 2022 at 10:32:11PM +0200, Heiko Stuebner wrote:
> > +#ifdef CONFIG_RISCV_DMA_NONCOHERENT
> > +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
> > +#endif
>
> This needs to be greater or equal to riscv_cbom_block_size, but the
> core code requires a compile time constant here. So we'll need a big
> fat comment here, and panic if riscv_cbom_block_size is >
> L1_CACHE_BYTES/ARCH_DMA_MINALIGN in the code that queries
> riscv_cbom_block_size.
ARM people also had this nice WARN_TAINT to warn when the similar
case happens on ARM64 and the ARCH_DMA_MINALIGN is smaller than
the register value so I've added a similar mechanism.
I've read numerous mails from Torvalds over time that panic-ing should
only ever be the very very last resort, so that WARN_TAINT looks like
a less drastic option while still generating that big warning to users.
> Note that the arm64 folks are looking into making this variable or
> killing it off in this current form, so things might be getting better
> soon.
>
> > +void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> > + enum dma_data_direction dir)
> > +{
> > + void *vaddr = phys_to_virt(paddr);
> > +
> > + switch (dir) {
> > + case DMA_TO_DEVICE:
> > + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> > + break;
> > + case DMA_FROM_DEVICE:
> > + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
> > + break;
>
> For this also see:
>
> https://lore.kernel.org/all/20220606152150.GA31568@willie-the-truck/
>
> and
>
> https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
so from that discussion, it looks like a "clean" should happen here to
prevent stale bytes (not written to by the dma transfer itself) in the
buffer area I guess.
I'll give that a spin :-)
> > +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> > + const struct iommu_ops *iommu, bool coherent)
> > +{
> > + dev->dma_coherent = coherent;
> > +}
>
> This probably wants a sanity check warn if coherent if false without
> any support for cache flushing as that will cause data corruption.
I've added a riscv_noncoherent_supported() call that will track that
"somebody" implemented non-coherence functionality from their
setup function (zicbom_probe, thead_errata-probe) and a matching
second WARN_TAINT in arch_setup_dma_ops() when coherent value
and availability of non-coherence handling is not matched.
Heiko
On 6/19/22 3:32 PM, Heiko Stuebner wrote:
> The T-Head C906 and C910 implement a scheme for handling
> cache operations different from the generic Zicbom extension.
>
> Add an errata for it next to the generic dma coherency ops.
>
> Signed-off-by: Heiko Stuebner <[email protected]>
Thanks for the update!
Reviewed-by: Samuel Holland <[email protected]>
Tested-by: Samuel Holland <[email protected]>