LinuxLists.cc - [PATCH 1/3] mmc: atmel-mci: move atmel-mci-regs.h content in atmel-mci.c

2015-11-23 15:27:16

Subject: [PATCH 1/3] mmc: atmel-mci: move atmel-mci-regs.h content in atmel-mci.c

atmel-mci-regs.h is only included in atmel-mci.c so move its content in
the driver and do some cleanup in these definitions to remove checkpatch
errors.

Signed-off-by: Ludovic Desroches <[email protected]>
---
drivers/mmc/host/atmel-mci-regs.h | 171 --------------------------------------
drivers/mmc/host/atmel-mci.c | 150 ++++++++++++++++++++++++++++++++-
2 files changed, 149 insertions(+), 172 deletions(-)
delete mode 100644 drivers/mmc/host/atmel-mci-regs.h

diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
deleted file mode 100644
index 0aa44e6..0000000
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Atmel MultiMedia Card Interface driver
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*
- * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
- * Registers and bitfields marked with [2] are only available in MCI2
- */
-
-#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
-#define __DRIVERS_MMC_ATMEL_MCI_H__
-
-/* MCI Register Definitions */
-#define ATMCI_CR 0x0000 /* Control */
-# define ATMCI_CR_MCIEN ( 1 << 0) /* MCI Enable */
-# define ATMCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */
-# define ATMCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */
-# define ATMCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */
-# define ATMCI_CR_SWRST ( 1 << 7) /* Software Reset */
-#define ATMCI_MR 0x0004 /* Mode */
-# define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
-# define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
-# define ATMCI_MR_RDPROOF ( 1 << 11) /* Read Proof */
-# define ATMCI_MR_WRPROOF ( 1 << 12) /* Write Proof */
-# define ATMCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */
-# define ATMCI_MR_PDCPADV ( 1 << 14) /* Padding Value */
-# define ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */
-# define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
-#define ATMCI_DTOR 0x0008 /* Data Timeout */
-# define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
-# define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
-#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
-# define ATMCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */
-# define ATMCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */
-# define ATMCI_SDCSEL_MASK ( 3 << 0)
-# define ATMCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */
-# define ATMCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */
-# define ATMCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */
-# define ATMCI_SDCBUS_MASK ( 3 << 6)
-#define ATMCI_ARGR 0x0010 /* Command Argument */
-#define ATMCI_CMDR 0x0014 /* Command */
-# define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
-# define ATMCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */
-# define ATMCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */
-# define ATMCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */
-# define ATMCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */
-# define ATMCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */
-# define ATMCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */
-# define ATMCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */
-# define ATMCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */
-# define ATMCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */
-# define ATMCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */
-# define ATMCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */
-# define ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */
-# define ATMCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */
-# define ATMCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */
-# define ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */
-# define ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */
-# define ATMCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */
-# define ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */
-# define ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */
-# define ATMCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */
-# define ATMCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */
-#define ATMCI_BLKR 0x0018 /* Block */
-# define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
-# define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
-#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
-# define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
-# define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
-#define ATMCI_RSPR 0x0020 /* Response 0 */
-#define ATMCI_RSPR1 0x0024 /* Response 1 */
-#define ATMCI_RSPR2 0x0028 /* Response 2 */
-#define ATMCI_RSPR3 0x002c /* Response 3 */
-#define ATMCI_RDR 0x0030 /* Receive Data */
-#define ATMCI_TDR 0x0034 /* Transmit Data */
-#define ATMCI_SR 0x0040 /* Status */
-#define ATMCI_IER 0x0044 /* Interrupt Enable */
-#define ATMCI_IDR 0x0048 /* Interrupt Disable */
-#define ATMCI_IMR 0x004c /* Interrupt Mask */
-# define ATMCI_CMDRDY ( 1 << 0) /* Command Ready */
-# define ATMCI_RXRDY ( 1 << 1) /* Receiver Ready */
-# define ATMCI_TXRDY ( 1 << 2) /* Transmitter Ready */
-# define ATMCI_BLKE ( 1 << 3) /* Data Block Ended */
-# define ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */
-# define ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */
-# define ATMCI_ENDRX ( 1 << 6) /* End of RX Buffer */
-# define ATMCI_ENDTX ( 1 << 7) /* End of TX Buffer */
-# define ATMCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */
-# define ATMCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */
-# define ATMCI_SDIOWAIT ( 1 << 12) /* SDIO Read Wait Operation Status */
-# define ATMCI_CSRCV ( 1 << 13) /* CE-ATA Completion Signal Received */
-# define ATMCI_RXBUFF ( 1 << 14) /* RX Buffer Full */
-# define ATMCI_TXBUFE ( 1 << 15) /* TX Buffer Empty */
-# define ATMCI_RINDE ( 1 << 16) /* Response Index Error */
-# define ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */
-# define ATMCI_RCRCE ( 1 << 18) /* Response CRC Error */
-# define ATMCI_RENDE ( 1 << 19) /* Response End Bit Error */
-# define ATMCI_RTOE ( 1 << 20) /* Response Time-Out Error */
-# define ATMCI_DCRCE ( 1 << 21) /* Data CRC Error */
-# define ATMCI_DTOE ( 1 << 22) /* Data Time-Out Error */
-# define ATMCI_CSTOE ( 1 << 23) /* Completion Signal Time-out Error */
-# define ATMCI_BLKOVRE ( 1 << 24) /* DMA Block Overrun Error */
-# define ATMCI_DMADONE ( 1 << 25) /* DMA Transfer Done */
-# define ATMCI_FIFOEMPTY ( 1 << 26) /* FIFO Empty Flag */
-# define ATMCI_XFRDONE ( 1 << 27) /* Transfer Done Flag */
-# define ATMCI_ACKRCV ( 1 << 28) /* Boot Operation Acknowledge Received */
-# define ATMCI_ACKRCVE ( 1 << 29) /* Boot Operation Acknowledge Error */
-# define ATMCI_OVRE ( 1 << 30) /* RX Overrun Error */
-# define ATMCI_UNRE ( 1 << 31) /* TX Underrun Error */
-#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
-# define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
-# define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
-# define ATMCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */
-#define ATMCI_CFG 0x0054 /* Configuration[2] */
-# define ATMCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */
-# define ATMCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */
-# define ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */
-# define ATMCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */
-#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
-# define ATMCI_WP_EN ( 1 << 0) /* WP Enable */
-# define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
-#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
-# define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
-# define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
-#define ATMCI_VERSION 0x00FC /* Version */
-#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
-
-/* This is not including the FIFO Aperture on MCI2 */
-#define ATMCI_REGS_SIZE 0x100
-
-/* Register access macros */
-#ifdef CONFIG_AVR32
-#define atmci_readl(port, reg) \
- __raw_readl((port)->regs + reg)
-#define atmci_writel(port, reg, value) \
- __raw_writel((value), (port)->regs + reg)
-#else
-#define atmci_readl(port, reg) \
- readl_relaxed((port)->regs + reg)
-#define atmci_writel(port, reg, value) \
- writel_relaxed((value), (port)->regs + reg)
-#endif
-
-/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
-#ifdef CONFIG_AVR32
-# define ATMCI_PDC_CONNECTED 0
-#else
-# define ATMCI_PDC_CONNECTED 1
-#endif
-
-/*
- * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
- * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
- *
- * This can be done by finding most significant bit set.
- */
-static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
-{
- if (maxburst > 1)
- return fls(maxburst) - 2;
- else
- return 0;
-}
-
-#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index bf62e42..9f3bb61 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -44,7 +44,155 @@
#include <asm/io.h>
#include <asm/unaligned.h>

-#include "atmel-mci-regs.h"
+/*
+ * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
+ * Registers and bitfields marked with [2] are only available in MCI2
+ */
+
+/* MCI Register Definitions */
+#define ATMCI_CR 0x0000 /* Control */
+#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
+#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
+#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
+#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
+#define ATMCI_CR_SWRST BIT(7) /* Software Reset */
+#define ATMCI_MR 0x0004 /* Mode */
+#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
+#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
+#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
+#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
+#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
+#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
+#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
+#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
+#define ATMCI_DTOR 0x0008 /* Data Timeout */
+#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
+#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
+#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
+#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
+#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
+#define ATMCI_SDCSEL_MASK (3 << 0)
+#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
+#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
+#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
+#define ATMCI_SDCBUS_MASK (3 << 6)
+#define ATMCI_ARGR 0x0010 /* Command Argument */
+#define ATMCI_CMDR 0x0014 /* Command */
+#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
+#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
+#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
+#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
+#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
+#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
+#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
+#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
+#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
+#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
+#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
+#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
+#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
+#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
+#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
+#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
+#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
+#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
+#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
+#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
+#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
+#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
+#define ATMCI_BLKR 0x0018 /* Block */
+#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
+#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
+#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
+#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
+#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
+#define ATMCI_RSPR 0x0020 /* Response 0 */
+#define ATMCI_RSPR1 0x0024 /* Response 1 */
+#define ATMCI_RSPR2 0x0028 /* Response 2 */
+#define ATMCI_RSPR3 0x002c /* Response 3 */
+#define ATMCI_RDR 0x0030 /* Receive Data */
+#define ATMCI_TDR 0x0034 /* Transmit Data */
+#define ATMCI_SR 0x0040 /* Status */
+#define ATMCI_IER 0x0044 /* Interrupt Enable */
+#define ATMCI_IDR 0x0048 /* Interrupt Disable */
+#define ATMCI_IMR 0x004c /* Interrupt Mask */
+#define ATMCI_CMDRDY BIT(0) /* Command Ready */
+#define ATMCI_RXRDY BIT(1) /* Receiver Ready */
+#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
+#define ATMCI_BLKE BIT(3) /* Data Block Ended */
+#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
+#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
+#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
+#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
+#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
+#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
+#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
+#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
+#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
+#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
+#define ATMCI_RINDE BIT(16) /* Response Index Error */
+#define ATMCI_RDIRE BIT(17) /* Response Direction Error */
+#define ATMCI_RCRCE BIT(18) /* Response CRC Error */
+#define ATMCI_RENDE BIT(19) /* Response End Bit Error */
+#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
+#define ATMCI_DCRCE BIT(21) /* Data CRC Error */
+#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
+#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
+#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
+#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
+#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
+#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
+#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
+#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
+#define ATMCI_OVRE BIT(30) /* RX Overrun Error */
+#define ATMCI_UNRE BIT(31) /* TX Underrun Error */
+#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
+#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
+#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
+#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
+#define ATMCI_CFG 0x0054 /* Configuration[2] */
+#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
+#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
+#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
+#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
+#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
+#define ATMCI_WP_EN BIT(0) /* WP Enable */
+#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
+#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
+#define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
+#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
+#define ATMCI_VERSION 0x00FC /* Version */
+#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
+
+/* This is not including the FIFO Aperture on MCI2 */
+#define ATMCI_REGS_SIZE 0x100
+
+/* Register access macros */
+#define atmci_readl(port, reg) \
+ __raw_readl((port)->regs + reg)
+#define atmci_writel(port, reg, value) \
+ __raw_writel((value), (port)->regs + reg)
+
+/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
+#ifdef CONFIG_AVR32
+# define ATMCI_PDC_CONNECTED 0
+#else
+# define ATMCI_PDC_CONNECTED 1
+#endif
+
+/*
+ * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
+ * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
+ *
+ * This can be done by finding most significant bit set.
+ */
+static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
+{
+ if (maxburst > 1)
+ return fls(maxburst) - 2;
+ else
+ return 0;
+}

#define AUTOSUSPEND_DELAY 50

--
2.5.0

2015-11-23 15:27:24

by Ludovic Desroches

[permalink] [raw]

Subject: [PATCH 2/3] MAINTAINERS: remove atmel-mci-regs.h file

Remove atmel-mci-regs.h file since it has been merged in atmel-mci.c.

Signed-off-by: Ludovic Desroches <[email protected]>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b2ab9fc..1df3df3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1904,7 +1904,6 @@ ATMEL AT91 / AT32 MCI DRIVER
M: Ludovic Desroches <[email protected]>
S: Maintained
F: drivers/mmc/host/atmel-mci.c
-F: drivers/mmc/host/atmel-mci-regs.h

ATMEL AT91 / AT32 SERIAL DRIVER
M: Nicolas Ferre <[email protected]>
--
2.5.0

2015-11-23 15:27:48

by Ludovic Desroches

[permalink] [raw]

Subject: [PATCH 3/3] mmc: atmel-mci: atmci_convert_chksize depends on controller version

The atmci_convert_chksize() function is no more valid for controller
version 0x600 due to the introduction of '2 data' chunk size.

Signed-off-by: Ludovic Desroches <[email protected]>
---
drivers/mmc/host/atmel-mci.c | 43 +++++++++++++++++++++++++++----------------
1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 9f3bb61..a36ebda 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -180,20 +180,6 @@
# define ATMCI_PDC_CONNECTED 1
#endif

-/*
- * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
- * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
- *
- * This can be done by finding most significant bit set.
- */
-static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
-{
- if (maxburst > 1)
- return fls(maxburst) - 2;
- else
- return 0;
-}
-
#define AUTOSUSPEND_DELAY 50

#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
@@ -732,6 +718,29 @@ static inline unsigned int atmci_get_version(struct atmel_mci *host)
return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
}

+/*
+ * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
+ * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
+ * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
+ * 8 -> 3, 16 -> 4.
+ *
+ * This can be done by finding most significant bit set.
+ */
+static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
+ unsigned int maxburst)
+{
+ unsigned int version = atmci_get_version(host);
+ unsigned int offset = 2;
+
+ if (version >= 0x600)
+ offset = 1;
+
+ if (maxburst > 1)
+ return fls(maxburst) - offset;
+ else
+ return 0;
+}
+
static void atmci_timeout_timer(unsigned long data)
{
struct atmel_mci *host;
@@ -1182,11 +1191,13 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
if (data->flags & MMC_DATA_READ) {
direction = DMA_FROM_DEVICE;
host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
- maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
+ maxburst = atmci_convert_chksize(host,
+ host->dma_conf.src_maxburst);
} else {
direction = DMA_TO_DEVICE;
host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
- maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
+ maxburst = atmci_convert_chksize(host,
+ host->dma_conf.dst_maxburst);
}

if (host->caps.has_dma_conf_reg)
--
2.5.0

2015-11-25 16:33:58

by Ulf Hansson

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Subject: Re: [PATCH 1/3] mmc: atmel-mci: move atmel-mci-regs.h content in atmel-mci.c

On 23 November 2015 at 16:27, <[email protected]> wrote:
included in atmel-mci.c so move its content in
cleanup in these definitions to remove checkpatch
Desroches <[email protected]>
| 171 --------------------------------------
| 150 ++++++++++++++++++++++++++++++++-
insertions(+), 172 deletions(-)
c/host/atmel-mci-regs.h
atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
/> Card Interface driver
Atmel Corporation
software; you can redistribute it and/or modify
of the GNU General Public License version 2 as
Free Software Foundation.
registers integrated in Atmel AVR32 and AT91 Processors
marked with [2] are only available in MCI2
/> /> */
0x0000 /* Control */
( 1 << 0) /* MCI Enable */
( 1 << 1) /* MCI Disable */
( 1 << 2) /* Power Save Enable */
( 1 << 3) /* Power Save Disable */
( 1 << 7) /* Software Reset */
0x0004 /* Mode */
((x) << 0) /* Clock Divider */
((x) << 8) /* Power Saving Divider */
( 1 << 11) /* Read Proof */
( 1 << 12) /* Write Proof */
( 1 << 13) /* Force Byte Transfer */
( 1 << 14) /* Padding Value */
( 1 << 15) /* PDC-oriented Mode */
((x) << 16) /* LSB of Clock Divider */
0x0008 /* Data Timeout */
((x) << 0) /* Data Timeout Cycles */
((x) << 4) /* Data Timeout Multiplier */
0x000c /* SD Card / SDIO */
( 0 << 0) /* Select SD slot A */
( 1 << 0) /* Select SD slot A */
( 3 << 0)
( 0 << 6) /* 1-bit data bus */
( 2 << 6) /* 4-bit data bus */
( 3 << 6) /* 8-bit data bus[2] */
( 3 << 6)
0x0010 /* Command Argument */
0x0014 /* Command */
((x) << 0) /* Command Opcode */
( 0 << 6) /* No response */
( 1 << 6) /* 48-bit response */
( 2 << 6) /* 136-bit response */
( 1 << 8) /* Initialization command */
( 2 << 8) /* Synchronized command */
( 4 << 8) /* Interrupt command */
( 5 << 8) /* Interrupt response */
( 1 << 11) /* Open Drain */
( 0 << 12) /* Max latency 5 cycles */
( 1 << 12) /* Max latency 64 cycles */
( 1 << 16) /* Start data transfer */
( 2 << 16) /* Stop data transfer */
( 0 << 18) /* Write data */
( 1 << 18) /* Read data */
( 0 << 19) /* Single-block transfer */
( 1 << 19) /* Multi-block transfer */
( 2 << 19) /* MMC Stream transfer */
( 4 << 19) /* SDIO Byte transfer */
( 5 << 19) /* SDIO Block transfer */
( 1 << 24) /* SDIO Suspend Command */
( 2 << 24) /* SDIO Resume Command */
0x0018 /* Block */
((x) << 0) /* Data Block Count */
((x) << 16) /* Data Block Length */
0x001c /* Completion Signal Timeout[2] */
((x) << 0) /* CST cycles */
((x) << 4) /* CST multiplier */
0x0020 /* Response 0 */
0x0024 /* Response 1 */
0x0028 /* Response 2 */
0x002c /* Response 3 */
0x0030 /* Receive Data */
0x0034 /* Transmit Data */
0x0040 /* Status */
0x0044 /* Interrupt Enable */
0x0048 /* Interrupt Disable */
0x004c /* Interrupt Mask */
( 1 << 0) /* Command Ready */
( 1 << 1) /* Receiver Ready */
( 1 << 2) /* Transmitter Ready */
( 1 << 3) /* Data Block Ended */
( 1 << 4) /* Data Transfer In Progress */
( 1 << 5) /* Data Not Busy */
( 1 << 6) /* End of RX Buffer */
( 1 << 7) /* End of TX Buffer */
( 1 << 8) /* SDIO IRQ in slot A */
( 1 << 9) /* SDIO IRQ in slot B */
( 1 << 12) /* SDIO Read Wait Operation Status */
( 1 << 13) /* CE-ATA Completion Signal Received */
( 1 << 14) /* RX Buffer Full */
( 1 << 15) /* TX Buffer Empty */
( 1 << 16) /* Response Index Error */
( 1 << 17) /* Response Direction Error */
( 1 << 18) /* Response CRC Error */
( 1 << 19) /* Response End Bit Error */
( 1 << 20) /* Response Time-Out Error */
( 1 << 21) /* Data CRC Error */
( 1 << 22) /* Data Time-Out Error */
( 1 << 23) /* Completion Signal Time-out Error */
( 1 << 24) /* DMA Block Overrun Error */
( 1 << 25) /* DMA Transfer Done */
( 1 << 26) /* FIFO Empty Flag */
( 1 << 27) /* Transfer Done Flag */
( 1 << 28) /* Boot Operation Acknowledge Received */
( 1 << 29) /* Boot Operation Acknowledge Error */
( 1 << 30) /* RX Overrun Error */
( 1 << 31) /* TX Underrun Error */
0x0050 /* DMA Configuration[2] */
((x) << 0) /* DMA Write Buffer Offset */
((x) << 4) /* DMA Channel Read and Write Chunk Size */
( 1 << 8) /* DMA Hardware Handshaking Enable */
0x0054 /* Configuration[2] */
( 1 << 0) /* MCI Internal FIFO control mode */
( 1 << 4) /* Flow Error flag reset control mode */
( 1 << 8) /* High Speed Mode */
( 1 << 12) /* Synchronize on the last block */
0x00e4 /* Write Protection Mode[2] */
( 1 << 0) /* WP Enable */
(0x4d4349 << 8) /* WP Key */
0x00e8 /* Write Protection Status[2] */
((x) & 0x0f)
(((x) >> 8) & 0xffff)
0x00FC /* Version */
0x0200 /* FIFO Aperture[2] */
the FIFO Aperture on MCI2 */
0x100
*/
\
+ reg)
\
(port)->regs + reg)
\
+ reg)
\
(port)->regs + reg)
Peripheral DMA Controller is not connected to MCI. */
0
1
size according to atmel MCI. We need to convert them as:
1, 8 -> 2, 16 -> 3.
by finding most significant bit set.
int atmci_convert_chksize(unsigned int maxburst)
fls(maxburst) - 2;
*/
b/drivers/mmc/host/atmel-mci.c
100644
/> /> /> /> registers integrated in Atmel AVR32 and AT91 Processors
marked with [2] are only available in MCI2
*/
0x0000 /* Control */
BIT(0) /* MCI Enable */
BIT(1) /* MCI Disable */
BIT(2) /* Power Save Enable */
BIT(3) /* Power Save Disable */
BIT(7) /* Software Reset */
0x0004 /* Mode */
ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
0x0008 /* Data Timeout */
((x) << 0) /* Data Timeout Cycles */
((x) << 4) /* Data Timeout Multiplier */
0x000c /* SD Card / SDIO */
ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
ATMCI_SDCSEL_MASK (3 << 0)
ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
ATMCI_SDCBUS_MASK (3 << 6)
0x0010 /* Command Argument */
0x0014 /* Command */
ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
0x0018 /* Block */
((x) << 0) /* Data Block Count */
((x) << 16) /* Data Block Length */
0x001c /* Completion Signal Timeout[2] */
ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
0x0020 /* Response 0 */
0x0024 /* Response 1 */
0x0028 /* Response 2 */
0x002c /* Response 3 */
0x0030 /* Receive Data */
0x0034 /* Transmit Data */
0x0040 /* Status */
0x0044 /* Interrupt Enable */
0x0048 /* Interrupt Disable */
0x004c /* Interrupt Mask */
BIT(0) /* Command Ready */
BIT(1) /* Receiver Ready */
BIT(2) /* Transmitter Ready */
BIT(3) /* Data Block Ended */
BIT(4) /* Data Transfer In Progress */
BIT(5) /* Data Not Busy */
BIT(6) /* End of RX Buffer */
BIT(7) /* End of TX Buffer */
BIT(8) /* SDIO IRQ in slot A */
BIT(9) /* SDIO IRQ in slot B */
BIT(12) /* SDIO Read Wait Operation Status */
BIT(13) /* CE-ATA Completion Signal Received */
BIT(14) /* RX Buffer Full */
BIT(15) /* TX Buffer Empty */
BIT(16) /* Response Index Error */
BIT(17) /* Response Direction Error */
BIT(18) /* Response CRC Error */
BIT(19) /* Response End Bit Error */
BIT(20) /* Response Time-Out Error */
BIT(21) /* Data CRC Error */
BIT(22) /* Data Time-Out Error */
BIT(23) /* Completion Signal Time-out Error */
BIT(24) /* DMA Block Overrun Error */
BIT(25) /* DMA Transfer Done */
BIT(26) /* FIFO Empty Flag */
BIT(27) /* Transfer Done Flag */
BIT(28) /* Boot Operation Acknowledge Received */
BIT(29) /* Boot Operation Acknowledge Error */
BIT(30) /* RX Overrun Error */
BIT(31) /* TX Underrun Error */
0x0050 /* DMA Configuration[2] */
ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
BIT(8) /* DMA Hardware Handshaking Enable */
0x0054 /* Configuration[2] */
ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
BIT(12) /* Synchronize on the last block */
0x00e4 /* Write Protection Mode[2] */
BIT(0) /* WP Enable */
(0x4d4349 << 8) /* WP Key */
0x00e8 /* Write Protection Status[2] */
ATMCI_GET_WP_VS(x) ((x) & 0x0f)
ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
0x00FC /* Version */
0x0200 /* FIFO Aperture[2] */
the FIFO Aperture on MCI2 */
0x100
*/
\
+ reg)
reg, value) \
(port)->regs + reg)
Peripheral DMA Controller is not connected to MCI. */
0
1
size according to atmel MCI. We need to convert them as:
1, 8 -> 2, 16 -> 3.
by finding most significant bit set.
int atmci_convert_chksize(unsigned int maxburst)
fls(maxburst) - 2;
50

2015-11-25 16:35:18

by Ulf Hansson

[permalink] [raw]

Subject: Re: [PATCH 2/3] MAINTAINERS: remove atmel-mci-regs.h file

On 23 November 2015 at 16:27, Ludovic Desroches
<[email protected]> wrote:
> Remove atmel-mci-regs.h file since it has been merged in atmel-mci.c.
>
> Signed-off-by: Ludovic Desroches <[email protected]>

Thanks, applied for next!

Kind regards
Uffe

> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b2ab9fc..1df3df3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1904,7 +1904,6 @@ ATMEL AT91 / AT32 MCI DRIVER
> M: Ludovic Desroches <[email protected]>
> S: Maintained
> F: drivers/mmc/host/atmel-mci.c
> -F: drivers/mmc/host/atmel-mci-regs.h
>
> ATMEL AT91 / AT32 SERIAL DRIVER
> M: Nicolas Ferre <[email protected]>
> --
> 2.5.0
>

2015-11-25 16:34:03

by Ulf Hansson

[permalink] [raw]

Subject: Re: [PATCH 3/3] mmc: atmel-mci: atmci_convert_chksize depends on controller version

On 23 November 2015 at 16:27, Ludovic Desroches
<[email protected]> wrote:
> The atmci_convert_chksize() function is no more valid for controller
> version 0x600 due to the introduction of '2 data' chunk size.
>
> Signed-off-by: Ludovic Desroches <[email protected]>

Thanks, applied for next!

Kind regards
Uffe

> ---
> drivers/mmc/host/atmel-mci.c | 43 +++++++++++++++++++++++++++----------------
> 1 file changed, 27 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index 9f3bb61..a36ebda 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -180,20 +180,6 @@
> # define ATMCI_PDC_CONNECTED 1
> #endif
>
> -/*
> - * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
> - * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
> - *
> - * This can be done by finding most significant bit set.
> - */
> -static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
> -{
> - if (maxburst > 1)
> - return fls(maxburst) - 2;
> - else
> - return 0;
> -}
> -
> #define AUTOSUSPEND_DELAY 50
>
> #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
> @@ -732,6 +718,29 @@ static inline unsigned int atmci_get_version(struct atmel_mci *host)
> return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
> }
>
> +/*
> + * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
> + * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
> + * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
> + * 8 -> 3, 16 -> 4.
> + *
> + * This can be done by finding most significant bit set.
> + */
> +static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
> + unsigned int maxburst)
> +{
> + unsigned int version = atmci_get_version(host);
> + unsigned int offset = 2;
> +
> + if (version >= 0x600)
> + offset = 1;
> +
> + if (maxburst > 1)
> + return fls(maxburst) - offset;
> + else
> + return 0;
> +}
> +
> static void atmci_timeout_timer(unsigned long data)
> {
> struct atmel_mci *host;
> @@ -1182,11 +1191,13 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
> if (data->flags & MMC_DATA_READ) {
> direction = DMA_FROM_DEVICE;
> host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
> - maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
> + maxburst = atmci_convert_chksize(host,
> + host->dma_conf.src_maxburst);
> } else {
> direction = DMA_TO_DEVICE;
> host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
> - maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
> + maxburst = atmci_convert_chksize(host,
> + host->dma_conf.dst_maxburst);
> }
>
> if (host->caps.has_dma_conf_reg)
> --
> 2.5.0
>