Select CONFIG_CPU_NO_EFFICIENT_FFS via Kconfig when the kernel is
configured for a pre-MIPS32r1 CPU, rather than defining its equivalent
in asm/cpu-features.h based upon overrides of cpu_has_mips* macros.
The latter only works if a platform has an cpu-feature-overrides.h
header which defines cpu_has_mips* macros, which are not generally
needed. There are many cases where we know that the target ISA for a
kernel build is MIPS32r1 or later & thus includes the CLZ instruction,
without requiring any overrides from the platform. Using Kconfig allows
us to take those into account, and more naturally make a decision about
instruction support using information about the target ISA.
Signed-off-by: Paul Burton <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Zhaoxiu Zeng <[email protected]>
---
arch/mips/Kconfig | 13 ++++++++++++-
arch/mips/include/asm/cpu-features.h | 10 ----------
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 71aaa5bcd805..6696eadf7267 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -15,6 +15,7 @@ config MIPS
select ARCH_WANT_IPC_PARSE_VERSION
select BUILDTIME_EXTABLE_SORT
select CLONE_BACKWARDS
+ select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
select CPU_PM if CPU_IDLE
select DMA_DIRECT_OPS
select GENERIC_ATOMIC64 if !64BIT
@@ -2032,7 +2033,7 @@ config CPU_MIPS64
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
#
-# These two indicate the revision of the architecture, either Release 1 or Release 2
+# These indicate the revision of the architecture
#
config CPU_MIPSR1
bool
@@ -2053,6 +2054,16 @@ config CPU_MIPSR6
select MIPS_CRC_SUPPORT
select MIPS_SPRAM
+config TARGET_ISA_REV
+ int
+ default 1 if CPU_MIPSR1
+ default 2 if CPU_MIPSR2
+ default 6 if CPU_MIPSR6
+ default 0
+ help
+ Reflects the ISA revision being targeted by the kernel build. This
+ is effectively the Kconfig equivalent of MIPS_ISA_REV.
+
config EVA
bool
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1f3f7453c1d2..83a27af8ada6 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -261,16 +261,6 @@
#endif
#endif
-/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
-#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
- (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
- (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
- (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
- (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
- (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
-#define CPU_NO_EFFICIENT_FFS 1
-#endif
-
#ifndef cpu_has_mips_1
# define cpu_has_mips_1 (MIPS_ISA_REV < 6)
#endif
--
2.19.1
The CPU_NO_EFFICIENT_FFS pre-processor macro is no longer used, with all
architectures toggling the equivalent Kconfig symbol
CONFIG_CPU_NO_EFFICIENT_FFS instead. Remove our check for the unused
macro.
Signed-off-by: Paul Burton <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Zhaoxiu Zeng <[email protected]>
---
lib/gcd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/gcd.c b/lib/gcd.c
index 227dea924425..7948ab27f0a4 100644
--- a/lib/gcd.c
+++ b/lib/gcd.c
@@ -10,7 +10,7 @@
* has decent hardware division.
*/
-#if !defined(CONFIG_CPU_NO_EFFICIENT_FFS) && !defined(CPU_NO_EFFICIENT_FFS)
+#if !defined(CONFIG_CPU_NO_EFFICIENT_FFS)
/* If __ffs is available, the even/odd algorithm benchmarks slower. */
--
2.19.1
Hello,
Paul Burton wrote:
> Select CONFIG_CPU_NO_EFFICIENT_FFS via Kconfig when the kernel is
> configured for a pre-MIPS32r1 CPU, rather than defining its equivalent
> in asm/cpu-features.h based upon overrides of cpu_has_mips* macros.
>
> The latter only works if a platform has an cpu-feature-overrides.h
> header which defines cpu_has_mips* macros, which are not generally
> needed. There are many cases where we know that the target ISA for a
> kernel build is MIPS32r1 or later & thus includes the CLZ instruction,
> without requiring any overrides from the platform. Using Kconfig allows
> us to take those into account, and more naturally make a decision about
> instruction support using information about the target ISA.
>
> Signed-off-by: Paul Burton <[email protected]>
> Cc: Andrew Morton <[email protected]>
> Cc: Zhaoxiu Zeng <[email protected]>
Series applied to mips-next.
Thanks,
Paul
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