Huashan Pi board is an embedded development platform based on the
CV1812H chip. Add minimal device tree files for this board.
Currently, it can boot to a basic shell.
NOTE: this series is based on the Jisheng's Milk-V Duo patch.
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Link: https://lore.kernel.org/linux-riscv/[email protected]/
Changed from v2:
1. use dt override to save code.
2. code cleanup.
Changed from v1:
1. split the patch into several patch and refactor them.
Inochi Amaoto (8):
dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
dt-bindings: timer: Add SOPHGO CV1812H clint
dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
riscv: dts: sophgo: Rename cv1800b device tree file
riscv: dts: sophgo: Separate compatible specific for cv1800b soc
riscv: dts: sophgo: cv18xx: Add gpio devices
riscv: dts: sophgo: add initial CV1812H SoC device tree
riscv: dts: sophgo: add Huashan Pi board device tree
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/sophgo.yaml | 4 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 1 +
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 +----------
.../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 +++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 193 ++++++++++++++++++
8 files changed, 279 insertions(+), 112 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi
--
2.42.0
Add compatible string for SOPHGO CV1812H plic.
Signed-off-by: Inochi Amaoto <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 0c07e8dda445..709b2211276b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
+ - sophgo,cv1812h-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
--
2.42.0
Add compatible string for the SOPHGO CV1812H clint.
Signed-off-by: Inochi Amaoto <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index e8be6c470364..4b6c20fc8194 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -38,6 +38,7 @@ properties:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
+ - sophgo,cv1812h-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:
--
2.42.0
Move the cv1800b soc specific compatible out of the common file.
Signed-off-by: Inochi Amaoto <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 18 ++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 3 ---
2 files changed, 18 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
new file mode 100644
index 000000000000..165e9e320a8c
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,cv1800b";
+};
+
+&plic {
+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+};
+
+&clint {
+ compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index df40e87ee063..55d4bc84faa0 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -6,7 +6,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
- compatible = "sophgo,cv1800b";
#address-cells = <1>;
#size-cells = <1>;
@@ -105,7 +104,6 @@ uart4: serial@41c0000 {
};
plic: interrupt-controller@70000000 {
- compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
@@ -115,7 +113,6 @@ plic: interrupt-controller@70000000 {
};
clint: timer@74000000 {
- compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
--
2.42.0
Document the compatible strings for the SOPHGO Huashan Pi board which
uses the SOPHGO CV1812H SoC.
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Acked-by: Chen Wang <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index 86748c5390be..9bc813dad098 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -22,6 +22,10 @@ properties:
- enum:
- milkv,duo
- const: sophgo,cv1800b
+ - items:
+ - enum:
+ - sophgo,huashan-pi
+ - const: sophgo,cv1812h
- items:
- enum:
- milkv,pioneer
--
2.42.0
As CV180x and CV181x have the identical layouts, it is OK to use the
cv1800b basic device tree for the whole series.
Signed-off-by: Inochi Amaoto <[email protected]>
---
arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} (100%)
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
similarity index 100%
rename from arch/riscv/boot/dts/sophgo/cv1800b.dtsi
rename to arch/riscv/boot/dts/sophgo/cv18xx.dtsi
--
2.42.0
Add common GPIO devices for the CV180x and CV181x soc.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 73 ++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 55d4bc84faa0..d415cc758def 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ * Copyright (C) 2023 Inochi Amaoto <[email protected]>
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -53,6 +54,78 @@ soc {
dma-noncoherent;
ranges;
+ gpio0: gpio@3020000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@3021000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3021000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio2: gpio@3022000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3022000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@3023000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3023000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
--
2.42.0
Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
Signed-off-by: Inochi Amaoto <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
new file mode 100644
index 000000000000..3e7a942f5c1a
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,cv1812h";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&plic {
+ compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+};
+
+&clint {
+ compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+};
--
2.42.0
Add initial device tree files for the Huashan Pi board.
Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to
function properly. To make the soc happy, reserved the last 2M memory
for the rtos firmware.
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15
Reviewed-by: Jisheng Zhang <[email protected]>
---
arch/riscv/boot/dts/sophgo/Makefile | 1 +
.../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++++++++++++++++
2 files changed, 49 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 3fb65512c631..57ad82a61ea6 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
new file mode 100644
index 000000000000..aa361f3a86bb
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "cv1812h.dtsi"
+
+/ {
+ model = "Huashan Pi";
+ compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ coprocessor_rtos: region@8fe00000 {
+ reg = <0x8fe00000 0x200000>;
+ no-map;
+ };
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.42.0
On 18/10/2023 13:31, Inochi Amaoto wrote:
> As CV180x and CV181x have the identical layouts, it is OK to use the
> cv1800b basic device tree for the whole series.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} (100%)
>
If nothing breaks by this commit, means the file is not used, so how did
it end up in the kernel?
Best regards,
Krzysztof
>On 18/10/2023 13:31, Inochi Amaoto wrote:
>> As CV180x and CV181x have the identical layouts, it is OK to use the
>> cv1800b basic device tree for the whole series.
>>
>> Signed-off-by: Inochi Amaoto <[email protected]>
>> ---
>> arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} | 0
>> 1 file changed, 0 insertions(+), 0 deletions(-)
>> rename arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} (100%)
>>
>
>If nothing breaks by this commit, means the file is not used, so how did
>it end up in the kernel?
>
This commit breaks the including file cv1800b-milkv-duo.dts, which is
fixed in the next patch. For cv1800b, it only needs to set compatible
strings. The cv1800b and cv1812h have identical layout.
I use this commit to avoid wired output provided by git and make the
change more clear.
>
>Best regards,
>Krzysztof
>
>
On 18/10/2023 14:37, Inochi Amaoto wrote:
>> On 18/10/2023 13:31, Inochi Amaoto wrote:
>>> As CV180x and CV181x have the identical layouts, it is OK to use the
>>> cv1800b basic device tree for the whole series.
>>>
>>> Signed-off-by: Inochi Amaoto <[email protected]>
>>> ---
>>> arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} | 0
>>> 1 file changed, 0 insertions(+), 0 deletions(-)
>>> rename arch/riscv/boot/dts/sophgo/{cv1800b.dtsi => cv18xx.dtsi} (100%)
>>>
>>
>> If nothing breaks by this commit, means the file is not used, so how did
>> it end up in the kernel?
>>
>
> This commit breaks the including file cv1800b-milkv-duo.dts, which is
> fixed in the next patch. For cv1800b, it only needs to set compatible
> strings. The cv1800b and cv1812h have identical layout.
You must preserve bisectability.
>
> I use this commit to avoid wired output provided by git and make the
> change more clear.
Don't do this. Previous patch was ok and readable. I don't understand
how this split helps (except breaking bisectability).
Best regards,
Krzysztof