This series adds FPGA Manager support for the Xilinx
Versal chip.
Appana Durga Kedareswara rao (1):
dt-bindings: fpga: Add binding doc for versal fpga manager
Nava kishore Manne (2):
drivers: firmware: Add PDI load API support
fpga: versal-fpga: Add versal fpga manager driver
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++++
drivers/firmware/xilinx/zynqmp.c | 17 +++
drivers/fpga/Kconfig | 9 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 117 ++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 10 ++
6 files changed, 187 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
create mode 100644 drivers/fpga/versal-fpga.c
--
2.18.0
This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v2:
-Updated API Doc and commit msg.
No functional changes.
Changes for v3:
-Added PDI_SRC_DDR macro in the firmware.h file.
drivers/firmware/xilinx/zynqmp.c | 17 +++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 7eb9958662dd..9ee02655db89 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -897,6 +897,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src: Source device where PDI is located
+ * @address: PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+ lower_32_bits(address),
+ upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
/**
* zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
* AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 2a0da841c942..3eba9d5c7640 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,10 @@
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+/* Loader commands */
+#define PM_LOAD_PDI 0x701
+#define PDI_SRC_DDR 0xF
+
/*
* Firmware FPGA Manager flags
* XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
@@ -354,6 +358,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -538,6 +543,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.18.0
From: Appana Durga Kedareswara rao <[email protected]>
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne <[email protected]>
Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
---
Changes for v2:
-Fixed file format and syntax issues.
Changes for v3:
-Removed unwated extra spaces.
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index 000000000000..fec6144766fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal FPGA driver.
+
+maintainers:
+ - Nava kishore Manne <[email protected]>
+
+description: |
+ Device Tree Versal FPGA bindings for the Versal SoC, controlled
+ using firmware interface.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,versal-fpga
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ versal_fpga: fpga {
+ compatible = "xlnx,versal-fpga";
+ };
+
+...
--
2.18.0
Add support for Xilinx Versal FPGA manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v2:
-Updated the Fpga Mgr registrations call's
to 5.11
-Fixed some minor coding issues as suggested by
Moritz.
Changes for v3:
-Rewritten the Versal fpga Kconfig contents.
drivers/fpga/Kconfig | 9 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++
3 files changed, 127 insertions(+)
create mode 100644 drivers/fpga/versal-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index bf85b9a65ec2..c1603c7e1518 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -223,4 +223,13 @@ config FPGA_MGR_ZYNQMP_FPGA
to configure the programmable logic(PL) through PS
on ZynqMP SoC.
+config FPGA_MGR_VERSAL_FPGA
+ tristate "Xilinx Versal FPGA"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ help
+ Select this option to enable FPGA manager driver support for
+ Xilinx Versal SoC. This driver uses the firmware interface to
+ configure the programmable logic(PL).
+
+ To compile this as a module, choose M here.
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index d8e21dfc6778..40c9adb6a644 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index 000000000000..5744e44f981d
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/**
+ * struct versal_fpga_priv - Private data structure
+ * @dev: Device data structure
+ */
+struct versal_fpga_priv {
+ struct device *dev;
+};
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+ const char *buf, size_t size)
+{
+ struct versal_fpga_priv *priv;
+ dma_addr_t dma_addr = 0;
+ char *kbuf;
+ int ret;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+ .state = versal_fpga_ops_state,
+ .write_init = versal_fpga_ops_write_init,
+ .write = versal_fpga_ops_write,
+ .write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct versal_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret < 0) {
+ dev_err(dev, "no usable DMA configuration\n");
+ return ret;
+ }
+
+ mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+ &versal_fpga_ops, priv);
+ if (!mgr)
+ return -ENOMEM;
+
+ return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+ { .compatible = "xlnx,versal-fpga", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_driver versal_fpga_driver = {
+ .probe = versal_fpga_probe,
+ .driver = {
+ .name = "versal_fpga_manager",
+ .of_match_table = of_match_ptr(versal_fpga_of_match),
+ },
+};
+module_platform_driver(versal_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <[email protected]>");
+MODULE_AUTHOR("Appana Durga Kedareswara rao <[email protected]>");
+MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
+MODULE_LICENSE("GPL");
--
2.18.0
On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne wrote:
> From: Appana Durga Kedareswara rao <[email protected]>
>
> This patch adds binding doc for versal fpga manager driver.
Why do you need a DT entry for this? Can't the Versal firmware driver
instantiate the fpga-mgr device?
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
> ---
> Changes for v2:
> -Fixed file format and syntax issues.
> Changes for v3:
> -Removed unwated extra spaces.
>
> .../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> new file mode 100644
> index 000000000000..fec6144766fe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> @@ -0,0 +1,33 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx Versal FPGA driver.
> +
> +maintainers:
> + - Nava kishore Manne <[email protected]>
> +
> +description: |
> + Device Tree Versal FPGA bindings for the Versal SoC, controlled
> + using firmware interface.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - xlnx,versal-fpga
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + versal_fpga: fpga {
> + compatible = "xlnx,versal-fpga";
> + };
> +
> +...
> --
> 2.18.0
>
Hi Rob,
Thanks for providing the review comments.
Please find my response inline.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Tuesday, March 9, 2021 1:50 AM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; [email protected]; Michal Simek <[email protected]>;
> [email protected]; Jolly Shah <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected]; Manish Narani
> <[email protected]>; Amit Sunil Dhamne <[email protected]>; Tejas
> Patel <[email protected]>; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Appana Durga
> Kedareswara Rao <[email protected]>
> Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga
> manager
>
> On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne wrote:
> > From: Appana Durga Kedareswara rao <[email protected]>
> >
> > This patch adds binding doc for versal fpga manager driver.
>
> Why do you need a DT entry for this? Can't the Versal firmware driver
> instantiate the fpga-mgr device?
>
This dt entry is need to handle the fpga regions properly for both full and Partial bitstream loading use cases and it cannot be done by Versal firmware driver instantiate.
Complete firmware DT node example is shown below for your reference.
Example for full FPGA configuration:
fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&versal_fpga>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
versal_fpga: fpga {
compatible = "xlnx,versal-fpga";
};
};
};
Please correct me if my understanding is wrong...
Regards,
Navakishore.
On Wed, Mar 10, 2021 at 3:50 AM Nava kishore Manne <[email protected]> wrote:
>
> Hi Rob,
>
> Thanks for providing the review comments.
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring <[email protected]>
> > Sent: Tuesday, March 9, 2021 1:50 AM
> > To: Nava kishore Manne <[email protected]>
> > Cc: [email protected]; [email protected]; Michal Simek <[email protected]>;
> > [email protected]; Jolly Shah <[email protected]>; Rajan Vaja
> > <[email protected]>; [email protected]; Manish Narani
> > <[email protected]>; Amit Sunil Dhamne <[email protected]>; Tejas
> > Patel <[email protected]>; [email protected];
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; [email protected]; Appana Durga
> > Kedareswara Rao <[email protected]>
> > Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga
> > manager
> >
> > On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne wrote:
> > > From: Appana Durga Kedareswara rao <[email protected]>
> > >
> > > This patch adds binding doc for versal fpga manager driver.
> >
> > Why do you need a DT entry for this? Can't the Versal firmware driver
> > instantiate the fpga-mgr device?
> >
> This dt entry is need to handle the fpga regions properly for both full and Partial bitstream loading use cases and it cannot be done by Versal firmware driver instantiate.
Ah yes, I forgot about that.
Rob
On Wed, Mar 10, 2021 at 10:12 AM Rob Herring <[email protected]> wrote:
>
> On Wed, Mar 10, 2021 at 3:50 AM Nava kishore Manne <[email protected]> wrote:
> >
> > Hi Rob,
> >
> > Thanks for providing the review comments.
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Rob Herring <[email protected]>
> > > Sent: Tuesday, March 9, 2021 1:50 AM
> > > To: Nava kishore Manne <[email protected]>
> > > Cc: [email protected]; [email protected]; Michal Simek <[email protected]>;
> > > [email protected]; Jolly Shah <[email protected]>; Rajan Vaja
> > > <[email protected]>; [email protected]; Manish Narani
> > > <[email protected]>; Amit Sunil Dhamne <[email protected]>; Tejas
> > > Patel <[email protected]>; [email protected];
> > > [email protected]; [email protected]; linux-arm-
> > > [email protected]; [email protected]; Appana Durga
> > > Kedareswara Rao <[email protected]>
> > > Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga
> > > manager
> > >
> > > On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne wrote:
> > > > From: Appana Durga Kedareswara rao <[email protected]>
> > > >
> > > > This patch adds binding doc for versal fpga manager driver.
> > >
> > > Why do you need a DT entry for this? Can't the Versal firmware driver
> > > instantiate the fpga-mgr device?
> > >
> > This dt entry is need to handle the fpga regions properly for both full and Partial bitstream loading use cases and it cannot be done by Versal firmware driver instantiate.
>
> Ah yes, I forgot about that.
Looking at this some more, please convert xlnx,zynqmp-firmware.txt to
schema and add the node for this there. We don't need a whole other
schema file just for a node and compatible. Also, looks like
xlnx,zynqmp-pcap-fpga.txt is the prior version of the same thing, so
it should be handled in the schema too.
Rob
Hi Rob,
Please find my response inline.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Wednesday, March 10, 2021 10:50 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; [email protected]; Michal Simek <[email protected]>;
> [email protected]; Jolly Shah <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected]; Manish Narani
> <[email protected]>; Amit Sunil Dhamne <[email protected]>; Tejas
> Patel <[email protected]>; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Appana Durga
> Kedareswara Rao <[email protected]>
> Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga
> manager
>
> On Wed, Mar 10, 2021 at 10:12 AM Rob Herring <[email protected]> wrote:
> >
> > On Wed, Mar 10, 2021 at 3:50 AM Nava kishore Manne
> <[email protected]> wrote:
> > >
> > > Hi Rob,
> > >
> > > Thanks for providing the review comments.
> > > Please find my response inline.
> > >
> > > > -----Original Message-----
> > > > From: Rob Herring <[email protected]>
> > > > Sent: Tuesday, March 9, 2021 1:50 AM
> > > > To: Nava kishore Manne <[email protected]>
> > > > Cc: [email protected]; [email protected]; Michal Simek
> > > > <[email protected]>; [email protected]; Jolly Shah
> > > > <[email protected]>; Rajan Vaja <[email protected]>;
> > > > [email protected]; Manish Narani <[email protected]>; Amit Sunil
> > > > Dhamne <[email protected]>; Tejas Patel
> > > > <[email protected]>; [email protected];
> > > > [email protected]; [email protected];
> > > > linux-arm- [email protected]; [email protected];
> > > > Appana Durga Kedareswara Rao <[email protected]>
> > > > Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for
> > > > versal fpga manager
> > > >
> > > > On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne
> wrote:
> > > > > From: Appana Durga Kedareswara rao
> <[email protected]>
> > > > >
> > > > > This patch adds binding doc for versal fpga manager driver.
> > > >
> > > > Why do you need a DT entry for this? Can't the Versal firmware
> > > > driver instantiate the fpga-mgr device?
> > > >
> > > This dt entry is need to handle the fpga regions properly for both full and
> Partial bitstream loading use cases and it cannot be done by Versal firmware
> driver instantiate.
> >
> > Ah yes, I forgot about that.
>
> Looking at this some more, please convert xlnx,zynqmp-firmware.txt to
> schema and add the node for this there. We don't need a whole other
> schema file just for a node and compatible. Also, looks like xlnx,zynqmp-
> pcap-fpga.txt is the prior version of the same thing, so it should be handled
> in the schema too.
>
Will fix this in the next version
Regards,
Navakishore.